Attachment #357165 for bug #596844

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Lines 98-104 const static struct intel_device_info intel_i965g_info = { Link Here

(-)a/drivers/gpu/drm/i915/i915_drv.c (-2 / +2 lines)
98		98
99	const static struct intel_device_info intel_i965gm_info = {	99	const static struct intel_device_info intel_i965gm_info = {
100	.is_i965g = 1, .is_mobile = 1, .is_i965gm = 1, .is_i9xx = 1,	100	.is_i965g = 1, .is_mobile = 1, .is_i965gm = 1, .is_i9xx = 1,
101	.is_mobile = 1, .has_fbc = 1, .has_rc6 = 1,	101	.is_mobile = 1, .has_rc6 = 1,
102	.has_hotplug = 1,	102	.has_hotplug = 1,
103	};	103	};
104		104
Lines 115-121 const static struct intel_device_info intel_g45_info = { Link Here
115		115
116	const static struct intel_device_info intel_gm45_info = {	116	const static struct intel_device_info intel_gm45_info = {
117	.is_i965g = 1, .is_mobile = 1, .is_g4x = 1, .is_i9xx = 1,	117	.is_i965g = 1, .is_mobile = 1, .is_g4x = 1, .is_i9xx = 1,
118	.is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1,	118	.is_mobile = 1, .need_gfx_hws = 1, .has_rc6 = 1,
119	.has_pipe_cxsr = 1,	119	.has_pipe_cxsr = 1,
120	.has_hotplug = 1,	120	.has_hotplug = 1,
121	};	121	};




	else
		dev_priv->display.dpms = i9xx_crtc_dpms;

	/* Only mobile has FBC, leave pointers NULL for other chips */
	if (IS_MOBILE(dev)) {
		if (IS_GM45(dev)) {
			dev_priv->display.fbc_enabled = g4x_fbc_enabled;
			dev_priv->display.enable_fbc = g4x_enable_fbc;
			dev_priv->display.disable_fbc = g4x_disable_fbc;
		} else if (IS_I965GM(dev)) {
			dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
			dev_priv->display.enable_fbc = i8xx_enable_fbc;
			dev_priv->display.disable_fbc = i8xx_disable_fbc;
		}
		/* 855GM needs testing */
	}

	/* Returns the core display clock speed */
	if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
		dev_priv->display.get_display_clock_speed =

Return to bug 596844

Lines 4809-4828 static void intel_init_display(struct drm_device *dev) Link Here

(-)a/drivers/gpu/drm/i915/intel_display.c (-14 lines)
4809	else	4809	else
4810	dev_priv->display.dpms = i9xx_crtc_dpms;	4810	dev_priv->display.dpms = i9xx_crtc_dpms;
4811		4811
4812	/* Only mobile has FBC, leave pointers NULL for other chips */
4813	if (IS_MOBILE(dev)) {
4814	if (IS_GM45(dev)) {
4815	dev_priv->display.fbc_enabled = g4x_fbc_enabled;
4816	dev_priv->display.enable_fbc = g4x_enable_fbc;
4817	dev_priv->display.disable_fbc = g4x_disable_fbc;
4818	} else if (IS_I965GM(dev)) {
4819	dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
4820	dev_priv->display.enable_fbc = i8xx_enable_fbc;
4821	dev_priv->display.disable_fbc = i8xx_disable_fbc;
4822	}
4823	/* 855GM needs testing */
4824	}
4825
4826	/* Returns the core display clock speed */	4812	/* Returns the core display clock speed */
4827	if (IS_I945G(dev) \|\| (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))	4813	if (IS_I945G(dev) \|\| (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
4828	dev_priv->display.get_display_clock_speed =	4814	dev_priv->display.get_display_clock_speed =