Attachment 48902 Details for Bug 114144

[patch] The requested patch

diff.i810_alanh (text/plain), 3.24 KB, created by Egbert Eich on 2005-09-06 10:58:02 UTC

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Creator: Egbert Eich

Created: 2005-09-06 10:58:02 UTC

Size: 3.24 KB

patch

obsolete

>Common subdirectories: i810.orig/CVS and i810/CVS
>diff -u i810.orig/Imakefile i810/Imakefile
>--- i810.orig/Imakefile	2005-05-20 17:24:02.000000000 +0200
>+++ i810/Imakefile	2005-09-05 09:57:09.000000000 +0200
>@@ -26,7 +26,7 @@
> DRISRCS = $(I810DRISRCS) $(I830DRISRCS)
> DRIOBJS = $(I810DRIOBJS) $(I830DRIOBJS)
> DRIINCLUDES = -I$(SERVERSRC)/GL/dri -I$(LIBSRC)/GL/dri \
>-	-I$(TOP)/include -I$(DRMSRCDIR)/shared
>+	-I$(TOP)/include -I$(DRMSRCDIR)/shared-core
> DRIDEFINES = $(GLX_DEFINES)
> #endif
> 
>diff -u i810.orig/i830_driver.c i810/i830_driver.c
>--- i810.orig/i830_driver.c	2005-09-05 09:55:52.000000000 +0200
>+++ i810/i830_driver.c	2005-09-06 12:49:38.000000000 +0200
>@@ -1736,7 +1736,11 @@
>       dspbase = DSPBBASE;
>    }
> 
>-   OUTREG(dspreg, INREG(dspreg) | DISPPLANE_GAMMA_ENABLE);
>+   /* To ensure gamma is enabled we need to turn off and on the plane */
>+   temp = INREG(dspreg);
>+   OUTREG(dspreg, temp & ~(1<<31));
>+   OUTREG(dspbase, INREG(dspbase));
>+   OUTREG(dspreg, temp | DISPPLANE_GAMMA_ENABLE);
>    OUTREG(dspbase, INREG(dspbase));
> 
>    /* It seems that an initial read is needed. */
>@@ -1749,19 +1753,18 @@
>          r = colors[index].red;
>          g = colors[index].green;
>          b = colors[index].blue;
>+	 val = (r << 16) | (g << 8) | b;
>          for (j = 0; j < 8; j++) {
>-	    val = (r << 16) | (g << 8) | b;
> 	    OUTREG(palreg + index * 32 + (j * 4), val);
>          }
>       }
>       break;
>    case 16:
>       for (i = 0; i < numColors; i++) {
>-         index = indices[i / 2];
>-         r = colors[index].red;
>-         b = colors[index].blue;
>          index = indices[i];
>-         g = colors[index].green;
>+	 r   = colors[index / 2].red;
>+	 g   = colors[index].green;
>+	 b   = colors[index / 2].blue;
> 
> 	 val = (r << 16) | (g << 8) | b;
> 	 OUTREG(palreg + index * 16, val);
>@@ -1769,15 +1772,17 @@
> 	 OUTREG(palreg + index * 16 + 8, val);
> 	 OUTREG(palreg + index * 16 + 12, val);
> 
>-         i++;
>-         index = indices[i];
>-         g = colors[index].green;
>+   	 if (index <= 31) {
>+            r   = colors[index].red;
>+	    g   = colors[(index * 2) + 1].green;
>+	    b   = colors[index].blue;
> 
>-	 val = (r << 16) | (g << 8) | b;
>-	 OUTREG(palreg + index * 16, val);
>-	 OUTREG(palreg + index * 16 + 4, val);
>-	 OUTREG(palreg + index * 16 + 8, val);
>-	 OUTREG(palreg + index * 16 + 12, val);
>+	    val = (r << 16) | (g << 8) | b;
>+	    OUTREG(palreg + index * 32, val);
>+	    OUTREG(palreg + index * 32 + 4, val);
>+	    OUTREG(palreg + index * 32 + 8, val);
>+	    OUTREG(palreg + index * 32 + 12, val);
>+	 }
>       }
>       break;
>    default:
>@@ -4863,6 +4868,10 @@
>    DPRINTF(PFX, "I830BIOSAdjustFrame: y = %d (+ %d), x = %d (+ %d)\n",
> 	   x, pI830->xoffset, y, pI830->yoffset);
> 
>+   /* Sync the engine before adjust frame */
>+   if (!pI830->noAccel)
>+      (*pI830->AccelInfoRec->Sync)(pScrn);
>+
>    /* The i830M just happens to have some problems programming offsets via
>     * this VESA BIOS call. Especially in dual head configurations which
>     * have high resolutions which cause the DSP{A,B}BASE registers to be
>@@ -5319,7 +5328,7 @@
> 
>    DPRINTF(PFX, "I830BIOSSwitchMode: mode == %p\n", mode);
> 
>-   /* Stops head pointer freezes for 845G */
>+   /* Sync the engine before mode switch */
>    if (!pI830->noAccel)
>       (*pI830->AccelInfoRec->Sync)(pScrn);
>

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Attachments on bug 114144: 48190 | 48429 | 48430 | 48902 | 49172