Attachment #49501 for bug #116305

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/************************************************************************
 * regs.h: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
 * Copyright(c) 2002-2005 Neterion Inc.

 * This software may be used and distributed according to the terms of
 * the GNU General Public License (GPL), incorporated herein by reference.

#define ADAPTER_STATUS_RMAC_REMOTE_FAULT   BIT(6)
#define ADAPTER_STATUS_RMAC_LOCAL_FAULT    BIT(7)
#define ADAPTER_STATUS_RMAC_PCC_IDLE       vBIT(0xFF,8,8)
#define ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE  vBIT(0x0F,8,8)
#define ADAPTER_STATUS_RC_PRC_QUIESCENT    vBIT(0xFF,16,8)
#define ADAPTER_STATUS_MC_DRAM_READY       BIT(24)
#define ADAPTER_STATUS_MC_QUEUES_READY     BIT(25)

#define ADAPTER_ECC_EN                     BIT(55)

	u64 serr_source;
#define SERR_SOURCE_PIC			BIT(0)
#define SERR_SOURCE_TXDMA		BIT(1)
#define SERR_SOURCE_RXDMA		BIT(2)
#define SERR_SOURCE_MAC                 BIT(3)
#define SERR_SOURCE_MC                  BIT(4)
#define SERR_SOURCE_XGXS                BIT(5)
#define	SERR_SOURCE_ANY			(SERR_SOURCE_PIC	| \
					SERR_SOURCE_TXDMA	| \
					SERR_SOURCE_RXDMA	| \
					SERR_SOURCE_MAC		| \
					SERR_SOURCE_MC		| \
					SERR_SOURCE_XGXS)

	u64 pci_mode;
#define	GET_PCI_MODE(val)		((val & vBIT(0xF, 0, 4)) >> 60)
#define	PCI_MODE_PCI_33			0
#define	PCI_MODE_PCI_66			0x1
#define	PCI_MODE_PCIX_M1_66		0x2
#define	PCI_MODE_PCIX_M1_100		0x3
#define	PCI_MODE_PCIX_M1_133		0x4
#define	PCI_MODE_PCIX_M2_66		0x5
#define	PCI_MODE_PCIX_M2_100		0x6
#define	PCI_MODE_PCIX_M2_133		0x7
#define	PCI_MODE_UNSUPPORTED		BIT(0)
#define	PCI_MODE_32_BITS		BIT(8)
#define	PCI_MODE_UNKNOWN_MODE		BIT(9)

	u8 unused_0[0x800 - 0x128];
	u8 unused_0[0x800 - 0x120];

/* PCI-X Controller registers */
	u64 pic_int_status;

	u8 unused4[0x08];

	u64 gpio_int_reg;
#define GPIO_INT_REG_LINK_DOWN                 BIT(1)
#define GPIO_INT_REG_LINK_UP                   BIT(2)
	u64 gpio_int_mask;
#define GPIO_INT_MASK_LINK_DOWN                BIT(1)
#define GPIO_INT_MASK_LINK_UP                  BIT(2)
	u64 gpio_alarms;

	u8 unused5[0x38];

	u64 xmsi_data;

	u64 rx_mat;
#define RX_MAT_SET(ring, msi)			vBIT(msi, (8 * ring), 8)

	u8 unused6[0x8];

	u64 tx_mat0_n[0x8];
#define TX_MAT_SET(fifo, msi)			vBIT(msi, (8 * fifo), 8)
	u64 tx_mat16_23;
	u64 tx_mat24_31;
	u64 tx_mat32_39;
	u64 tx_mat40_47;
	u64 tx_mat48_55;
	u64 tx_mat56_63;

	u8 unused_1[0x8];
	u64 stat_byte_cnt;
#define STAT_BC(n)                              vBIT(n,4,12)

	/* Automated statistics collection */
	u64 stat_cfg;

#define STAT_TRSF_PER(n)           TBD
#define	PER_SEC					   0x208d5
#define	SET_UPDT_PERIOD(n)		   vBIT((PER_SEC*n),32,32)
#define	SET_UPDT_CLICKS(val)		   vBIT(val, 32, 32)

	u64 stat_addr;



	u64 gpio_control;
#define GPIO_CTRL_GPIO_0		BIT(8)
	u64 misc_control;
#define MISC_LINK_STABILITY_PRD(val)   vBIT(val,29,3)

	u8 unused7_1[0x240 - 0x208];

	u64 wreq_split_mask;
#define	WREQ_SPLIT_MASK_SET_MASK(val)	vBIT(val, 52, 12)

	u8 unused7_2[0x800 - 0x248];

/* TxDMA registers */
	u64 txdma_int_status;


	u64 pcc_err_reg;
#define PCC_FB_ECC_DB_ERR		vBIT(0xFF, 16, 8)
#define PCC_ENABLE_FOUR			vBIT(0x0F,0,8)

	u64 pcc_err_mask;
	u64 pcc_err_alarm;

#define PRC_CTRL_NO_SNOOP                      (BIT(22)|BIT(23))
#define PRC_CTRL_NO_SNOOP_DESC                 BIT(22)
#define PRC_CTRL_NO_SNOOP_BUFF                 BIT(23)
#define PRC_CTRL_BIMODAL_INTERRUPT             BIT(37)
#define PRC_CTRL_RXD_BACKOFF_INTERVAL(val)     vBIT(val,40,24)

	u64 prc_alarm_action;

	u64 mc_err_reg;
#define MC_ERR_REG_ECC_DB_ERR_L            BIT(14)
#define MC_ERR_REG_ECC_DB_ERR_U            BIT(15)
#define MC_ERR_REG_MIRI_ECC_DB_ERR_0       BIT(18)
#define MC_ERR_REG_MIRI_ECC_DB_ERR_1       BIT(20)
#define MC_ERR_REG_MIRI_CRI_ERR_0          BIT(22)
#define MC_ERR_REG_MIRI_CRI_ERR_1          BIT(23)
#define MC_ERR_REG_SM_ERR                  BIT(31)
#define MC_ERR_REG_ECC_ALL_SNG		   (BIT(2) | BIT(3) | BIT(4) | BIT(5) |\
					    BIT(6) | BIT(7) | BIT(17) | BIT(19))
#define MC_ERR_REG_ECC_ALL_DBL		   (BIT(10) | BIT(11) | BIT(12) |\
					    BIT(13) | BIT(14) | BIT(15) |\
					    BIT(18) | BIT(20))
	u64 mc_err_mask;
	u64 mc_err_alarm;


	u64 mc_rldram_test_d1;
	u8 unused24[0x300 - 0x288];
	u64 mc_rldram_test_d2;

	u8 unused24_1[0x360 - 0x308];
	u64 mc_rldram_ctrl;
#define	MC_RLDRAM_ENABLE_ODT		BIT(7)

	u8 unused24_2[0x640 - 0x368];
	u64 mc_rldram_ref_per_herc;
#define	MC_RLDRAM_SET_REF_PERIOD(val)	vBIT(val, 0, 16)

	u8 unused24_3[0x660 - 0x648];
	u64 mc_rldram_mrs_herc;

	u8 unused25[0x700 - 0x668];
	u64 mc_debug_ctrl;

	u8 unused26[0x3000 - 0x2f08];




/************************************************************************
 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
 * Copyright(c) 2002-2005 Neterion Inc.

 * This software may be used and distributed according to the terms of
 * the GNU General Public License (GPL), incorporated herein by reference.

 * See the file COPYING in this distribution for more information.
 *
 * Credits:
 * Jeff Garzik		: For pointing out the improper error condition
 *			  check in the s2io_xmit routine and also some
 *			  issues in the Tx watch dog function. Also for
 *			  patiently answering all those innumerable
 *			  questions regaring the 2.6 porting issues.
 * Stephen Hemminger	: Providing proper 2.6 porting mechanism for some
 *			  macros available only in 2.6 Kernel.
 * Francois Romieu	: For pointing out all code part that were
 *			  deprecated and also styling related comments.
 * Grant Grundler	: For helping me get rid of some Architecture
 *			  dependent code.
 * Christopher Hellwig	: Some more 2.6 specific issues in the driver.
 *
 * The module loadable parameters that are supported by the driver and a brief
 * explaination of all the variables.
 * rx_ring_num : This can be used to program the number of receive rings used
 * in the driver.
 * rx_ring_sz: This defines the number of descriptors each ring can have. This
 * size of the received frame that can be steered into the corrsponding 
 * receive ring.
 * ring_len: This defines the number of descriptors each ring can have. This 
 * is also an array of size 8.
 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
 * tx_fifo_len: This too is an array of 8. Each element defines the number of
 * Tx descriptors that can be associated with each corresponding FIFO.
 * latency_timer: This input is programmed into the Latency timer register
 * in PCI Configuration space.
 ************************************************************************/

#include <linux/config.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/pci.h>
#include <linux/dma-mapping.h>
#include <linux/kernel.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/stddef.h>
#include <linux/ioctl.h>
#include <linux/timex.h>
#include <linux/sched.h>
#include <linux/ethtool.h>
#include <linux/version.h>
#include <linux/workqueue.h>
#include <linux/if_vlan.h>
#include <linux/moduleparam.h>

#include <asm/system.h>
#include <asm/uaccess.h>
#include <asm/io.h>

/* local include */
#include "s2io.h"
#include "s2io-regs.h"

/* S2io Driver name & version. */
static char s2io_driver_name[] = "Neterion";
static char s2io_driver_version[] = "Version 2.0.8.1";

static inline int RXD_IS_UP2DT(RxD_t *rxdp)
{
	int ret;

	ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
		(GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));

	return ret;
}

/*
 * Cards with following subsystem_id have a link state indication
 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
 * macro below identifies these cards given the subsystem_id.
 */
#define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
	(dev_type == XFRAME_I_DEVICE) ?			\
		((((subid >= 0x600B) && (subid <= 0x600D)) || \
		 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0

#define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
				      ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
#define TASKLET_IN_USE test_and_set_bit(0, (&sp->tasklet_status))
				(unsigned long *)(&sp->tasklet_status))
#define PANIC	1
#define LOW	2
static inline int rx_buffer_level(nic_t * sp, int rxb_size, int ring)
{
	int level = 0;
	mac_info_t *mac_control;

	mac_control = &sp->mac_control;
	if ((mac_control->rings[ring].pkt_cnt - rxb_size) > 16) {
		level = LOW;
		if (rxb_size <= MAX_RXDS_PER_BLOCK) {
			level = PANIC;
		}
	}

	{"rmac_pause_cnt"},
	{"rmac_accepted_ip"},
	{"rmac_err_tcp"},
	{"\n DRIVER STATISTICS"},
	{"single_bit_ecc_errs"},
	{"double_bit_ecc_errs"},
};

#define S2IO_STAT_LEN sizeof(ethtool_stats_keys)/ ETH_GSTRING_LEN

#define S2IO_TEST_LEN	sizeof(s2io_gstrings) / ETH_GSTRING_LEN
#define S2IO_STRINGS_LEN	S2IO_TEST_LEN * ETH_GSTRING_LEN

#define S2IO_TIMER_CONF(timer, handle, arg, exp)		\
			init_timer(&timer);			\
			timer.function = handle;		\
			timer.data = (unsigned long) arg;	\
			mod_timer(&timer, (jiffies + exp))	\

/* Add the vlan */
static void s2io_vlan_rx_register(struct net_device *dev,
					struct vlan_group *grp)
{
	nic_t *nic = dev->priv;
	unsigned long flags;

	spin_lock_irqsave(&nic->tx_lock, flags);
	nic->vlgrp = grp;
	spin_unlock_irqrestore(&nic->tx_lock, flags);
}

/* Unregister the vlan */
static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned long vid)
{
	nic_t *nic = dev->priv;
	unsigned long flags;

	spin_lock_irqsave(&nic->tx_lock, flags);
	if (nic->vlgrp)
		nic->vlgrp->vlan_devices[vid] = NULL;
	spin_unlock_irqrestore(&nic->tx_lock, flags);
}

/*
 * Constants to be programmed into the Xena's registers, to configure
 * the XAUI.
 */

#define SWITCH_SIGN	0xA5A5A5A5A5A5A5A5ULL
#define	END_SIGN	0x0

static u64 herc_act_dtx_cfg[] = {
	/* Set address */
	0x8000051536750000ULL, 0x80000515367500E0ULL,
	/* Write data */
	0x8000051536750004ULL, 0x80000515367500E4ULL,
	/* Set address */
	0x80010515003F0000ULL, 0x80010515003F00E0ULL,
	/* Write data */
	0x80010515003F0004ULL, 0x80010515003F00E4ULL,
	/* Set address */
	0x801205150D440000ULL, 0x801205150D4400E0ULL,
	/* Write data */
	0x801205150D440004ULL, 0x801205150D4400E4ULL,
	/* Set address */
	0x80020515F2100000ULL, 0x80020515F21000E0ULL,
	/* Write data */
	0x80020515F2100004ULL, 0x80020515F21000E4ULL,
	/* Done */
	END_SIGN
};

static u64 xena_mdio_cfg[] = {
	/* Reset PMA PLL */
	0xC001010000000000ULL, 0xC0010100000000E0ULL,
	0xC0010100008000E4ULL,

	END_SIGN
};

static u64 xena_dtx_cfg[] = {
	0x8000051500000000ULL, 0x80000515000000E0ULL,
	0x80000515D93500E4ULL, 0x8001051500000000ULL,
	0x80010515000000E0ULL, 0x80010515001E00E4ULL,

	END_SIGN
};

/*
/* 
 * Constants for Fixing the MacAddress problem seen mostly on
 * Alpha machines.
 */

};

/* Module Loadable parameters. */
static unsigned int tx_fifo_num = 1;
static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
    {[0 ...(MAX_TX_FIFOS - 1)] = 0 };
static unsigned int rx_ring_num = 1;
static unsigned int rx_ring_sz[MAX_RX_RINGS] =
    {[0 ...(MAX_RX_RINGS - 1)] = 0 };
static unsigned int rts_frm_len[MAX_RX_RINGS] =
    {[0 ...(MAX_RX_RINGS - 1)] = 0 };
static unsigned int use_continuous_tx_intrs = 1;
static unsigned int TxFifoNum = 1;
static unsigned int TxFIFOLen_0 = DEFAULT_FIFO_LEN;
static unsigned int TxFIFOLen_1 = 0;
static unsigned int TxFIFOLen_2 = 0;
static unsigned int TxFIFOLen_3 = 0;
static unsigned int TxFIFOLen_4 = 0;
static unsigned int TxFIFOLen_5 = 0;
static unsigned int TxFIFOLen_6 = 0;
static unsigned int TxFIFOLen_7 = 0;
static unsigned int MaxTxDs = MAX_SKB_FRAGS;
static unsigned int RxRingNum = 1;
static unsigned int RxRingSz_0 = SMALL_BLK_CNT;
static unsigned int RxRingSz_1 = 0;
static unsigned int RxRingSz_2 = 0;
static unsigned int RxRingSz_3 = 0;
static unsigned int RxRingSz_4 = 0;
static unsigned int RxRingSz_5 = 0;
static unsigned int RxRingSz_6 = 0;
static unsigned int RxRingSz_7 = 0;
static unsigned int Stats_refresh_time = 4;
static unsigned int rmac_pause_time = 65535;
static unsigned int mc_pause_threshold_q0q3 = 187;
static unsigned int mc_pause_threshold_q4q7 = 187;
static unsigned int shared_splits;
#if defined(__ia64__)
static unsigned int max_splits_trans = XENA_THREE_SPLIT_TRANSACTION;
#else
static unsigned int max_splits_trans = XENA_TWO_SPLIT_TRANSACTION;
#endif
static unsigned int tmac_util_period = 5;
static unsigned int rmac_util_period = 5;
static unsigned int bimodal = 0;
#ifndef CONFIG_S2IO_NAPI
static unsigned int indicate_max_pkts;
#endif
/* Frequency of Rx desc syncs expressed as power of 2 */
static unsigned int rxsync_frequency = 3;
static unsigned int tx_urange_b = 0x10;
static unsigned int tx_ufc_b = 0x20;
static unsigned int tx_urange_c = 0x30;
static unsigned int tx_ufc_c = 0x40;
static unsigned int tx_ufc_d = 0x80;
static unsigned int rx_urange_a = 0xA;
static unsigned int rx_ufc_a = 0x1;
static unsigned int rx_urange_b = 0x10;
static unsigned int rx_ufc_b = 0x2;
static unsigned int rx_urange_c = 0x30;
static unsigned int rx_ufc_c = 0x40;
static unsigned int rx_ufc_d = 0x80;
static u8 latency_timer = 0xf8;
static u8 max_read_byte_cnt = 2;

/*
 * S2IO device table.
 * This table lists all the devices that this driver supports.
 */
static struct pci_device_id s2io_tbl[] __devinitdata = {
	{PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
	 PCI_ANY_ID, PCI_ANY_ID},
	{PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
	 PCI_ANY_ID, PCI_ANY_ID},
	{PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
         PCI_ANY_ID, PCI_ANY_ID},
        {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
         PCI_ANY_ID, PCI_ANY_ID},
	{0,}
};

MODULE_DEVICE_TABLE(pci, s2io_tbl);

static struct pci_driver s2io_driver = {
      .name = "S2IO",
      .id_table = s2io_tbl,
      .probe = s2io_init_nic,
      .remove = __devexit_p(s2io_rem_nic),
};

/* A simplifier macro used both by init and free shared_mem Fns(). */
#define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)

/**
 * init_shared_mem - Allocation and Initialization of Memory
 * @nic: Device private variable.
 * Description: The function allocates all the memory areas shared
 * between the NIC and the driver. This includes Tx descriptors,
 * Rx descriptors and the statistics block.
 */


	void *tmp_v_addr, *tmp_v_addr_next;
	dma_addr_t tmp_p_addr, tmp_p_addr_next;
	RxD_block_t *pre_rxd_blk = NULL;
	int i, j, blk_cnt, rx_sz, tx_sz;
	int lst_size, lst_per_page;
	struct net_device *dev = nic->dev;
#ifdef CONFIG_2BUFF_MODE


	/* Allocation and initialization of TXDLs in FIOFs */
	size = 0;
	for (i = 0; i < config->tx_fifo_num; i++) {
		size += config->tx_cfg[i].fifo_len;
	}
	if (size > MAX_AVAILABLE_TXDS) {
		DBG_PRINT(ERR_DBG, "%s: Requested TxDs too high, ",
			  __FUNCTION__);
		DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
		DBG_PRINT(ERR_DBG, "that can be used\n");
		return FAILURE;
	}

	lst_size = (sizeof(TxD_t) * config->max_txds);
	tx_sz = lst_size * size;
	lst_per_page = PAGE_SIZE / lst_size;

	for (i = 0; i < config->tx_fifo_num; i++) {
		int fifo_len = config->tx_cfg[i].fifo_len;
		int list_holder_size = fifo_len * sizeof(list_info_hold_t);
		mac_control->fifos[i].list_info = kmalloc(list_holder_size,
							  GFP_KERNEL);
		if (!mac_control->fifos[i].list_info) {
			DBG_PRINT(ERR_DBG,
				  "Malloc failed for list_info\n");
			return -ENOMEM;
		}
		memset(mac_control->fifos[i].list_info, 0, list_holder_size);
	}
	for (i = 0; i < config->tx_fifo_num; i++) {
		int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
						lst_per_page);
		mac_control->fifos[i].tx_curr_put_info.offset = 0;
		mac_control->fifos[i].tx_curr_put_info.fifo_len =
		    config->tx_cfg[i].fifo_len - 1;
		mac_control->fifos[i].tx_curr_get_info.offset = 0;
		mac_control->fifos[i].tx_curr_get_info.fifo_len =
		    config->tx_cfg[i].fifo_len - 1;
		mac_control->fifos[i].fifo_no = i;
		mac_control->fifos[i].nic = nic;
		mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 1;

		for (j = 0; j < page_num; j++) {
			int k = 0;
			dma_addr_t tmp_p;

				DBG_PRINT(ERR_DBG, "failed for TxDL\n");
				return -ENOMEM;
			}
			/* If we got a zero DMA address(can happen on
			 * certain platforms like PPC), reallocate.
			 * Store virtual address of page we don't want,
			 * to be freed later.
			 */
			if (!tmp_p) {
				mac_control->zerodma_virt_addr = tmp_v;
				DBG_PRINT(INIT_DBG, 
				"%s: Zero DMA address for TxDL. ", dev->name);
				DBG_PRINT(INIT_DBG, 
				"Virtual address %llx\n", (u64)tmp_v);
				tmp_v = pci_alloc_consistent(nic->pdev,
						     PAGE_SIZE, &tmp_p);
				if (!tmp_v) {
					DBG_PRINT(ERR_DBG,
					  "pci_alloc_consistent ");
					DBG_PRINT(ERR_DBG, "failed for TxDL\n");
					return -ENOMEM;
				}
			}
			while (k < lst_per_page) {
				int l = (j * lst_per_page) + k;
				if (l == config->tx_cfg[i].fifo_len)
					break;
				mac_control->fifos[i].list_info[l].list_virt_addr =
				    tmp_v + (k * lst_size);
				mac_control->fifos[i].list_info[l].list_phy_addr =
				    tmp_p + (k * lst_size);
				k++;
			}
		}
	}
      end_txd_alloc:

	/* Allocation and initialization of RXDs in Rings */
	size = 0;
	for (i = 0; i < config->rx_ring_num; i++) {
		if (config->rx_cfg[i].num_rxd % (MAX_RXDS_PER_BLOCK + 1)) {
			DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
			DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
				  i);
			DBG_PRINT(ERR_DBG, "RxDs per Block");
			return FAILURE;
		}
		size += config->rx_cfg[i].num_rxd;
		mac_control->rings[i].block_count =
		    config->rx_cfg[i].num_rxd / (MAX_RXDS_PER_BLOCK + 1);
		mac_control->rings[i].pkt_cnt =
		    config->rx_cfg[i].num_rxd - mac_control->rings[i].block_count;
	}
	size = (size * (sizeof(RxD_t)));
	rx_sz = size;

	for (i = 0; i < config->rx_ring_num; i++) {
		mac_control->rings[i].rx_curr_get_info.block_index = 0;
		mac_control->rings[i].rx_curr_get_info.offset = 0;
		mac_control->rings[i].rx_curr_get_info.ring_len =
		    config->rx_cfg[i].num_rxd - 1;
		mac_control->rings[i].rx_curr_put_info.block_index = 0;
		mac_control->rings[i].rx_curr_put_info.offset = 0;
		mac_control->rings[i].rx_curr_put_info.ring_len =
		    config->rx_cfg[i].num_rxd - 1;
		mac_control->rings[i].nic = nic;
		mac_control->rings[i].ring_no = i;

	for (i = 0; i < config->RxRingNum; i++) {
		mac_control->rx_curr_get_info[i].block_index = 0;
		mac_control->rx_curr_get_info[i].offset = 0;
		mac_control->rx_curr_get_info[i].ring_len =
		    config->rx_cfg[i].NumRxd - 1;
		mac_control->rx_curr_put_info[i].block_index = 0;
		mac_control->rx_curr_put_info[i].offset = 0;
		mac_control->rx_curr_put_info[i].ring_len =
		    config->rx_cfg[i].NumRxd - 1;
		blk_cnt =
		    config->rx_cfg[i].num_rxd / (MAX_RXDS_PER_BLOCK + 1);
		/*  Allocating all the Rx blocks */
		for (j = 0; j < blk_cnt; j++) {
#ifndef CONFIG_2BUFF_MODE

							  &tmp_p_addr);
			if (tmp_v_addr == NULL) {
				/*
				 * In case of failure, free_shared_mem()
				 * is called, which should free any
				 * memory that was alloced till the
				 * failure happened.
				 */
				mac_control->rings[i].rx_blocks[j].block_virt_addr =
				    tmp_v_addr;
				return -ENOMEM;
			}
			memset(tmp_v_addr, 0, size);
			mac_control->rings[i].rx_blocks[j].block_virt_addr =
				tmp_v_addr;
			mac_control->rings[i].rx_blocks[j].block_dma_addr =
				tmp_p_addr;
		}
		/* Interlinking all Rx Blocks */
		for (j = 0; j < blk_cnt; j++) {
			tmp_v_addr =
				mac_control->rings[i].rx_blocks[j].block_virt_addr;
			tmp_v_addr_next =
				mac_control->rings[i].rx_blocks[(j + 1) %
					      blk_cnt].block_virt_addr;
			tmp_p_addr =
				mac_control->rings[i].rx_blocks[j].block_dma_addr;
			tmp_p_addr_next =
				mac_control->rings[i].rx_blocks[(j + 1) %
					      blk_cnt].block_dma_addr;

			pre_rxd_blk = (RxD_block_t *) tmp_v_addr;
			pre_rxd_blk->reserved_1 = END_OF_BLOCK;	/* last RxD
								 * marker.
								 */
#ifndef	CONFIG_2BUFF_MODE

	}

#ifdef CONFIG_2BUFF_MODE
	/*
	 * Allocation of Storages for buffer addresses in 2BUFF mode
	 * and the buffers as well.
	 */
	for (i = 0; i < config->rx_ring_num; i++) {
		blk_cnt =
		    config->rx_cfg[i].num_rxd / (MAX_RXDS_PER_BLOCK + 1);
		mac_control->rings[i].ba = kmalloc((sizeof(buffAdd_t *) * blk_cnt),
				     GFP_KERNEL);
		if (!mac_control->rings[i].ba)
			return -ENOMEM;
		for (j = 0; j < blk_cnt; j++) {
			int k = 0;
			mac_control->rings[i].ba[j] = kmalloc((sizeof(buffAdd_t) *
						 (MAX_RXDS_PER_BLOCK + 1)),
						GFP_KERNEL);
			if (!mac_control->rings[i].ba[j])
				return -ENOMEM;
			while (k != MAX_RXDS_PER_BLOCK) {
				ba = &mac_control->rings[i].ba[j][k];

				ba->ba_0_org = (void *) kmalloc
				    (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
				if (!ba->ba_0_org)
					return -ENOMEM;
				tmp = (u64) ba->ba_0_org;

				ba->ba_0 = (void *) tmp;

				ba->ba_1_org = (void *) kmalloc
				    (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
				if (!ba->ba_1_org)
					return -ENOMEM;
				tmp = (u64) ba->ba_1_org;

	    (nic->pdev, size, &mac_control->stats_mem_phy);

	if (!mac_control->stats_mem) {
		/*
		 * In case of failure, free_shared_mem() is called, which
		 * should free any memory that was alloced till the
		 * failure happened.
		 */
		return -ENOMEM;

	tmp_v_addr = mac_control->stats_mem;
	mac_control->stats_info = (StatInfo_t *) tmp_v_addr;
	memset(tmp_v_addr, 0, size);
#ifdef SNMP_SUPPORT
	nic->nMemorySize = mac_control->txd_list_mem_sz +
	    mac_control->stats_mem_sz + mac_control->rxd_ring_mem_sz;
#endif

	DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
		  (unsigned long long) tmp_p_addr);

	return SUCCESS;
}

/**
 * free_shared_mem - Free the allocated Memory
 * @nic:  Device private variable.
 * Description: This function is to free all memory locations allocated by
 * the init_shared_mem() function and return it to the kernel.

	mac_info_t *mac_control;
	struct config_param *config;
	int lst_size, lst_per_page;
	struct net_device *dev = nic->dev;

	if (!nic)
		return;

	mac_control = &nic->mac_control;
	config = &nic->config;

	lst_size = (sizeof(TxD_t) * config->max_txds);
	lst_per_page = PAGE_SIZE / lst_size;

	for (i = 0; i < config->tx_fifo_num; i++) {
		int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
						lst_per_page);
		for (j = 0; j < page_num; j++) {
			int mem_blks = (j * lst_per_page);
			if (!mac_control->fifos[i].list_info)
				return;	
			if (!mac_control->fifos[i].list_info[mem_blks].
				 list_virt_addr)
				break;
			pci_free_consistent(nic->pdev, PAGE_SIZE,
					    mac_control->fifos[i].
					    list_info[mem_blks].
					    list_virt_addr,
					    mac_control->fifos[i].
					    list_info[mem_blks].
					    list_phy_addr);
		}
		/* If we got a zero DMA address during allocation,
		 * free the page now
		 */
		if (mac_control->zerodma_virt_addr) {
			pci_free_consistent(nic->pdev, PAGE_SIZE,
					    mac_control->zerodma_virt_addr,
					    (dma_addr_t)0);
			DBG_PRINT(INIT_DBG, 
			"%s: Freeing TxDL with zero DMA addr. ", dev->name);
			DBG_PRINT(INIT_DBG, "Virtual address %llx\n",
			(u64)(mac_control->zerodma_virt_addr));
		}
		kfree(mac_control->fifos[i].list_info);
	}

#ifndef CONFIG_2BUFF_MODE

#else
	size = SIZE_OF_BLOCK;
#endif
	for (i = 0; i < config->rx_ring_num; i++) {
		blk_cnt = mac_control->rings[i].block_count;
		for (j = 0; j < blk_cnt; j++) {
			tmp_v_addr = mac_control->rings[i].rx_blocks[j].
				block_virt_addr;
			tmp_p_addr = mac_control->rings[i].rx_blocks[j].
				block_dma_addr;
			if (tmp_v_addr == NULL)
				break;
			pci_free_consistent(nic->pdev, size,


#ifdef CONFIG_2BUFF_MODE
	/* Freeing buffer storage addresses in 2BUFF mode. */
	for (i = 0; i < config->rx_ring_num; i++) {
		blk_cnt =
		    config->rx_cfg[i].num_rxd / (MAX_RXDS_PER_BLOCK + 1);
		for (j = 0; j < blk_cnt; j++) {
			int k = 0;
			if (!mac_control->rings[i].ba[j])
				continue;
			while (k != MAX_RXDS_PER_BLOCK) {
				buffAdd_t *ba = &mac_control->rings[i].ba[j][k];
				kfree(ba->ba_0_org);
				kfree(ba->ba_1_org);
				k++;
			}
			kfree(mac_control->rings[i].ba[j]);
		}
		if (mac_control->rings[i].ba)
			kfree(mac_control->rings[i].ba);
	}
#endif


	}
}

/**
 * s2io_verify_pci_mode -
 */

static int s2io_verify_pci_mode(nic_t *nic)
{
	XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
	register u64 val64 = 0;
	int     mode;

	val64 = readq(&bar0->pci_mode);
	mode = (u8)GET_PCI_MODE(val64);

	if ( val64 & PCI_MODE_UNKNOWN_MODE)
		return -1;      /* Unknown PCI mode */
	return mode;
}


/**
 * s2io_print_pci_mode -
 */
static int s2io_print_pci_mode(nic_t *nic)
{
	XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
	register u64 val64 = 0;
	int	mode;
	struct config_param *config = &nic->config;

	val64 = readq(&bar0->pci_mode);
	mode = (u8)GET_PCI_MODE(val64);

	if ( val64 & PCI_MODE_UNKNOWN_MODE)
		return -1;	/* Unknown PCI mode */

	if (val64 & PCI_MODE_32_BITS) {
		DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
	} else {
		DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
	}

	switch(mode) {
		case PCI_MODE_PCI_33:
			DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
			config->bus_speed = 33;
			break;
		case PCI_MODE_PCI_66:
			DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
			config->bus_speed = 133;
			break;
		case PCI_MODE_PCIX_M1_66:
			DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
			config->bus_speed = 133; /* Herc doubles the clock rate */
			break;
		case PCI_MODE_PCIX_M1_100:
			DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
			config->bus_speed = 200;
			break;
		case PCI_MODE_PCIX_M1_133:
			DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
			config->bus_speed = 266;
			break;
		case PCI_MODE_PCIX_M2_66:
			DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
			config->bus_speed = 133;
			break;
		case PCI_MODE_PCIX_M2_100:
			DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
			config->bus_speed = 200;
			break;
		case PCI_MODE_PCIX_M2_133:
			DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
			config->bus_speed = 266;
			break;
		default:
			return -1;	/* Unsupported bus speed */
	}

	return mode;
}

/**
 *  init_nic - Initialization of hardware
 *  @nic: device peivate variable
 *  Description: The function sequentially configures every block
 *  of the H/W from their reset values.
 *  Return Value:  SUCCESS on success and
 *  '-1' on failure (endian settings incorrect).
 */

static int init_nic(struct s2io_nic *nic)
{
	XENA_dev_config_t __iomem *bar0 = nic->bar0;
	struct net_device *dev = nic->dev;
	register u64 val64 = 0;
	void __iomem *add;
	u32 time;
	int i, j;
	mac_info_t *mac_control;
	struct config_param *config;
	int mdio_cnt = 0, dtx_cnt = 0;
	unsigned long long mem_share;
	int mem_size;

	mac_control = &nic->mac_control;
	config = &nic->config;

	/* to set the swapper controle on the card */
	if(s2io_set_swapper(nic)) {
		DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
		return -1;
	}
	/*
	 * The device by default set to a big endian format, so 
	 * a big endian driver need not set anything.
	 */
	writeq(0xffffffffffffffffULL, &bar0->swapper_ctrl);
	val64 = (SWAPPER_CTRL_PIF_R_FE |
		 SWAPPER_CTRL_PIF_R_SE |
		 SWAPPER_CTRL_PIF_W_FE |
		 SWAPPER_CTRL_PIF_W_SE |
		 SWAPPER_CTRL_TXP_FE |
		 SWAPPER_CTRL_TXP_SE |
		 SWAPPER_CTRL_TXD_R_FE |
		 SWAPPER_CTRL_TXD_W_FE |
		 SWAPPER_CTRL_TXF_R_FE |
		 SWAPPER_CTRL_RXD_R_FE |
		 SWAPPER_CTRL_RXD_W_FE |
		 SWAPPER_CTRL_RXF_W_FE |
		 SWAPPER_CTRL_XMSI_FE |
		 SWAPPER_CTRL_XMSI_SE |
		 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
	writeq(val64, &bar0->swapper_ctrl);
#else
	/* 
	 * Initially we enable all bits to make it accessible by 
	 * the driver, then we selectively enable only those bits 
	 * that we want to set.
	 */
	writeq(0xffffffffffffffffULL, &bar0->swapper_ctrl);
	val64 = (SWAPPER_CTRL_PIF_R_FE |
		 SWAPPER_CTRL_PIF_R_SE |
		 SWAPPER_CTRL_PIF_W_FE |
		 SWAPPER_CTRL_PIF_W_SE |
		 SWAPPER_CTRL_TXP_FE |
		 SWAPPER_CTRL_TXP_SE |
		 SWAPPER_CTRL_TXD_R_FE |
		 SWAPPER_CTRL_TXD_R_SE |
		 SWAPPER_CTRL_TXD_W_FE |
		 SWAPPER_CTRL_TXD_W_SE |
		 SWAPPER_CTRL_TXF_R_FE |
		 SWAPPER_CTRL_RXD_R_FE |
		 SWAPPER_CTRL_RXD_R_SE |
		 SWAPPER_CTRL_RXD_W_FE |
		 SWAPPER_CTRL_RXD_W_SE |
		 SWAPPER_CTRL_RXF_W_FE |
		 SWAPPER_CTRL_XMSI_FE |
		 SWAPPER_CTRL_XMSI_SE |
		 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
	writeq(val64, &bar0->swapper_ctrl);
#endif

	/*
	 * Herc requires EOI to be removed from reset before XGXS, so..
	 * reading a feedback register.
	 */
	if (nic->device_type & XFRAME_II_DEVICE) {
		val64 = 0xA500000000ULL;
		writeq(val64, &bar0->sw_reset);
		msleep(500);
		val64 = readq(&bar0->sw_reset);
			  dev->name);
		DBG_PRINT(ERR_DBG, ", feedback read %llx\n", print_var);

		return FAILURE;
	}

	/* Remove XGXS from reset state */
	val64 = 0;
	writeq(val64, &bar0->sw_reset);
	msleep(500);
	val64 = readq(&bar0->sw_reset);
	set_current_state(TASK_UNINTERRUPTIBLE);
	schedule_timeout(HZ / 2);

	/*  Enable Receiving broadcasts */
	add = &bar0->mac_cfg;
	val64 = readq(&bar0->mac_cfg);
	val64 |= MAC_RMAC_BCAST_ENABLE;
	writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);

	val64 = dev->mtu;
	writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);

	/*
	 * Configuring the XAUI Interface of Xena.
	 * ***************************************
	 * To Configure the Xena's XAUI, one has to write a series
	 * of 64 bit values into two registers in a particular
	 * sequence. Hence a macro 'SWITCH_SIGN' has been defined
	 * which will be defined in the array of configuration values
	 * (xena_dtx_cfg & xena_mdio_cfg) at appropriate places
	 * to switch writing from one regsiter to another. We continue
	 * writing these values until we encounter the 'END_SIGN' macro.
	 * For example, After making a series of 21 writes into
	 * dtx_control register the 'SWITCH_SIGN' appears and hence we
	 * start writing into mdio_control until we encounter END_SIGN.
	 */
	if (nic->device_type & XFRAME_II_DEVICE) {
		while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
			SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
			if (default_dtx_cfg[dtx_cnt] == SWITCH_SIGN) {
				dtx_cnt++;
				goto mdio_cfg;
			}
			SPECIAL_REG_WRITE(default_dtx_cfg[dtx_cnt],
					  &bar0->dtx_control, UF);
			if (dtx_cnt & 0x1)
				msleep(1); /* Necessary!! */
			dtx_cnt++;
		}
	} else {
		while (1) {
		      dtx_cfg:
			while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
				if (xena_dtx_cfg[dtx_cnt] == SWITCH_SIGN) {
					dtx_cnt++;
					goto mdio_cfg;
				}
				SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
						  &bar0->dtx_control, UF);
				val64 = readq(&bar0->dtx_control);
				dtx_cnt++;
			}
		      mdio_cfg:
			while (xena_mdio_cfg[mdio_cnt] != END_SIGN) {
				if (xena_mdio_cfg[mdio_cnt] == SWITCH_SIGN) {
					mdio_cnt++;
					goto dtx_cfg;
				}
				SPECIAL_REG_WRITE(xena_mdio_cfg[mdio_cnt],
						  &bar0->mdio_control, UF);
				val64 = readq(&bar0->mdio_control);
				mdio_cnt++;
			}
			if ((xena_dtx_cfg[dtx_cnt] == END_SIGN) &&
			    (xena_mdio_cfg[mdio_cnt] == END_SIGN)) {
				break;
			} else {
				goto dtx_cfg;
			}
			SPECIAL_REG_WRITE(default_mdio_cfg[mdio_cnt],
					  &bar0->mdio_control, UF);
			val64 = readq(&bar0->mdio_control);
			mdio_cnt++;
		}
		if ((default_dtx_cfg[dtx_cnt] == END_SIGN) &&
		    (default_mdio_cfg[mdio_cnt] == END_SIGN)) {
			break;
		} else {
			goto dtx_cfg;
		}
	}


	writeq(val64, &bar0->tx_fifo_partition_3);


	for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
		val64 |=
		    vBIT(config->tx_cfg[i].fifo_len - 1, ((i * 32) + 19),
			 13) | vBIT(config->tx_cfg[i].fifo_priority,
				    ((i * 32) + 5), 3);

		if (i == (config->tx_fifo_num - 1)) {
			if (i % 2 == 0)
				i++;
		}

	val64 |= BIT(0);	/* To enable the FIFO partition. */
	writeq(val64, &bar0->tx_fifo_partition_0);

	/*
	 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
	 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
	 */
	if ((nic->device_type == XFRAME_I_DEVICE) &&
		(get_xena_rev_id(nic->pdev) < 4))
		writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);

	val64 = readq(&bar0->tx_fifo_partition_0);
	DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
		  &bar0->tx_fifo_partition_0, (unsigned long long) val64);

	/*
	 * Initialization of Tx_PA_CONFIG register to ignore packet
	 * integrity checking.
	 */
	val64 = readq(&bar0->tx_pa_cfg);


	/* Rx DMA intialization. */
	val64 = 0;
	for (i = 0; i < config->rx_ring_num; i++) {
		val64 |=
		    vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)),
			 3);
	}
	writeq(val64, &bar0->rx_queue_priority);

	/*
	 * Allocating equal share of memory to all the
	 * configured Rings.
	 */
	val64 = 0;
	if (nic->device_type & XFRAME_II_DEVICE)
		mem_size = 32;
	else
		mem_size = 64;

	for (i = 0; i < config->rx_ring_num; i++) {
		switch (i) {
		case 0:
			mem_share = (mem_size / config->rx_ring_num +
				     mem_size % config->rx_ring_num);
			val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
			continue;
		case 1:
			mem_share = (mem_size / config->rx_ring_num);
			val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
			continue;
		case 2:
			mem_share = (mem_size / config->rx_ring_num);
			val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
			continue;
		case 3:
			mem_share = (mem_size / config->rx_ring_num);
			val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
			continue;
		case 4:
			mem_share = (mem_size / config->rx_ring_num);
			val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
			continue;
		case 5:
			mem_share = (mem_size / config->rx_ring_num);
			val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
			continue;
		case 6:
			mem_share = (mem_size / config->rx_ring_num);
			val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
			continue;
		case 7:
			mem_share = (mem_size / config->rx_ring_num);
			val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
			continue;
		}
	}
	writeq(val64, &bar0->rx_queue_cfg);

	/*
	 * Filling Tx round robin registers
	 * as per the number of FIFOs
	 */
	switch (config->tx_fifo_num) {
	case 1:
		val64 = 0x0000000000000000ULL;
		writeq(val64, &bar0->tx_w_round_robin_0);
		writeq(val64, &bar0->tx_w_round_robin_1);
		writeq(val64, &bar0->tx_w_round_robin_2);
		writeq(val64, &bar0->tx_w_round_robin_3);
		writeq(val64, &bar0->tx_w_round_robin_4);
		break;
	case 2:
		val64 = 0x0000010000010000ULL;
		writeq(val64, &bar0->tx_w_round_robin_0);
		val64 = 0x0100000100000100ULL;
		writeq(val64, &bar0->tx_w_round_robin_1);
		val64 = 0x0001000001000001ULL;
		writeq(val64, &bar0->tx_w_round_robin_2);
		val64 = 0x0000010000010000ULL;
		writeq(val64, &bar0->tx_w_round_robin_3);
		val64 = 0x0100000000000000ULL;
		writeq(val64, &bar0->tx_w_round_robin_4);
		break;
	case 3:
		val64 = 0x0001000102000001ULL;
		writeq(val64, &bar0->tx_w_round_robin_0);
		val64 = 0x0001020000010001ULL;
		writeq(val64, &bar0->tx_w_round_robin_1);
		val64 = 0x0200000100010200ULL;
		writeq(val64, &bar0->tx_w_round_robin_2);
		val64 = 0x0001000102000001ULL;
		writeq(val64, &bar0->tx_w_round_robin_3);
		val64 = 0x0001020000000000ULL;
		writeq(val64, &bar0->tx_w_round_robin_4);
		break;
	case 4:
		val64 = 0x0001020300010200ULL;
		writeq(val64, &bar0->tx_w_round_robin_0);
		val64 = 0x0100000102030001ULL;
		writeq(val64, &bar0->tx_w_round_robin_1);
		val64 = 0x0200010000010203ULL;
		writeq(val64, &bar0->tx_w_round_robin_2);
		val64 = 0x0001020001000001ULL;
		writeq(val64, &bar0->tx_w_round_robin_3);
		val64 = 0x0203000100000000ULL;
		writeq(val64, &bar0->tx_w_round_robin_4);
		break;
	case 5:
		val64 = 0x0001000203000102ULL;
		writeq(val64, &bar0->tx_w_round_robin_0);
		val64 = 0x0001020001030004ULL;
		writeq(val64, &bar0->tx_w_round_robin_1);
		val64 = 0x0001000203000102ULL;
		writeq(val64, &bar0->tx_w_round_robin_2);
		val64 = 0x0001020001030004ULL;
		writeq(val64, &bar0->tx_w_round_robin_3);
		val64 = 0x0001000000000000ULL;
		writeq(val64, &bar0->tx_w_round_robin_4);
		break;
	case 6:
		val64 = 0x0001020304000102ULL;
		writeq(val64, &bar0->tx_w_round_robin_0);
		val64 = 0x0304050001020001ULL;
		writeq(val64, &bar0->tx_w_round_robin_1);
		val64 = 0x0203000100000102ULL;
		writeq(val64, &bar0->tx_w_round_robin_2);
		val64 = 0x0304000102030405ULL;
		writeq(val64, &bar0->tx_w_round_robin_3);
		val64 = 0x0001000200000000ULL;
		writeq(val64, &bar0->tx_w_round_robin_4);
		break;
	case 7:
		val64 = 0x0001020001020300ULL;
		writeq(val64, &bar0->tx_w_round_robin_0);
		val64 = 0x0102030400010203ULL;
		writeq(val64, &bar0->tx_w_round_robin_1);
		val64 = 0x0405060001020001ULL;
		writeq(val64, &bar0->tx_w_round_robin_2);
		val64 = 0x0304050000010200ULL;
		writeq(val64, &bar0->tx_w_round_robin_3);
		val64 = 0x0102030000000000ULL;
		writeq(val64, &bar0->tx_w_round_robin_4);
		break;
	case 8:
		val64 = 0x0001020300040105ULL;
		writeq(val64, &bar0->tx_w_round_robin_0);
		val64 = 0x0200030106000204ULL;
		writeq(val64, &bar0->tx_w_round_robin_1);
		val64 = 0x0103000502010007ULL;
		writeq(val64, &bar0->tx_w_round_robin_2);
		val64 = 0x0304010002060500ULL;
		writeq(val64, &bar0->tx_w_round_robin_3);
		val64 = 0x0103020400000000ULL;
		writeq(val64, &bar0->tx_w_round_robin_4);
		break;
	}

	/* Filling the Rx round robin registers as per the
	 * number of Rings and steering based on QoS.
         */
	switch (config->rx_ring_num) {
	case 1:
		val64 = 0x8080808080808080ULL;
		writeq(val64, &bar0->rts_qos_steering);
		break;
	case 2:
		val64 = 0x0000010000010000ULL;
		writeq(val64, &bar0->rx_w_round_robin_0);
		val64 = 0x0100000100000100ULL;
		writeq(val64, &bar0->rx_w_round_robin_1);
		val64 = 0x0001000001000001ULL;
		writeq(val64, &bar0->rx_w_round_robin_2);
		val64 = 0x0000010000010000ULL;
		writeq(val64, &bar0->rx_w_round_robin_3);
		val64 = 0x0100000000000000ULL;
		writeq(val64, &bar0->rx_w_round_robin_4);

		val64 = 0x8080808040404040ULL;
		writeq(val64, &bar0->rts_qos_steering);
		break;
	case 3:
		val64 = 0x0001000102000001ULL;
		writeq(val64, &bar0->rx_w_round_robin_0);
		val64 = 0x0001020000010001ULL;
		writeq(val64, &bar0->rx_w_round_robin_1);
		val64 = 0x0200000100010200ULL;
		writeq(val64, &bar0->rx_w_round_robin_2);
		val64 = 0x0001000102000001ULL;
		writeq(val64, &bar0->rx_w_round_robin_3);
		val64 = 0x0001020000000000ULL;
		writeq(val64, &bar0->rx_w_round_robin_4);

		val64 = 0x8080804040402020ULL;
		writeq(val64, &bar0->rts_qos_steering);
		break;
	case 4:
		val64 = 0x0001020300010200ULL;
		writeq(val64, &bar0->rx_w_round_robin_0);
		val64 = 0x0100000102030001ULL;
		writeq(val64, &bar0->rx_w_round_robin_1);
		val64 = 0x0200010000010203ULL;
		writeq(val64, &bar0->rx_w_round_robin_2);
		val64 = 0x0001020001000001ULL;	
		writeq(val64, &bar0->rx_w_round_robin_3);
		val64 = 0x0203000100000000ULL;
		writeq(val64, &bar0->rx_w_round_robin_4);

		val64 = 0x8080404020201010ULL;
		writeq(val64, &bar0->rts_qos_steering);
		break;
	case 5:
		val64 = 0x0001000203000102ULL;
		writeq(val64, &bar0->rx_w_round_robin_0);
		val64 = 0x0001020001030004ULL;
		writeq(val64, &bar0->rx_w_round_robin_1);
		val64 = 0x0001000203000102ULL;
		writeq(val64, &bar0->rx_w_round_robin_2);
		val64 = 0x0001020001030004ULL;
		writeq(val64, &bar0->rx_w_round_robin_3);
		val64 = 0x0001000000000000ULL;
		writeq(val64, &bar0->rx_w_round_robin_4);

		val64 = 0x8080404020201008ULL;
		writeq(val64, &bar0->rts_qos_steering);
		break;
	case 6:
		val64 = 0x0001020304000102ULL;
		writeq(val64, &bar0->rx_w_round_robin_0);
		val64 = 0x0304050001020001ULL;
		writeq(val64, &bar0->rx_w_round_robin_1);
		val64 = 0x0203000100000102ULL;
		writeq(val64, &bar0->rx_w_round_robin_2);
		val64 = 0x0304000102030405ULL;
		writeq(val64, &bar0->rx_w_round_robin_3);
		val64 = 0x0001000200000000ULL;
		writeq(val64, &bar0->rx_w_round_robin_4);

		val64 = 0x8080404020100804ULL;
		writeq(val64, &bar0->rts_qos_steering);
		break;
	case 7:
		val64 = 0x0001020001020300ULL;
		writeq(val64, &bar0->rx_w_round_robin_0);
		val64 = 0x0102030400010203ULL;
		writeq(val64, &bar0->rx_w_round_robin_1);
		val64 = 0x0405060001020001ULL;
		writeq(val64, &bar0->rx_w_round_robin_2);
		val64 = 0x0304050000010200ULL;
		writeq(val64, &bar0->rx_w_round_robin_3);
		val64 = 0x0102030000000000ULL;
		writeq(val64, &bar0->rx_w_round_robin_4);

		val64 = 0x8080402010080402ULL;
		writeq(val64, &bar0->rts_qos_steering);
		break;
	case 8:
		val64 = 0x0001020300040105ULL;
		writeq(val64, &bar0->rx_w_round_robin_0);
		val64 = 0x0200030106000204ULL;
		writeq(val64, &bar0->rx_w_round_robin_1);
		val64 = 0x0103000502010007ULL;
		writeq(val64, &bar0->rx_w_round_robin_2);
		val64 = 0x0304010002060500ULL;
		writeq(val64, &bar0->rx_w_round_robin_3);
		val64 = 0x0103020400000000ULL;
		writeq(val64, &bar0->rx_w_round_robin_4);

		val64 = 0x8040201008040201ULL;
		writeq(val64, &bar0->rts_qos_steering);
		break;
	}

	/* UDP Fix */
	val64 = 0;
	for (i = 0; i < 8; i++)
		writeq(val64, &bar0->rts_frm_len_n[i]);

	/* Set the default rts frame length for the rings configured */
	val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
	for (i = 0 ; i < config->rx_ring_num ; i++)
		writeq(val64, &bar0->rts_frm_len_n[i]);

	/* Set the frame length for the configured rings
	 * desired by the user
	 */
	for (i = 0; i < config->rx_ring_num; i++) {
		/* If rts_frm_len[i] == 0 then it is assumed that user not
		 * specified frame length steering.
		 * If the user provides the frame length then program
		 * the rts_frm_len register for those values or else
		 * leave it as it is.
		 */
		if (rts_frm_len[i] != 0) {
			writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
				&bar0->rts_frm_len_n[i]);
		}
	}

	/* Program statistics memory */
	writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
	val64 = SET_UPDT_PERIOD(Stats_refresh_time) |
	    STAT_CFG_STAT_RO | STAT_CFG_STAT_EN;
	writeq(val64, &bar0->stat_cfg);

	if (nic->device_type == XFRAME_II_DEVICE) {
		val64 = STAT_BC(0x320);
		writeq(val64, &bar0->stat_byte_cnt);
	}

	/*
	 * Initializing the sampling rate for the device to calculate the
	 * bandwidth utilization.
	 */

	writeq(val64, &bar0->mac_link_util);


	/*
	 * Initializing the Transmit and Receive Traffic Interrupt
	 * Scheme.
	 */
	/*
	 * TTI Initialization. Default Tx timer gets us about
	 * 250 interrupts per sec. Continuous interrupts are enabled
	 * by default.
	 */
	if (nic->device_type == XFRAME_II_DEVICE) {
		int count = (nic->config.bus_speed * 125)/2;
		val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
	} else {

		val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
	}
	val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
	    TTI_DATA1_MEM_TX_URNG_B(0x10) |
	    TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN;
		if (use_continuous_tx_intrs)
			val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
	writeq(val64, &bar0->tti_data1_mem);

	val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
	    TTI_DATA2_MEM_TX_UFC_B(0x20) |
	    TTI_DATA2_MEM_TX_UFC_C(0x70) | TTI_DATA2_MEM_TX_UFC_D(0x80);
	    TTI_DATA2_MEM_TX_UFC_D(tx_ufc_d);
	writeq(val64, &bar0->tti_data2_mem);

	val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
	writeq(val64, &bar0->tti_command_mem);

	/*
	 * Once the operation completes, the Strobe bit of the command
	 * register will be reset. We poll for this particular condition
	 * We wait for a maximum of 500ms for the operation to complete,

				  dev->name);
			return -1;
		}
		msleep(50);
		schedule_timeout(HZ / 20);
		time++;
	}

	if (nic->config.bimodal) {
		int k = 0;
		for (k = 0; k < config->rx_ring_num; k++) {
			val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
			val64 |= TTI_CMD_MEM_OFFSET(0x38+k);
			writeq(val64, &bar0->tti_command_mem);

		/*
		 * Once the operation completes, the Strobe bit of the command
		 * register will be reset. We poll for this particular condition
		 * We wait for a maximum of 500ms for the operation to complete,
		 * if it's not complete by then we return error.
		*/
			time = 0;
			while (TRUE) {
				val64 = readq(&bar0->tti_command_mem);
				if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
					break;
				}
				if (time > 10) {
					DBG_PRINT(ERR_DBG,
						"%s: TTI init Failed\n",
					dev->name);
					return -1;
				}
				time++;
				msleep(50);
			}
		}
	} else {

		/* RTI Initialization */
		if (nic->device_type == XFRAME_II_DEVICE) {
			/*
			 * Programmed to generate Apprx 500 Intrs per
			 * second
			 */
			int count = (nic->config.bus_speed * 125)/4;
			val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
		} else {
			val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
			break;
		}
		val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
		    RTI_DATA1_MEM_RX_URNG_B(0x10) |
		    RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;

		writeq(val64, &bar0->rti_data1_mem);

		val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
		    RTI_DATA2_MEM_RX_UFC_B(0x2) |
		    RTI_DATA2_MEM_RX_UFC_C(0x40) | RTI_DATA2_MEM_RX_UFC_D(0x80);
		writeq(val64, &bar0->rti_data2_mem);

		for (i = 0; i < config->rx_ring_num; i++) {
			val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
					| RTI_CMD_MEM_OFFSET(i);
			writeq(val64, &bar0->rti_command_mem);

			/*
			 * Once the operation completes, the Strobe bit of the
			 * command register will be reset. We poll for this
			 * particular condition. We wait for a maximum of 500ms
			 * for the operation to complete, if it's not complete
			 * by then we return error.
			 */
			time = 0;
			while (TRUE) {
				val64 = readq(&bar0->rti_command_mem);
				if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD)) {
					break;
				}
				if (time > 10) {
					DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
						  dev->name);
					return -1;
				}
				time++;
				msleep(50);
			}
		}
		time++;
		set_current_state(TASK_UNINTERRUPTIBLE);
		schedule_timeout(HZ / 20);
	}

	/*
	 * Initializing proper values as Pause threshold into all
	 * the 8 Queues on Rx side.
	 */
	writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);

	writel((u32) (val64 >> 32), (add + 4));
	val64 = readq(&bar0->mac_cfg);

	/*
	 * Set the time value to be inserted in the pause frame
	 * generated by xena.
	 */
	val64 = readq(&bar0->rmac_pause_cfg);

	val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
	writeq(val64, &bar0->rmac_pause_cfg);

	/*
	 * Set the Threshold Limit for Generating the pause frame
	 * If the amount of data in any Queue exceeds ratio of
	 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256

	}
	writeq(val64, &bar0->mc_pause_thresh_q4q7);

	/*
	 * TxDMA will stop Read request if the number of read split has
	 * exceeded the limit pointed by shared_splits
	 */
	val64 = readq(&bar0->pic_control);
	val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
	writeq(val64, &bar0->pic_control);

	/*
	 * Programming the Herc to split every write transaction
	 * that does not start on an ADB to reduce disconnects.
	 */
	if (nic->device_type == XFRAME_II_DEVICE) {
		val64 = WREQ_SPLIT_MASK_SET_MASK(255);
		writeq(val64, &bar0->wreq_split_mask);
	}

	/* Setting Link stability period to 64 ms */ 
	if (nic->device_type == XFRAME_II_DEVICE) {
		val64 = MISC_LINK_STABILITY_PRD(3);
		writeq(val64, &bar0->misc_control);
	}

	return SUCCESS;
}
#define LINK_UP_DOWN_INTERRUPT		1
#define MAC_RMAC_ERR_TIMER		2

#if defined(CONFIG_MSI_MODE) || defined(CONFIG_MSIX_MODE)
#define s2io_link_fault_indication(x) MAC_RMAC_ERR_TIMER
#else
int s2io_link_fault_indication(nic_t *nic)
{
	if (nic->device_type == XFRAME_II_DEVICE)
		return LINK_UP_DOWN_INTERRUPT;
	else
		return MAC_RMAC_ERR_TIMER;
}
#endif

/**
 *  en_dis_able_nic_intrs - Enable or Disable the interrupts
 *  @nic: device private variable,
 *  @mask: A mask indicating which Intr block must be modified and,
 *  @flag: A flag indicating whether to enable or disable the Intrs.
 *  Description: This function will either disable or enable the interrupts
 *  depending on the flag argument. The mask argument can be used to
 *  enable/disable any Intr block.
 *  Return Value: NONE.
 */

static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
{
	XENA_dev_config_t __iomem *bar0 = nic->bar0;
	register u64 val64 = 0, temp64 = 0;

	/*  Top level interrupt classification */

			temp64 = readq(&bar0->general_int_mask);
			temp64 &= ~((u64) val64);
			writeq(temp64, &bar0->general_int_mask);
			/*
			 * If Hercules adapter enable GPIO otherwise
			 * disabled all PCIX, Flash, MDIO, IIC and GPIO
			 * interrupts for now.
			 * TODO
			 */
			if (s2io_link_fault_indication(nic) ==
					LINK_UP_DOWN_INTERRUPT ) {
				temp64 = readq(&bar0->pic_int_mask);
				temp64 &= ~((u64) PIC_INT_GPIO);
				writeq(temp64, &bar0->pic_int_mask);
				temp64 = readq(&bar0->gpio_int_mask);
				temp64 &= ~((u64) GPIO_INT_MASK_LINK_UP);
				writeq(temp64, &bar0->gpio_int_mask);
			} else {
				writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
			}
			/*
			 * No MSI Support is available presently, so TTI and
			 * RTI interrupts are also disabled.
			 */
		} else if (flag == DISABLE_INTRS) {
			/*
			 * Disable PIC Intrs in the general
			 * intr mask register
			 */
			writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
			temp64 = readq(&bar0->general_int_mask);

			temp64 = readq(&bar0->general_int_mask);
			temp64 &= ~((u64) val64);
			writeq(temp64, &bar0->general_int_mask);
			/*
			 * Keep all interrupts other than PFC interrupt
			 * and PCC interrupt disabled in DMA level.
			 */
			val64 = DISABLE_ALL_INTRS & ~(TXDMA_PFC_INT_M |
						      TXDMA_PCC_INT_M);
			writeq(val64, &bar0->txdma_int_mask);
			/*
			 * Enable only the MISC error 1 interrupt in PFC block
			 */
			val64 = DISABLE_ALL_INTRS & (~PFC_MISC_ERR_1);
			writeq(val64, &bar0->pfc_err_mask);
			/*
			 * Enable only the FB_ECC error interrupt in PCC block
			 */
			val64 = DISABLE_ALL_INTRS & (~PCC_FB_ECC_ERR);
			writeq(val64, &bar0->pcc_err_mask);
		} else if (flag == DISABLE_INTRS) {
			/*
			 * Disable TxDMA Intrs in the general intr mask
			 * register
			 */
			writeq(DISABLE_ALL_INTRS, &bar0->txdma_int_mask);
			writeq(DISABLE_ALL_INTRS, &bar0->pfc_err_mask);

			temp64 = readq(&bar0->general_int_mask);
			temp64 &= ~((u64) val64);
			writeq(temp64, &bar0->general_int_mask);
			/*
			 * All RxDMA block interrupts are disabled for now
			 * TODO
			 */
			writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);
		} else if (flag == DISABLE_INTRS) {
			/*
			 * Disable RxDMA Intrs in the general intr mask
			 * register
			 */
			writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);
			temp64 = readq(&bar0->general_int_mask);

			temp64 = readq(&bar0->general_int_mask);
			temp64 &= ~((u64) val64);
			writeq(temp64, &bar0->general_int_mask);
			/*
			 * All MAC block error interrupts are disabled for now
			 * except the link status change interrupt.
			 * TODO
			 */
			val64 = MAC_INT_STATUS_RMAC_INT;
			temp64 = readq(&bar0->mac_int_mask);
			temp64 &= ~((u64) val64);
			writeq(temp64, &bar0->mac_int_mask);

			val64 = readq(&bar0->mac_rmac_err_mask);
			val64 &= ~((u64) RMAC_LINK_STATE_CHANGE_INT);
			writeq(val64, &bar0->mac_rmac_err_mask);
		} else if (flag == DISABLE_INTRS) {
			/*
			 * Disable MAC Intrs in the general intr mask register
			 */
			writeq(DISABLE_ALL_INTRS, &bar0->mac_int_mask);
			writeq(DISABLE_ALL_INTRS,

			temp64 = readq(&bar0->general_int_mask);
			temp64 &= ~((u64) val64);
			writeq(temp64, &bar0->general_int_mask);
			/*
			 * All XGXS block error interrupts are disabled for now
			 * TODO
			 */
			writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);
		} else if (flag == DISABLE_INTRS) {
			/*
			 * Disable MC Intrs in the general intr mask register
			 */
			writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);
			temp64 = readq(&bar0->general_int_mask);

			temp64 = readq(&bar0->general_int_mask);
			temp64 &= ~((u64) val64);
			writeq(temp64, &bar0->general_int_mask);
			/*
			 * Enable all MC Intrs.
			 * TODO 
			 */
			writeq(0x0, &bar0->mc_int_mask);
			writeq(0x0, &bar0->mc_err_mask);
		} else if (flag == DISABLE_INTRS) {
			/*
			 * Disable MC Intrs in the general intr mask register

			temp64 = readq(&bar0->general_int_mask);
			temp64 &= ~((u64) val64);
			writeq(temp64, &bar0->general_int_mask);
			/*
			 * Enable all the Tx side interrupts
			 * writing 0 Enables all 64 TX interrupt levels
			 */
			writeq(0x0, &bar0->tx_traffic_mask);
		} else if (flag == DISABLE_INTRS) {
			/*
			 * Disable Tx Traffic Intrs in the general intr mask
			 * register.
			 */
			writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);

			/* writing 0 Enables all 8 RX interrupt levels */
			writeq(0x0, &bar0->rx_traffic_mask);
		} else if (flag == DISABLE_INTRS) {
			/*
			 * Disable Rx Traffic Intrs in the general intr mask
			 * register.
			 */
			writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);

	}
}

static int check_prc_pcc_state(u64 val64, int flag, int rev_id, int herc)
{
	int ret = 0;

	if (flag == FALSE) {
		if ((!herc && (rev_id >= 4)) || herc) {
			if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) &&
			    ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
			     ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
				ret = 1;
			}
		}else {
			if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) &&
			    ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
			     ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
				ret = 1;
			}
		}
	} else {
		if ((!herc && (rev_id >= 4)) || herc) {
			if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
			     ADAPTER_STATUS_RMAC_PCC_IDLE) &&
			    (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ||
			     ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
			      ADAPTER_STATUS_RC_PRC_QUIESCENT))) {
				ret = 1;
			}
		} else {
			if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
			     ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) &&
			    (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ||
			     ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
			      ADAPTER_STATUS_RC_PRC_QUIESCENT))) {
				ret = 1;
			}
		}
	}

	return ret;
}
/**
 *  verify_xena_quiescence - Checks whether the H/W is ready
 *  @val64 :  Value read from adapter status register.
 *  @flag : indicates if the adapter enable bit was ever written once
 *  before.
 *  Description: Returns whether the H/W is ready to go or not. Depending
 *  on whether adapter enable bit was written or not the comparison
 *  differs and the calling function passes the input argument flag to
 *  indicate this.
 *  Return: 1 If xena is quiescence
 *          0 If Xena is not quiescence
 */

static int verify_xena_quiescence(nic_t *sp, u64 val64, int flag)
{
	int ret = 0, herc;
	u64 tmp64 = ~((u64) val64);
	int rev_id = get_xena_rev_id(sp->pdev);

	herc = (sp->device_type == XFRAME_II_DEVICE);
	if (!
	    (tmp64 &
	     (ADAPTER_STATUS_TDMA_READY | ADAPTER_STATUS_RDMA_READY |

	      ADAPTER_STATUS_PIC_QUIESCENT | ADAPTER_STATUS_MC_DRAM_READY |
	      ADAPTER_STATUS_MC_QUEUES_READY | ADAPTER_STATUS_M_PLL_LOCK |
	      ADAPTER_STATUS_P_PLL_LOCK))) {
		ret = check_prc_pcc_state(val64, flag, rev_id, herc);
			if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) &&
			    ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
			     ADAPTER_STATUS_RC_PRC_QUIESCENT)) {

				ret = 1;

			}
		} else {
			if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
			     ADAPTER_STATUS_RMAC_PCC_IDLE) &&
			    (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ||
			     ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
			      ADAPTER_STATUS_RC_PRC_QUIESCENT))) {

				ret = 1;

			}
		}
	}

	return ret;

/**
 * fix_mac_address -  Fix for Mac addr problem on Alpha platforms
 * @sp: Pointer to device specifc structure
 * Description :
 * New procedure to clear mac address reading  problems on Alpha platforms
 *
 */

void fix_mac_address(nic_t * sp)
{
	XENA_dev_config_t __iomem *bar0 = sp->bar0;
	u64 val64;
	int i = 0;

	while (fix_mac[i] != END_SIGN) {
		writeq(fix_mac[i++], &bar0->gpio_control);
		udelay(10);
		val64 = readq(&bar0->gpio_control);
	}
}

/**
 *  start_nic - Turns the device on
 *  @nic : device private variable.
 *  Description:
 *  This function actually turns the device on. Before this  function is
 *  called,all Registers are configured from their reset states
 *  and shared memory is allocated but the NIC is still quiescent. On
 *  calling this function, the device interrupts are cleared and the NIC is
 *  literally switched on by writing into the adapter control register.
 *  Return Value:
 *  SUCCESS on success and -1 on failure.
 */

static int start_nic(struct s2io_nic *nic)
{
	XENA_dev_config_t __iomem *bar0 = nic->bar0;
	struct net_device *dev = nic->dev;
	register u64 val64 = 0;
	u16 interruptible;
	u16 subid, i;
	mac_info_t *mac_control;
	struct config_param *config;


	config = &nic->config;

	/*  PRC Initialization and configuration */
	for (i = 0; i < config->rx_ring_num; i++) {
		writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,
		       &bar0->prc_rxd0_n[i]);

		val64 = readq(&bar0->prc_ctrl_n[i]);
		if (nic->config.bimodal)
			val64 |= PRC_CTRL_BIMODAL_INTERRUPT;
#ifndef CONFIG_2BUFF_MODE
		val64 |= PRC_CTRL_RC_ENABLED;
#else

	writeq(val64, &bar0->rx_pa_cfg);
#endif

	/*
	 * Enabling MC-RLDRAM. After enabling the device, we timeout
	 * for around 100ms, which is approximately the time required
	 * for the device to be ready for operation.

	SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
	val64 = readq(&bar0->mc_rldram_mrs);

	msleep(100);	/* Delay by around 100 ms. */
	schedule_timeout(HZ / 10);	/* Delay by around 100 ms. */

	/* Enabling ECC Protection. */
	val64 = readq(&bar0->adapter_control);
	val64 &= ~ADAPTER_ECC_EN;
	writeq(val64, &bar0->adapter_control);

	/*
	 * Clearing any possible Link state change interrupts that
	 * could have popped up just before Enabling the card.
	 */
	val64 = readq(&bar0->mac_rmac_err_reg);
	if (val64)
		writeq(val64, &bar0->mac_rmac_err_reg);

	/*
	 * Verify if the device is ready to be enabled, if so enable
	 * it.
	 */
	val64 = readq(&bar0->adapter_status);
	if (!verify_xena_quiescence(nic, val64, nic->device_enabled_once)) {
		DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
		DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
			  (unsigned long long) val64);

	}

	/*  Enable select interrupts */
	interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
	interruptible |= TX_PIC_INTR | RX_PIC_INTR;
	interruptible |= TX_MAC_INTR | RX_MAC_INTR;

	en_dis_able_nic_intrs(nic, interruptible, ENABLE_INTRS);

	/*
	 * With some switches, link might be already up at this point.
	 * Because of this weird behavior, when we enable laser,
	 * we may not get link. We need to handle this. We cannot
	 * figure out which switch is misbehaving. So we are forced to
	 * make a global change.
	 */

	/* Enabling Laser. */


	/* SXE-002: Initialize link and activity LED */
	subid = nic->pdev->subsystem_device;
	if (((subid & 0xFF) >= 0x07) &&
	    (nic->device_type == XFRAME_I_DEVICE)) {
		val64 = readq(&bar0->gpio_control);
		val64 |= 0x0000800000000000ULL;
		writeq(val64, &bar0->gpio_control);
		val64 = 0x0411040400000000ULL;
		writeq(val64, (void __iomem *) ((u8 *) bar0 + 0x2700));
	}

	/*
	 * Don't see link state interrupts on certain switches, so
	 * directly scheduling a link state task from here.
	 */
#ifdef INIT_TQUEUE
	schedule_task(&nic->set_link_task);
#else
	schedule_work(&nic->set_link_task);
#endif

	/* 
	 * Here we are performing soft reset on XGXS to 
	 * force link down. Since link is already up, we will get
	 * link state change interrupt after this reset
	 */
	SPECIAL_REG_WRITE(0x80010515001E0000ULL, &bar0->dtx_control, UF);
	val64 = readq(&bar0->dtx_control);
	udelay(50);
	SPECIAL_REG_WRITE(0x80010515001E00E0ULL, &bar0->dtx_control, UF);
	val64 = readq(&bar0->dtx_control);
	udelay(50);
	SPECIAL_REG_WRITE(0x80070515001F00E4ULL, &bar0->dtx_control, UF);
	val64 = readq(&bar0->dtx_control);
	udelay(50);

	return SUCCESS;
}

/**
 *  free_tx_buffers - Free all queued Tx buffers
 *  @nic : device private variable.
 *  Description:
 *  Free all queued Tx buffers.
 *  Return Value: void
*/

static void free_tx_buffers(struct s2io_nic *nic)
{
	struct net_device *dev = nic->dev;
	struct sk_buff *skb;

	int i, j;
	mac_info_t *mac_control;
	struct config_param *config;
	int cnt = 0, frg_cnt;

	mac_control = &nic->mac_control;
	config = &nic->config;

	for (i = 0; i < config->tx_fifo_num; i++) {
		for (j = 0; j < config->tx_cfg[i].fifo_len - 1; j++) {
			txdp = (TxD_t *) mac_control->fifos[i].list_info[j].
			    list_virt_addr;
			skb =
			    (struct sk_buff *) ((unsigned long) txdp->
						Host_Control);
			if (skb == NULL) {
				memset(txdp, 0, sizeof(TxD_t) *
				       config->max_txds);
				continue;
			}
			frg_cnt = skb_shinfo(skb)->nr_frags;
			pci_unmap_single(nic->pdev, (dma_addr_t)
					 txdp->Buffer_Pointer,
					 skb->len - skb->data_len,
					 PCI_DMA_TODEVICE);
			if (frg_cnt) {
				TxD_t *temp;
				temp = txdp;
				txdp++;
				for (j = 0; j < frg_cnt; j++, txdp++) {
					skb_frag_t *frag =
					    &skb_shinfo(skb)->frags[j];
					pci_unmap_page(nic->pdev,
						       (dma_addr_t)
						       txdp->
						       Buffer_Pointer,
						       frag->size,
						       PCI_DMA_TODEVICE);
				}
				txdp = temp;
			}
			dev_kfree_skb(skb);
			memset(txdp, 0, sizeof(TxD_t) * config->max_txds);
			cnt++;
		}
		DBG_PRINT(INTR_DBG,
			  "%s:forcibly freeing %d skbs on FIFO%d\n",
			  dev->name, cnt, i);
		mac_control->fifos[i].tx_curr_get_info.offset = 0;
		mac_control->fifos[i].tx_curr_put_info.offset = 0;
	}
}

/**
 *   stop_nic -  To stop the nic
 *   @nic ; device private variable.
 *   Description:
 *   This function does exactly the opposite of what the start_nic()
 *   function does. This function is called to stop the device.
 *   Return Value:
 *   void.


static void stop_nic(struct s2io_nic *nic)
{
	XENA_dev_config_t __iomem *bar0 = nic->bar0;
	register u64 val64 = 0;
	u16 interruptible, i;
	mac_info_t *mac_control;

	config = &nic->config;

	/*  Disable all interrupts */
	interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
	interruptible |= TX_PIC_INTR | RX_PIC_INTR;
	interruptible |= TX_MAC_INTR | RX_MAC_INTR;
	en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);

	/*  Disable PRCs */
	for (i = 0; i < config->rx_ring_num; i++) {
		val64 = readq(&bar0->prc_ctrl_n[i]);
		val64 &= ~((u64) PRC_CTRL_RC_ENABLED);
		writeq(val64, &bar0->prc_ctrl_n[i]);
	}
}

/**
 *  fill_rx_buffers - Allocates the Rx side skbs
 *  @nic:  device private variable
 *  @ring_no: ring number
 *  Description:
 *  The function allocates Rx side skbs and puts the physical
 *  address of these buffers into the RxD buffer pointers, so that the NIC
 *  can DMA the received frame into these locations.

 *  1. single buffer,
 *  2. three buffer and
 *  3. Five buffer modes.
 *  Each mode defines how many fragments the received frame will be split
 *  up into by the NIC. The frame is split into L3 header, L4 Header,
 *  L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
 *  is split into 3 fragments. As of now only single buffer mode is
 *  supported.

	int off, off1, size, block_no, block_no1;
	int offset, offset1;
	u32 alloc_tab = 0;
	u32 alloc_cnt;
	    atomic_read(&nic->rx_bufs_left[ring_no]);
	mac_info_t *mac_control;
	struct config_param *config;
#ifdef CONFIG_2BUFF_MODE

#ifndef CONFIG_S2IO_NAPI
	unsigned long flags;
#endif
	RxD_t *first_rxdp = NULL;

	mac_control = &nic->mac_control;
	config = &nic->config;
	alloc_cnt = mac_control->rings[ring_no].pkt_cnt -
	    atomic_read(&nic->rx_bufs_left[ring_no]);
	size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
	    HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
		size = frame_len[ring_no] + HEADER_ETHERNET_II_802_3_SIZE +
		    HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
	} else {
		size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
		    HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
	}

	while (alloc_tab < alloc_cnt) {
		block_no = mac_control->rings[ring_no].rx_curr_put_info.
		    block_index;
		block_no1 = mac_control->rings[ring_no].rx_curr_get_info.
		    block_index;
		off = mac_control->rings[ring_no].rx_curr_put_info.offset;
		off1 = mac_control->rings[ring_no].rx_curr_get_info.offset;
#ifndef CONFIG_2BUFF_MODE
		offset = block_no * (MAX_RXDS_PER_BLOCK + 1) + off;
		offset1 = block_no1 * (MAX_RXDS_PER_BLOCK + 1) + off1;

		offset1 = block_no1 * (MAX_RXDS_PER_BLOCK) + off1;
#endif

		rxdp = mac_control->rings[ring_no].rx_blocks[block_no].
		    block_virt_addr + off;
		if ((offset == offset1) && (rxdp->Host_Control)) {
			DBG_PRINT(INTR_DBG, "%s: Get and Put", dev->name);

		}
#ifndef	CONFIG_2BUFF_MODE
		if (rxdp->Control_1 == END_OF_BLOCK) {
			mac_control->rings[ring_no].rx_curr_put_info.
			    block_index++;
			mac_control->rings[ring_no].rx_curr_put_info.
			    block_index %= mac_control->rings[ring_no].block_count;
			block_no = mac_control->rings[ring_no].rx_curr_put_info.
				block_index;
			off++;
			off %= (MAX_RXDS_PER_BLOCK + 1);
			mac_control->rings[ring_no].rx_curr_put_info.offset =
			    off;
			rxdp = (RxD_t *) ((unsigned long) rxdp->Control_2);
			DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",

		}
#ifndef CONFIG_S2IO_NAPI
		spin_lock_irqsave(&nic->put_lock, flags);
		mac_control->rings[ring_no].put_pos =
		    (block_no * (MAX_RXDS_PER_BLOCK + 1)) + off;
		spin_unlock_irqrestore(&nic->put_lock, flags);
#endif
#else
		if (rxdp->Host_Control == END_OF_BLOCK) {
			mac_control->rings[ring_no].rx_curr_put_info.
			    block_index++;
			mac_control->rings[ring_no].rx_curr_put_info.block_index
			    %= mac_control->rings[ring_no].block_count;
			block_no = mac_control->rings[ring_no].rx_curr_put_info
			    .block_index;
			off = 0;
			DBG_PRINT(INTR_DBG, "%s: block%d at: 0x%llx\n",
				  dev->name, block_no,
				  (unsigned long long) rxdp->Control_1);
			mac_control->rings[ring_no].rx_curr_put_info.offset =
			    off;
			rxdp = mac_control->rings[ring_no].rx_blocks[block_no].
			    block_virt_addr;
		}
#ifndef CONFIG_S2IO_NAPI
		spin_lock_irqsave(&nic->put_lock, flags);
		mac_control->rings[ring_no].put_pos = (block_no *
					 (MAX_RXDS_PER_BLOCK + 1)) + off;
		spin_unlock_irqrestore(&nic->put_lock, flags);
#endif
#endif

		if (rxdp->Control_2 & BIT(0))
#endif
		{
			mac_control->rings[ring_no].rx_curr_put_info.
			    offset = off;
			goto end;
		}
#ifdef	CONFIG_2BUFF_MODE
		/*
		 * RxDs Spanning cache lines will be replenished only
		 * if the succeeding RxD is also owned by Host. It
		 * will always be the ((8*i)+3) and ((8*i)+6)
		 * descriptors for the 48 byte descriptor. The offending
		 * decsriptor is of-course the 3rd descriptor.
		 */
		rxdpphys = mac_control->rings[ring_no].rx_blocks[block_no].
		    block_dma_addr + (off * sizeof(RxD_t));
		if (((u64) (rxdpphys)) % 128 > 80) {
			rxdpnext = mac_control->rings[ring_no].rx_blocks[block_no].
			    block_virt_addr + (off + 1);
			if (rxdpnext->Host_Control == END_OF_BLOCK) {
				nextblk = (block_no + 1) %
				    (mac_control->rings[ring_no].block_count);
				rxdpnext = mac_control->rings[ring_no].rx_blocks
				    [nextblk].block_virt_addr;
			}
			if (rxdpnext->Control_2 & BIT(0))

#endif

#ifndef	CONFIG_2BUFF_MODE
		skb = dev_alloc_skb(size + NET_IP_ALIGN);
#else
		skb = dev_alloc_skb(dev->mtu + ALIGN_SIZE + BUF0_LEN + 4);
				    /*BUF0_LEN + */ 22);
#endif
		if (!skb) {
			DBG_PRINT(ERR_DBG, "%s: Out of ", dev->name);
			DBG_PRINT(ERR_DBG, "memory to allocate SKBs\n");
			if (first_rxdp) {
				wmb();
				first_rxdp->Control_1 |= RXD_OWN_XENA;
			}
			return -ENOMEM;
		}
#ifndef	CONFIG_2BUFF_MODE
		skb_reserve(skb, NET_IP_ALIGN);
		memset(rxdp, 0, sizeof(RxD_t));
		rxdp->Buffer0_ptr = pci_map_single
		    (nic->pdev, skb->data, size, PCI_DMA_FROMDEVICE);
		rxdp->Control_2 &= (~MASK_BUFFER0_SIZE);
		rxdp->Control_2 |= SET_BUFFER0_SIZE(size);
		rxdp->Host_Control = (unsigned long) (skb);
		if (alloc_tab & ((1 << rxsync_frequency) - 1))
			rxdp->Control_1 |= RXD_OWN_XENA;
		off++;
		off %= (MAX_RXDS_PER_BLOCK + 1);
		mac_control->rings[ring_no].rx_curr_put_info.offset = off;
#else
		ba = &mac_control->rings[ring_no].ba[block_no][off];
		skb_reserve(skb, BUF0_LEN);
		tmp = ((unsigned long) skb->data & ALIGN_SIZE);
		if (tmp)
			skb_reserve(skb, (ALIGN_SIZE + 1) - tmp);

		memset(rxdp, 0, sizeof(RxD_t));
		rxdp->Buffer2_ptr = pci_map_single
		    (nic->pdev, skb->data, dev->mtu + BUF0_LEN + 4,
		     PCI_DMA_FROMDEVICE);
		rxdp->Buffer0_ptr =
		    pci_map_single(nic->pdev, ba->ba_0, BUF0_LEN,

		    pci_map_single(nic->pdev, ba->ba_1, BUF1_LEN,
				   PCI_DMA_FROMDEVICE);

		rxdp->Control_2 = SET_BUFFER2_SIZE(dev->mtu + 4);
		rxdp->Control_2 |= SET_BUFFER0_SIZE(BUF0_LEN);
		rxdp->Control_2 |= SET_BUFFER1_SIZE(1);	/* dummy. */
		rxdp->Control_2 |= BIT(0);	/* Set Buffer_Empty bit. */
		rxdp->Host_Control = (u64) ((unsigned long) (skb));
		if (alloc_tab & ((1 << rxsync_frequency) - 1))
			rxdp->Control_1 |= RXD_OWN_XENA;
		off++;
		mac_control->rings[ring_no].rx_curr_put_info.offset = off;
#endif
		rxdp->Control_2 |= SET_RXD_MARKER;

		if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
			if (first_rxdp) {
				wmb();
				first_rxdp->Control_1 |= RXD_OWN_XENA;
			}
			first_rxdp = rxdp;
		}
		atomic_inc(&nic->rx_bufs_left[ring_no]);
		alloc_tab++;
	}

      end:
	/* Transfer ownership of first descriptor to adapter just before
	 * exiting. Before that, use memory barrier so that ownership
	 * and other fields are seen by adapter correctly.
	 */
	if (first_rxdp) {
		wmb();
		first_rxdp->Control_1 |= RXD_OWN_XENA;
	}

	return SUCCESS;
}

/**
 *  free_rx_buffers - Frees all Rx buffers
 *  @sp: device private variable.
 *  Description:
 *  This function will free all Rx buffers allocated by host.
 *  Return Value:
 *  NONE.

	mac_control = &sp->mac_control;
	config = &sp->config;

	for (i = 0; i < config->rx_ring_num; i++) {
		for (j = 0, blk = 0; j < config->rx_cfg[i].num_rxd; j++) {
			off = j % (MAX_RXDS_PER_BLOCK + 1);
			rxdp = mac_control->rings[i].rx_blocks[blk].
				block_virt_addr + off;

#ifndef CONFIG_2BUFF_MODE
			if (rxdp->Control_1 == END_OF_BLOCK) {

						 HEADER_SNAP_SIZE,
						 PCI_DMA_FROMDEVICE);
#else
				ba = &mac_control->rings[i].ba[blk][off];
				pci_unmap_single(sp->pdev, (dma_addr_t)
						 rxdp->Buffer0_ptr,
						 BUF0_LEN,

						 PCI_DMA_FROMDEVICE);
				pci_unmap_single(sp->pdev, (dma_addr_t)
						 rxdp->Buffer2_ptr,
						 dev->mtu + BUF0_LEN + 4,
						 PCI_DMA_FROMDEVICE);
#endif
				dev_kfree_skb(skb);

			}
			memset(rxdp, 0, sizeof(RxD_t));
		}
		mac_control->rings[i].rx_curr_put_info.block_index = 0;
		mac_control->rings[i].rx_curr_get_info.block_index = 0;
		mac_control->rings[i].rx_curr_put_info.offset = 0;
		mac_control->rings[i].rx_curr_get_info.offset = 0;
		atomic_set(&sp->rx_bufs_left[i], 0);
		DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
			  dev->name, buf_cnt, i);

/**
 * s2io_poll - Rx interrupt handler for NAPI support
 * @dev : pointer to the device structure.
 * @budget : The number of packets that were budgeted to be processed
 * during  one pass through the 'Poll" function.
 * Description:
 * Comes into picture only if NAPI support has been incorporated. It does

 * 0 on success and 1 if there are No Rx packets to be processed.
 */

#if defined(CONFIG_S2IO_NAPI)
static int s2io_poll(struct net_device *dev, int *budget)
{
	nic_t *nic = dev->priv;
	int pkt_cnt = 0, org_pkts_to_process;
	int pkts_to_process = *budget, pkt_cnt = 0;
	register u64 val64 = 0;
	rx_curr_get_info_t get_info, put_info;
	int i, get_block, put_block, get_offset, put_offset, ring_bufs;
#ifndef CONFIG_2BUFF_MODE
	u16 val16, cksum;
#endif
	struct sk_buff *skb;
	RxD_t *rxdp;
	mac_info_t *mac_control;
	struct config_param *config;
	XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
	u64 val64;
	int i;

	atomic_inc(&nic->isr_cnt);
	mac_control = &nic->mac_control;
	config = &nic->config;

	nic->pkts_to_process = *budget;
	if (nic->pkts_to_process > dev->quota)
		nic->pkts_to_process = dev->quota;
	org_pkts_to_process = nic->pkts_to_process;

	val64 = readq(&bar0->rx_traffic_int);
	writeq(val64, &bar0->rx_traffic_int);

	for (i = 0; i < config->rx_ring_num; i++) {
		rx_intr_handler(&mac_control->rings[i]);
		pkt_cnt = org_pkts_to_process - nic->pkts_to_process;
		if (!nic->pkts_to_process) {
			/* Quota for the current iteration has been met */
			goto no_rx;
		rxdp = nic->rx_blocks[i][get_block].block_virt_addr +
		    get_info.offset;
#ifndef	CONFIG_2BUFF_MODE
		get_offset = (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
		    get_info.offset;
#ifndef CONFIG_S2IO_NAPI
		spin_lock(&nic->put_lock);
		put_offset = nic->put_pos;
		spin_unlock(&nic->put_lock);
#else
		put_offset = (put_block * (MAX_RXDS_PER_BLOCK + 1)) +
		    put_info.offset;
#endif
		while ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
		       (((get_offset + 1) % ring_bufs) != put_offset)) {
			if (--pkts_to_process < 0) {
				goto no_rx;
			}
			if (rxdp->Control_1 == END_OF_BLOCK) {
				rxdp =
				    (RxD_t *) ((unsigned long) rxdp->
					       Control_2);
				get_info.offset++;
				get_info.offset %=
				    (MAX_RXDS_PER_BLOCK + 1);
				get_block++;
				get_block %= nic->block_count[i];
				mac_control->rx_curr_get_info[i].
				    offset = get_info.offset;
				mac_control->rx_curr_get_info[i].
				    block_index = get_block;
				continue;
			}
			get_offset =
			    (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
			    get_info.offset;
			skb =
			    (struct sk_buff *) ((unsigned long) rxdp->
						Host_Control);
			if (skb == NULL) {
				DBG_PRINT(ERR_DBG, "%s: The skb is ",
					  dev->name);
				DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
				goto no_rx;
			}
			val64 = RXD_GET_BUFFER0_SIZE(rxdp->Control_2);
			val16 = (u16) (val64 >> 48);
			cksum = RXD_GET_L4_CKSUM(rxdp->Control_1);
			pci_unmap_single(nic->pdev, (dma_addr_t)
					 rxdp->Buffer0_ptr,
					 dev->mtu +
					 HEADER_ETHERNET_II_802_3_SIZE +
					 HEADER_802_2_SIZE +
					 HEADER_SNAP_SIZE,
					 PCI_DMA_FROMDEVICE);
			rx_osm_handler(nic, val16, rxdp, i);
			pkt_cnt++;
			get_info.offset++;
			get_info.offset %= (MAX_RXDS_PER_BLOCK + 1);
			rxdp =
			    nic->rx_blocks[i][get_block].block_virt_addr +
			    get_info.offset;
			mac_control->rx_curr_get_info[i].offset =
			    get_info.offset;
		}
#else
		get_offset = (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
		    get_info.offset;
#ifndef CONFIG_S2IO_NAPI
		spin_lock(&nic->put_lock);
		put_offset = nic->put_pos;
		spin_unlock(&nic->put_lock);
#else
		put_offset = (put_block * (MAX_RXDS_PER_BLOCK + 1)) +
		    put_info.offset;
#endif
		while (((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
			!(rxdp->Control_2 & BIT(0))) &&
		       (((get_offset + 1) % ring_bufs) != put_offset)) {
			if (--pkts_to_process < 0) {
				goto no_rx;
			}
			skb = (struct sk_buff *) ((unsigned long)
						  rxdp->Host_Control);
			if (skb == NULL) {
				DBG_PRINT(ERR_DBG, "%s: The skb is ",
					  dev->name);
				DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
				goto no_rx;
			}

			pci_unmap_single(nic->pdev, (dma_addr_t)
					 rxdp->Buffer0_ptr,
					 BUF0_LEN, PCI_DMA_FROMDEVICE);
			pci_unmap_single(nic->pdev, (dma_addr_t)
					 rxdp->Buffer1_ptr,
					 BUF1_LEN, PCI_DMA_FROMDEVICE);
			pci_unmap_single(nic->pdev, (dma_addr_t)
					 rxdp->Buffer2_ptr,
					 dev->mtu + 22,
					 PCI_DMA_FROMDEVICE);
			ba = &nic->ba[i][get_block][get_info.offset];

			rx_osm_handler(nic, rxdp, i, ba);

			get_info.offset++;
			mac_control->rx_curr_get_info[i].offset =
			    get_info.offset;
			rxdp =
			    nic->rx_blocks[i][get_block].block_virt_addr +
			    get_info.offset;

			if (get_info.offset &&
			    (!(get_info.offset % MAX_RXDS_PER_BLOCK))) {
				get_info.offset = 0;
				mac_control->rx_curr_get_info[i].
				    offset = get_info.offset;
				get_block++;
				get_block %= nic->block_count[i];
				mac_control->rx_curr_get_info[i].
				    block_index = get_block;
				rxdp =
				    nic->rx_blocks[i][get_block].
				    block_virt_addr;
			}
			get_offset =
			    (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
			    get_info.offset;
			pkt_cnt++;
		}
#endif
	}
	if (!pkt_cnt)
		pkt_cnt = 1;

	*budget -= pkt_cnt;
	netif_rx_complete(dev);

	for (i = 0; i < config->rx_ring_num; i++) {
		if (fill_rx_buffers(nic, i) == -ENOMEM) {
			DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
			DBG_PRINT(ERR_DBG, " in Rx Poll!!\n");

	}
	/* Re enable the Rx interrupts. */
	en_dis_able_nic_intrs(nic, RX_TRAFFIC_INTR, ENABLE_INTRS);
	atomic_dec(&nic->isr_cnt);
	return 0;

no_rx:
	dev->quota -= pkt_cnt;
	*budget -= pkt_cnt;

	for (i = 0; i < config->rx_ring_num; i++) {
		if (fill_rx_buffers(nic, i) == -ENOMEM) {
			DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
			DBG_PRINT(ERR_DBG, " in Rx Poll!!\n");
			break;
		}
	}
	atomic_dec(&nic->isr_cnt);
	return 1;
}
#endif

/**
 *  rx_intr_handler - Rx interrupt handler
 *  @nic: device private variable.
 *  Description:
 *  If the interrupt is because of a received frame or if the
 *  receive ring contains fresh as yet un-processed frames,this function is
 *  called. It picks out the RxD at which place the last Rx processing had
 *  stopped and sends the skb to the OSM's Rx handler and then increments
 *  the offset.
 *  Return Value:
 *  NONE.
 */
static void rx_intr_handler(ring_info_t *ring_data)
static void rx_intr_handler(struct s2io_nic *nic)
{
	nic_t *nic = ring_data->nic;
	struct net_device *dev = (struct net_device *) nic->dev;
	int get_block, get_offset, put_block, put_offset, ring_bufs;
	rx_curr_get_info_t get_info, put_info;
	RxD_t *rxdp;
	struct sk_buff *skb;
#ifndef CONFIG_S2IO_NAPI
	int pkt_cnt = 0;
#endif
	register u64 val64 = 0;
	int get_block, get_offset, put_block, put_offset, ring_bufs;
	int i, pkt_cnt = 0;
	mac_info_t *mac_control;
	struct config_param *config;
#ifdef CONFIG_2BUFF_MODE
	buffAdd_t *ba;
#endif
	spin_lock(&nic->rx_lock);
	if (atomic_read(&nic->card_state) == CARD_DOWN) {
		DBG_PRINT(INTR_DBG, "%s: %s going down for reset\n",
			  __FUNCTION__, dev->name);
		spin_unlock(&nic->rx_lock);
		return;
	}

	get_info = ring_data->rx_curr_get_info;
	get_block = get_info.block_index;
	put_info = ring_data->rx_curr_put_info;
	put_block = put_info.block_index;
	ring_bufs = get_info.ring_len+1;
	rxdp = ring_data->rx_blocks[get_block].block_virt_addr +
	 */
	val64 = readq(&bar0->rx_traffic_int);
	writeq(val64, &bar0->rx_traffic_int);

	for (i = 0; i < config->RxRingNum; i++) {
		get_info = mac_control->rx_curr_get_info[i];
		get_block = get_info.block_index;
		put_info = mac_control->rx_curr_put_info[i];
		put_block = put_info.block_index;
		ring_bufs = config->rx_cfg[i].NumRxd;
		rxdp = nic->rx_blocks[i][get_block].block_virt_addr +
		    get_info.offset;
#ifndef	CONFIG_2BUFF_MODE
		get_offset = (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
		    get_info.offset;
	get_offset = (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
		get_info.offset;
#ifndef CONFIG_S2IO_NAPI
	spin_lock(&nic->put_lock);
	put_offset = ring_data->put_pos;
	spin_unlock(&nic->put_lock);
#else
	put_offset = (put_block * (MAX_RXDS_PER_BLOCK + 1)) +
		put_info.offset;
#endif
	while (RXD_IS_UP2DT(rxdp) &&
	       (((get_offset + 1) % ring_bufs) != put_offset)) {
		skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
		if (skb == NULL) {
			DBG_PRINT(ERR_DBG, "%s: The skb is ",
				  dev->name);
			DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
			spin_unlock(&nic->rx_lock);
			return;
				get_block %= nic->block_count[i];
				mac_control->rx_curr_get_info[i].
				    offset = get_info.offset;
				mac_control->rx_curr_get_info[i].
				    block_index = get_block;
				continue;
			}
			get_offset =
			    (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
			    get_info.offset;
			skb = (struct sk_buff *) ((unsigned long)
						  rxdp->Host_Control);
			if (skb == NULL) {
				DBG_PRINT(ERR_DBG, "%s: The skb is ",
					  dev->name);
				DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
				return;
			}
			val64 = RXD_GET_BUFFER0_SIZE(rxdp->Control_2);
			val16 = (u16) (val64 >> 48);
			cksum = RXD_GET_L4_CKSUM(rxdp->Control_1);
			pci_unmap_single(nic->pdev, (dma_addr_t)
					 rxdp->Buffer0_ptr,
					 dev->mtu +
					 HEADER_ETHERNET_II_802_3_SIZE +
					 HEADER_802_2_SIZE +
					 HEADER_SNAP_SIZE,
					 PCI_DMA_FROMDEVICE);
			rx_osm_handler(nic, val16, rxdp, i);
			get_info.offset++;
			get_info.offset %= (MAX_RXDS_PER_BLOCK + 1);
			rxdp =
			    nic->rx_blocks[i][get_block].block_virt_addr +
			    get_info.offset;
			mac_control->rx_curr_get_info[i].offset =
			    get_info.offset;
			pkt_cnt++;
			if ((indicate_max_pkts)
			    && (pkt_cnt > indicate_max_pkts))
				break;
		}
#ifndef CONFIG_2BUFF_MODE
		pci_unmap_single(nic->pdev, (dma_addr_t)
				 rxdp->Buffer0_ptr,
				 dev->mtu +
				 HEADER_ETHERNET_II_802_3_SIZE +
				 HEADER_802_2_SIZE +
				 HEADER_SNAP_SIZE,
				 PCI_DMA_FROMDEVICE);
#else
		pci_unmap_single(nic->pdev, (dma_addr_t)
				 rxdp->Buffer0_ptr,
				 BUF0_LEN, PCI_DMA_FROMDEVICE);
		pci_unmap_single(nic->pdev, (dma_addr_t)
				 rxdp->Buffer1_ptr,
				 BUF1_LEN, PCI_DMA_FROMDEVICE);
		pci_unmap_single(nic->pdev, (dma_addr_t)
				 rxdp->Buffer2_ptr,
				 dev->mtu + BUF0_LEN + 4,
				 PCI_DMA_FROMDEVICE);
#endif
		rx_osm_handler(ring_data, rxdp);
		get_info.offset++;
		ring_data->rx_curr_get_info.offset =
		    get_info.offset;
		rxdp = ring_data->rx_blocks[get_block].block_virt_addr +
		    get_info.offset;
		if (get_info.offset &&
		    (!(get_info.offset % MAX_RXDS_PER_BLOCK))) {
			get_info.offset = 0;
			ring_data->rx_curr_get_info.offset
			    = get_info.offset;
			get_block++;
			get_block %= ring_data->block_count;
			ring_data->rx_curr_get_info.block_index
			    = get_block;
			rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
		}
				DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
				return;
			}

			pci_unmap_single(nic->pdev, (dma_addr_t)
					 rxdp->Buffer0_ptr,
					 BUF0_LEN, PCI_DMA_FROMDEVICE);
			pci_unmap_single(nic->pdev, (dma_addr_t)
					 rxdp->Buffer1_ptr,
					 BUF1_LEN, PCI_DMA_FROMDEVICE);
			pci_unmap_single(nic->pdev, (dma_addr_t)
					 rxdp->Buffer2_ptr,
					 dev->mtu + 22,
					 PCI_DMA_FROMDEVICE);
			ba = &nic->ba[i][get_block][get_info.offset];

		get_offset = (get_block * (MAX_RXDS_PER_BLOCK + 1)) +

			get_info.offset++;
			mac_control->rx_curr_get_info[i].offset =
			    get_info.offset;
			rxdp =
			    nic->rx_blocks[i][get_block].block_virt_addr +
			    get_info.offset;

			if (get_info.offset &&
			    (!(get_info.offset % MAX_RXDS_PER_BLOCK))) {
				get_info.offset = 0;
				mac_control->rx_curr_get_info[i].
				    offset = get_info.offset;
				get_block++;
				get_block %= nic->block_count[i];
				mac_control->rx_curr_get_info[i].
				    block_index = get_block;
				rxdp =
				    nic->rx_blocks[i][get_block].
				    block_virt_addr;
			}
			get_offset =
			    (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
			    get_info.offset;
#ifdef CONFIG_S2IO_NAPI
		nic->pkts_to_process -= 1;
		if (!nic->pkts_to_process)
			break;
#else
		pkt_cnt++;
		if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
			break;
#endif
	}
	spin_unlock(&nic->rx_lock);
}

/**
 *  tx_intr_handler - Transmit interrupt handler
 *  @nic : device private variable
 *  Description:
 *  If an interrupt was raised to indicate DMA complete of the
 *  Tx packet, this function is called. It identifies the last TxD
 *  whose buffer was freed and frees all skbs whose data have already
 *  DMA'ed into the NICs internal memory.
 *  Return Value:
 *  NONE
 */

static void tx_intr_handler(fifo_info_t *fifo_data)
{
	nic_t *nic = fifo_data->nic;
	struct net_device *dev = (struct net_device *) nic->dev;
	tx_curr_get_info_t get_info, put_info;
	struct sk_buff *skb;
	TxD_t *txdlp;
	register u64 val64 = 0;
	int i;
	u16 j, frg_cnt;
	mac_info_t *mac_control;
	struct config_param *config;

	mac_control = &nic->mac_control;
	config = &nic->config;

	get_info = fifo_data->tx_curr_get_info;
	put_info = fifo_data->tx_curr_put_info;
	txdlp = (TxD_t *) fifo_data->list_info[get_info.offset].
	    list_virt_addr;
	while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
	       (get_info.offset != put_info.offset) &&
	       (txdlp->Host_Control)) {
		/* Check for TxD errors */
		if (txdlp->Control_1 & TXD_T_CODE) {
			unsigned long long err;
			err = txdlp->Control_1 & TXD_T_CODE;
			if ((err >> 48) == 0xA) {
				DBG_PRINT(TX_DBG, "TxD returned due \
						to loss of link\n");
		       (txdlp->Host_Control)) {
			/* Check for TxD errors */
			if (txdlp->Control_1 & TXD_T_CODE) {
				unsigned long long err;
				err = txdlp->Control_1 & TXD_T_CODE;
				DBG_PRINT(ERR_DBG, "***TxD error %llx\n",
					  err);
			}
			else {
				DBG_PRINT(ERR_DBG, "***TxD error \
						%llx\n", err);
			if (skb == NULL) {
				DBG_PRINT(ERR_DBG, "%s: Null skb ",
					  dev->name);
				DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
				return;
			}
		}

		skb = (struct sk_buff *) ((unsigned long)
				txdlp->Host_Control);
		if (skb == NULL) {
			DBG_PRINT(ERR_DBG, "%s: Null skb ",
			__FUNCTION__);
			DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
			return;
		}

		frg_cnt = skb_shinfo(skb)->nr_frags;
		nic->tx_pkt_count++;
					 txdlp->Buffer_Pointer,
					 skb->len - skb->data_len,
					 PCI_DMA_TODEVICE);
			if (frg_cnt) {
				TxD_t *temp = txdlp;
				txdlp++;
				for (j = 0; j < frg_cnt; j++, txdlp++) {
					skb_frag_t *frag =
					    &skb_shinfo(skb)->frags[j];
					pci_unmap_page(nic->pdev,
						       (dma_addr_t)
						       txdlp->
						       Buffer_Pointer,
						       frag->size,
						       PCI_DMA_TODEVICE);
				}
				txdlp = temp;
			}
			memset(txdlp, 0,
			       (sizeof(TxD_t) * config->MaxTxDs));

		pci_unmap_single(nic->pdev, (dma_addr_t)
				 txdlp->Buffer_Pointer,
				 skb->len - skb->data_len,
				 PCI_DMA_TODEVICE);
		if (frg_cnt) {
			TxD_t *temp;
			temp = txdlp;
			txdlp++;
			for (j = 0; j < frg_cnt; j++, txdlp++) {
				skb_frag_t *frag =
				    &skb_shinfo(skb)->frags[j];
				if (!txdlp->Buffer_Pointer)
					break;
				pci_unmap_page(nic->pdev,
					       (dma_addr_t)
					       txdlp->
					       Buffer_Pointer,
					       frag->size,
					       PCI_DMA_TODEVICE);
			}
			txdlp = temp;
		}
		memset(txdlp, 0,
		       (sizeof(TxD_t) * fifo_data->max_txds));

		/* Updating the statistics block */
		nic->stats.tx_bytes += skb->len;
		dev_kfree_skb_irq(skb);

		get_info.offset++;
		get_info.offset %= get_info.fifo_len + 1;
		txdlp = (TxD_t *) fifo_data->list_info
		    [get_info.offset].list_virt_addr;
		fifo_data->tx_curr_get_info.offset =
		    get_info.offset;
	}

	spin_lock(&nic->tx_lock);

	spin_unlock(&nic->tx_lock);
}

/**
 *  alarm_intr_handler - Alarm Interrrupt handler
 *  @nic: device private variable
 *  Description: If the interrupt was neither because of Rx packet or Tx
 *  complete, this function is called. If the interrupt was to indicate
 *  a loss of link, the OSM link status handler is invoked for any other
 *  alarm interrupt the block that raised the interrupt is displayed
 *  and a H/W reset is issued.
 *  Return Value:
 *  NONE

static void alarm_intr_handler(struct s2io_nic *nic)
{
	struct net_device *dev = (struct net_device *) nic->dev;
	XENA_dev_config_t __iomem *bar0 = nic->bar0;
	register u64 val64 = 0, err_reg = 0;

	/* Handling link status change error Intr */
	if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
		err_reg = readq(&bar0->mac_rmac_err_reg);
		writeq(err_reg, &bar0->mac_rmac_err_reg);
		if (err_reg & RMAC_LINK_STATE_CHANGE_INT) {
			schedule_work(&nic->set_link_task);
		}
	}

	/* Handling Ecc errors */
	val64 = readq(&bar0->mc_err_reg);
	writeq(val64, &bar0->mc_err_reg);
	if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
		if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
			nic->mac_control.stats_info->sw_stat.
				double_ecc_errs++;
			DBG_PRINT(INIT_DBG, "%s: Device indicates ",
				  dev->name);
			DBG_PRINT(INIT_DBG, "double ECC error!!\n");
			if (nic->device_type != XFRAME_II_DEVICE) {
				/* Reset XframeI only if critical error */
				if (val64 & (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
					     MC_ERR_REG_MIRI_ECC_DB_ERR_1)) {
					netif_stop_queue(dev);
					schedule_work(&nic->rst_timer_task);
				}
			}
		} else {
			nic->mac_control.stats_info->sw_stat.
				single_ecc_errs++;
		}
	}

	/* In case of a serious error, the device will be Reset. */
	val64 = readq(&bar0->serr_source);
	if (val64 & SERR_SOURCE_ANY) {
		DBG_PRINT(ERR_DBG, "%s: Device indicates ", dev->name);
		DBG_PRINT(ERR_DBG, "serious error %llx!!\n", 
			  (unsigned long long)val64);
		netif_stop_queue(dev);
		schedule_work(&nic->rst_timer_task);
	}

	/*
	 * Also as mentioned in the latest Errata sheets if the PCC_FB_ECC
	 * Error occurs, the adapter will be recycled by disabling the
	 * adapter enable bit and enabling it again after the device
	 * becomes Quiescent.
	 */
	val64 = readq(&bar0->pcc_err_reg);

	/* Other type of interrupts are not being handled now,  TODO */
}

/**
 *  wait_for_cmd_complete - waits for a command to complete.
 *  @sp : private member of the device structure, which is a pointer to the
 *  s2io_nic structure.
 *  Description: Function that waits for a command to Write into RMAC
 *  ADDR DATA registers to be completed and returns either success or
 *  error depending on whether the command was complete or not.
 *  Return value:
 *   SUCCESS on success and FAILURE on failure.
 */

int wait_for_cmd_complete(nic_t * sp)
{
	XENA_dev_config_t __iomem *bar0 = sp->bar0;
	int ret = FAILURE, cnt = 0;
	u64 val64;


			ret = SUCCESS;
			break;
		}
		msleep(50);
		schedule_timeout(HZ / 20);
		if (cnt++ > 10)
			break;
	}

	return ret;
}

/**
 *  s2io_reset - Resets the card.
 *  @sp : private member of the device structure.
 *  Description: Function to Reset the card. This function then also
 *  restores the previously saved PCI configuration space registers as
 *  the card reset also resets the configuration space.
 *  Return value:
 *  void.
 */

void s2io_reset(nic_t * sp)
{
	XENA_dev_config_t __iomem *bar0 = sp->bar0;
	u64 val64;
	u16 subid, pci_cmd;

	/* Back up  the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
	pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));

	val64 = SW_RESET_ALL;
	writeq(val64, &bar0->sw_reset);

	/*
	 * At this stage, if the PCI write is indeed completed, the
	 * card is reset and so is the PCI Config space of the device.
	 * So a read cannot be issued at this stage on any of the
	 * registers to ensure the write into "sw_reset" register
	 * has gone through.
	 * Question: Is there any system call that will explicitly force
	 * all the write commands still pending on the bus to be pushed
	 * through?
	 * As of now I'am just giving a 250ms delay and hoping that the
	 * PCI write to sw_reset register is done by this time.
	 */
	msleep(250);

	/* Restore the PCI state saved during initialization. */
	pci_restore_state(sp->pdev, sp->config_space);
	pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
				     pci_cmd);
	s2io_init_pci(sp);

	msleep(250);

	/* Set swapper to enable I/O register access */
	s2io_set_swapper(sp);

	/* Clear certain PCI/PCI-X fields after reset */
	if (sp->device_type == XFRAME_II_DEVICE) {
		/* Clear parity err detect bit */
		pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);

		/* Clearing PCIX Ecc status register */
		pci_write_config_dword(sp->pdev, 0x68, 0x7C);

		/* Clearing PCI_STATUS error reflected here */
		writeq(BIT(62), &bar0->txpic_int_reg);
	}

	/* Reset device statistics maintained by OS */
	memset(&sp->stats, 0, sizeof (struct net_device_stats));

	/* SXE-002: Configure link and activity LED to turn it off */
	subid = sp->pdev->subsystem_device;
	if (((subid & 0xFF) >= 0x07) &&
	    (sp->device_type == XFRAME_I_DEVICE)) {
		val64 = readq(&bar0->gpio_control);
		val64 |= 0x0000800000000000ULL;
		writeq(val64, &bar0->gpio_control);
		val64 = 0x0411040400000000ULL;
		writeq(val64, (void __iomem *) ((u8 *) bar0 + 0x2700));
	}

	/*
	 * Clear spurious ECC interrupts that would have occured on
	 * XFRAME II cards after reset.
	 */
	if (sp->device_type == XFRAME_II_DEVICE) {
		val64 = readq(&bar0->pcc_err_reg);
		writeq(val64, &bar0->pcc_err_reg);
	}

	sp->device_enabled_once = FALSE;
}

/**
 *  s2io_set_swapper - to set the swapper controle on the card
 *  @sp : private member of the device structure,
 *  pointer to the s2io_nic structure.
 *  Description: Function to set the swapper control on the card
 *  correctly depending on the 'endianness' of the system.
 *  Return value:
 *  SUCCESS on success and FAILURE on failure.

int s2io_set_swapper(nic_t * sp)
{
	struct net_device *dev = sp->dev;
	XENA_dev_config_t __iomem *bar0 = sp->bar0;
	u64 val64, valt, valr;

	/*
	 * Set proper endian settings and verify the same by reading
	 * the PIF Feed-back register.
	 */

	val64 = readq(&bar0->pif_rd_swapper_fb);
	if (val64 != 0x0123456789ABCDEFULL) {
		int i = 0;
		u64 value[] = { 0xC30000C3C30000C3ULL,   /* FE=1, SE=1 */
				0x8100008181000081ULL,  /* FE=1, SE=0 */
				0x4200004242000042ULL,  /* FE=0, SE=1 */
				0};                     /* FE=0, SE=0 */

		while(i<4) {
			writeq(value[i], &bar0->swapper_ctrl);
			val64 = readq(&bar0->pif_rd_swapper_fb);
			if (val64 == 0x0123456789ABCDEFULL)
				break;
			i++;
		}
		if (i == 4) {
			DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
				dev->name);
			DBG_PRINT(ERR_DBG, "feedback read %llx\n",
				(unsigned long long) val64);
			return FAILURE;
		}
		valr = value[i];
	} else {
		valr = readq(&bar0->swapper_ctrl);
	}

	valt = 0x0123456789ABCDEFULL;
	writeq(valt, &bar0->xmsi_address);
	val64 = readq(&bar0->xmsi_address);

	if(val64 != valt) {
		int i = 0;
		u64 value[] = { 0x00C3C30000C3C300ULL,  /* FE=1, SE=1 */
				0x0081810000818100ULL,  /* FE=1, SE=0 */
				0x0042420000424200ULL,  /* FE=0, SE=1 */
				0};                     /* FE=0, SE=0 */

		while(i<4) {
			writeq((value[i] | valr), &bar0->swapper_ctrl);
			writeq(valt, &bar0->xmsi_address);
			val64 = readq(&bar0->xmsi_address);
			if(val64 == valt)
				break;
			i++;
		}
		if(i == 4) {
			unsigned long long x = val64;
			DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
			DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
			return FAILURE;
		}
	}
	val64 = readq(&bar0->swapper_ctrl);
	val64 &= 0xFFFF000000000000ULL;

#ifdef  __BIG_ENDIAN
	/*
	 * The device by default set to a big endian format, so a
	 * big endian driver need not set anything.
	 */
	val64 |= (SWAPPER_CTRL_TXP_FE |
	val64 = (SWAPPER_CTRL_PIF_R_FE |
		 SWAPPER_CTRL_PIF_R_SE |
		 SWAPPER_CTRL_PIF_W_FE |
		 SWAPPER_CTRL_PIF_W_SE |
		 SWAPPER_CTRL_TXP_FE |
		 SWAPPER_CTRL_TXP_SE |
		 SWAPPER_CTRL_TXD_R_FE |
		 SWAPPER_CTRL_TXD_W_FE |

		 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
	writeq(val64, &bar0->swapper_ctrl);
#else
	/*
	 * Initially we enable all bits to make it accessible by the
	 * driver, then we selectively enable only those bits that
	 * we want to set.
	 */
	val64 |= (SWAPPER_CTRL_TXP_FE |
	val64 = (SWAPPER_CTRL_PIF_R_FE |
		 SWAPPER_CTRL_PIF_R_SE |
		 SWAPPER_CTRL_PIF_W_FE |
		 SWAPPER_CTRL_PIF_W_SE |
		 SWAPPER_CTRL_TXP_FE |
		 SWAPPER_CTRL_TXP_SE |
		 SWAPPER_CTRL_TXD_R_FE |
		 SWAPPER_CTRL_TXD_R_SE |

		 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
	writeq(val64, &bar0->swapper_ctrl);
#endif
	val64 = readq(&bar0->swapper_ctrl);

	/*
	 * Verifying if endian settings are accurate by reading a
	 * feedback register.
	 */
	val64 = readq(&bar0->pif_rd_swapper_fb);

 * Functions defined below concern the OS part of the driver *
 * ********************************************************* */

/**
 *  s2io_open - open entry point of the driver
 *  @dev : pointer to the device structure.
 *  Description:
 *  This function is the open entry point of the driver. It mainly calls a
 *  function to allocate Rx buffers and inserts them into the buffer
 *  descriptors and then enables the Rx part of the NIC.
 *  Return value:
 *  0 on success and an appropriate (-)ve integer as defined in errno.h
 *   file on failure.

int s2io_open(struct net_device *dev)
{
	nic_t *sp = dev->priv;
	int err = 0;
	mac_info_t *mac_control;
	struct config_param *config;

	/*
	 * Make sure you have link off by default every time
	 * Make sure you have link off by default every time 
	 * Nic is initialized
	 */
	netif_carrier_off(dev);
	sp->last_link_state = 0;

	/* Initialize H/W and enable interrupts */
	if (s2io_card_up(sp)) {
		DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
			  dev->name);
		err = -ENODEV;
		goto hw_init_failed;
	}

	/* After proper initialization of H/W, register ISR */
	err = request_irq((int) sp->pdev->irq, s2io_isr, SA_SHIRQ,
			  sp->name, dev);
	if (err) {
		s2io_reset(sp);
		DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
			  dev->name);
		goto isr_registration_failed;
	}

	if (s2io_set_mac_addr(dev, dev->dev_addr) == FAILURE) {
		DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
		err = -ENODEV;
		goto setting_mac_address_failed;
	}


	/* Setting its receive mode */
	s2io_set_multicast(dev);

	/* 
	 * Initializing the Rx buffers. For now we are considering only 1 
	 * Rx ring and initializing buffers into 1016 RxDs or 8 Rx blocks
	 */
	mac_control = &sp->mac_control;
	config = &sp->config;

	for (i = 0; i < config->RxRingNum; i++) {
		if ((ret = fill_rx_buffers(sp, i))) {
			DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
				  dev->name);
			s2io_reset(sp);
			free_irq(dev->irq, dev);
			free_rx_buffers(sp);
			return -ENOMEM;
		}
		DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
			  atomic_read(&sp->rx_bufs_left[i]));
	}

	/* Enable tasklet for the device */
	tasklet_init(&sp->task, s2io_tasklet, (unsigned long) dev);

	/* Enable Rx Traffic and interrupts on the NIC */
	if (start_nic(sp)) {
		DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
		tasklet_kill(&sp->task);
		s2io_reset(sp);
		free_irq(dev->irq, dev);
		free_rx_buffers(sp);
		return -ENODEV;
	}

	sp->device_close_flag = FALSE;	/* Device is up and running. */
	netif_start_queue(dev);

	return 0;

setting_mac_address_failed:
	free_irq(sp->pdev->irq, dev);
isr_registration_failed:
	del_timer_sync(&sp->alarm_timer);
	s2io_reset(sp);
hw_init_failed:
	return err;
}

/**

int s2io_close(struct net_device *dev)
{
	nic_t *sp = dev->priv;
	flush_scheduled_work();
	register u64 val64 = 0;
	u16 cnt = 0;
	unsigned long flags;

	spin_lock_irqsave(&sp->tx_lock, flags);
	netif_stop_queue(dev);
	/* Reset card, kill tasklet and free Tx and Rx buffers. */
	s2io_card_down(sp);

	free_irq(sp->pdev->irq, dev);
	stop_nic(sp);

	/* 
	 * If the device tasklet is running, wait till its done 
	 * before killing it 
	 */
	while (atomic_read(&(sp->tasklet_status))) {
		set_current_state(TASK_UNINTERRUPTIBLE);
		schedule_timeout(HZ / 10);
	}
	tasklet_kill(&sp->task);

	/*  Free the Registered IRQ */
	free_irq(dev->irq, dev);

	/* Flush all scheduled tasks */
	if (sp->task_flag == 1) {
		DBG_PRINT(INFO_DBG, "%s: Calling close from a task\n",
			  dev->name);
	} else {
		flush_scheduled_work();
	}

	/* Check if the device is Quiescent and then Reset the NIC */
	do {
		val64 = readq(&bar0->adapter_status);
		if (verify_xena_quiescence(val64, sp->device_enabled_once)) {
			break;
		}

		set_current_state(TASK_UNINTERRUPTIBLE);
		schedule_timeout(HZ / 20);
		cnt++;
		if (cnt == 10) {
			DBG_PRINT(ERR_DBG,
				  "s2io_close:Device not Quiescent ");
			DBG_PRINT(ERR_DBG, "adaper status reads 0x%llx\n",
				  (unsigned long long) val64);
			break;
		}
	} while (1);
	s2io_reset(sp);

	/* Free all Tx Buffers waiting for transmission */
	free_tx_buffers(sp);

	/*  Free all Rx buffers allocated by host */
	free_rx_buffers(sp);

	sp->device_close_flag = TRUE;	/* Device is shut down. */
	spin_unlock_irqrestore(&sp->tx_lock, flags);

	return 0;
}


	u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
	register u64 val64;
	TxD_t *txdp;
	TxFIFO_element_t __iomem *tx_fifo;
	unsigned long flags;
#ifdef NETIF_F_TSO
	int mss;
#endif
	u16 vlan_tag = 0;
	int vlan_priority = 0;
	mac_info_t *mac_control;
	struct config_param *config;
	XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;

	mac_control = &sp->mac_control;
	config = &sp->config;

	DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);

	spin_lock_irqsave(&sp->tx_lock, flags);
	if (atomic_read(&sp->card_state) == CARD_DOWN) {
		DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
			  dev->name);
		dev_kfree_skb(skb);
		spin_unlock_irqrestore(&sp->tx_lock, flags);
		dev_kfree_skb(skb);
		return 0;
	}

	queue = 0;
	/* Multi FIFO Tx is disabled for now. */
	if (!queue && tx_prio) {
		u8 x = (skb->data)[5];
		queue = x % config->TxFIFONum;
	}

	/* Get Fifo number to Transmit based on vlan priority */
	if (sp->vlgrp && vlan_tx_tag_present(skb)) {
		vlan_tag = vlan_tx_tag_get(skb);
		vlan_priority = vlan_tag >> 13;
		queue = config->fifo_mapping[vlan_priority];
	}

	put_off = (u16) mac_control->fifos[queue].tx_curr_put_info.offset;
	get_off = (u16) mac_control->fifos[queue].tx_curr_get_info.offset;
	txdp = (TxD_t *) mac_control->fifos[queue].list_info[put_off].
		list_virt_addr;

	queue_len = mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1;
	/* Avoid "put" pointer going beyond "get" pointer */
	if (txdp->Host_Control || (((put_off + 1) % queue_len) == get_off)) {
		DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
		netif_stop_queue(dev);
		dev_kfree_skb(skb);
		spin_unlock_irqrestore(&sp->tx_lock, flags);
		return 0;
	}

	/* A buffer with no data will be dropped */
	if (!skb->len) {
		DBG_PRINT(TX_DBG, "%s:Buffer has no data..\n", dev->name);
		dev_kfree_skb(skb);
		spin_unlock_irqrestore(&sp->tx_lock, flags);
		return 0;
	}

#ifdef NETIF_F_TSO
	mss = skb_shinfo(skb)->tso_size;
	if (mss) {

	frg_cnt = skb_shinfo(skb)->nr_frags;
	frg_len = skb->len - skb->data_len;

	txdp->Host_Control = (unsigned long) skb;
	txdp->Buffer_Pointer = pci_map_single
	    (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE);
	txdp->Host_Control = (unsigned long) skb;
	if (skb->ip_summed == CHECKSUM_HW) {
		txdp->Control_2 |=
		    (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN |
		     TXD_TX_CKO_UDP_EN);
	}

	txdp->Control_2 |= config->tx_intr_type;

	if (sp->vlgrp && vlan_tx_tag_present(skb)) {
		txdp->Control_2 |= TXD_VLAN_ENABLE;
		txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
	}

	txdp->Control_1 |= (TXD_BUFFER0_SIZE(frg_len) |
			    TXD_GATHER_CODE_FIRST);

	/* For fragmented SKB. */
	for (i = 0; i < frg_cnt; i++) {
		skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
		/* A '0' length fragment will be ignored */
		if (!frag->size)
			continue;
		txdp++;
		txdp->Buffer_Pointer = (u64) pci_map_page
		    (sp->pdev, frag->page, frag->page_offset,

	txdp->Control_1 |= TXD_GATHER_CODE_LAST;

	tx_fifo = mac_control->tx_FIFO_start[queue];
	val64 = mac_control->fifos[queue].list_info[put_off].list_phy_addr;
	writeq(val64, &tx_fifo->TxDL_Pointer);

	val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
		 TX_FIFO_LAST_LIST);

#ifdef NETIF_F_TSO
	if (mss)
		val64 |= TX_FIFO_SPECIAL_FUNC;
#endif
	writeq(val64, &tx_fifo->List_Control);

	mmiowb();
	val64 = readq(&bar0->general_int_status);

	put_off++;
	put_off %= mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1;
	mac_control->fifos[queue].tx_curr_put_info.offset = put_off;

	/* Avoid "put" pointer going beyond "get" pointer */
	if (((put_off + 1) % queue_len) == get_off) {

	return 0;
}

static void
s2io_alarm_handle(unsigned long data)
{
	nic_t *sp = (nic_t *)data;

	alarm_intr_handler(sp);
	mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
}

static void s2io_txpic_intr_handle(nic_t *sp)
{
	XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
	u64 val64;

	val64 = readq(&bar0->pic_int_status);
	if (val64 & PIC_INT_GPIO) {
		val64 = readq(&bar0->gpio_int_reg);
		if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
		    (val64 & GPIO_INT_REG_LINK_UP)) {
			val64 |=  GPIO_INT_REG_LINK_DOWN;
			val64 |= GPIO_INT_REG_LINK_UP;
			writeq(val64, &bar0->gpio_int_reg);
			goto masking;
		}

		if (((sp->last_link_state == LINK_UP) &&
			(val64 & GPIO_INT_REG_LINK_DOWN)) ||
		((sp->last_link_state == LINK_DOWN) &&
		(val64 & GPIO_INT_REG_LINK_UP))) {
			val64 = readq(&bar0->gpio_int_mask);
			val64 |=  GPIO_INT_MASK_LINK_DOWN;
			val64 |= GPIO_INT_MASK_LINK_UP;
			writeq(val64, &bar0->gpio_int_mask);
			s2io_set_link((unsigned long)sp);
		}
masking:
		if (sp->last_link_state == LINK_UP) {
			/*enable down interrupt */
			val64 = readq(&bar0->gpio_int_mask);
			/* unmasks link down intr */
			val64 &=  ~GPIO_INT_MASK_LINK_DOWN;
			/* masks link up intr */
			val64 |= GPIO_INT_MASK_LINK_UP;
			writeq(val64, &bar0->gpio_int_mask);
		} else {
			/*enable UP Interrupt */
			val64 = readq(&bar0->gpio_int_mask);
			/* unmasks link up interrupt */
			val64 &= ~GPIO_INT_MASK_LINK_UP;
			/* masks link down interrupt */
			val64 |=  GPIO_INT_MASK_LINK_DOWN;
			writeq(val64, &bar0->gpio_int_mask);
		}
	}
}

/**
 *  s2io_isr - ISR handler of the device .
 *  @irq: the irq of the device.
 *  @dev_id: a void pointer to the dev structure of the NIC.
 *  @pt_regs: pointer to the registers pushed on the stack.
 *  Description:  This function is the ISR handler of the device. It
 *  identifies the reason for the interrupt and calls the relevant
 *  service routines. As a contongency measure, this ISR allocates the
 *  recv buffers, if their numbers are below the panic value which is
 *  presently set to 25% of the original number of rcv buffers allocated.
 *  Return value:
 *   IRQ_HANDLED: will be returned if IRQ was handled by this routine
 *   IRQ_NONE: will be returned if interrupt is not from our device
 */
static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs)
{
	struct net_device *dev = (struct net_device *) dev_id;
	nic_t *sp = dev->priv;
	XENA_dev_config_t __iomem *bar0 = sp->bar0;
	int i;
	u64 reason = 0, val64;
#endif
	u64 reason = 0;
	mac_info_t *mac_control;
	struct config_param *config;

	atomic_inc(&sp->isr_cnt);
	mac_control = &sp->mac_control;
	config = &sp->config;

	/*
	 * Identify the cause for interrupt and call the appropriate
	 * interrupt handler. Causes for the interrupt could be;
	 * 1. Rx of packet.
	 * 2. Tx complete.
	 * 3. Link down.
	 * 4. Error in any functional blocks of the NIC.
	 */
	reason = readq(&bar0->general_int_status);

	if (!reason) {
		/* The interrupt was not raised by Xena. */
		atomic_dec(&sp->isr_cnt);
		return IRQ_NONE;
	}

	/* If Intr is because of Tx Traffic */
	if (reason & GEN_INTR_TXTRAFFIC) {
		tx_intr_handler(sp);
	}

	/* If Intr is because of an error */
	if (reason & (GEN_ERROR_INTR))
		alarm_intr_handler(sp);

#ifdef CONFIG_S2IO_NAPI
	if (reason & GEN_INTR_RXTRAFFIC) {
		if (netif_rx_schedule_prep(dev)) {

#else
	/* If Intr is because of Rx Traffic */
	if (reason & GEN_INTR_RXTRAFFIC) {
		/*
		 * rx_traffic_int reg is an R1 register, writing all 1's
		 * will ensure that the actual interrupt causing bit get's
		 * cleared and hence a read can be avoided.
		 */
		val64 = 0xFFFFFFFFFFFFFFFFULL;
		writeq(val64, &bar0->rx_traffic_int);
		for (i = 0; i < config->rx_ring_num; i++) {
			rx_intr_handler(&mac_control->rings[i]);
		}
	}
#endif

	/* If Intr is because of Tx Traffic */
	if (reason & GEN_INTR_TXTRAFFIC) {
		/*
		 * tx_traffic_int reg is an R1 register, writing all 1's
		 * will ensure that the actual interrupt causing bit get's
		 * cleared and hence a read can be avoided.
		 */
		val64 = 0xFFFFFFFFFFFFFFFFULL;
		writeq(val64, &bar0->tx_traffic_int);

		for (i = 0; i < config->tx_fifo_num; i++)
			tx_intr_handler(&mac_control->fifos[i]);
	}

	if (reason & GEN_INTR_TXPIC)
		s2io_txpic_intr_handle(sp);
	/*
	 * If the Rx buffer count is below the panic threshold then
	 * reallocate the buffers from the interrupt handler itself,
	 * else schedule a tasklet to reallocate the buffers.
	 */
#ifndef CONFIG_S2IO_NAPI
	for (i = 0; i < config->rx_ring_num; i++) {
		int ret;
		int rxb_size = atomic_read(&sp->rx_bufs_left[i]);
		int level = rx_buffer_level(sp, rxb_size, i);


				DBG_PRINT(ERR_DBG, "%s:Out of memory",
					  dev->name);
				DBG_PRINT(ERR_DBG, " in ISR!!\n");
				clear_bit(0, (&sp->tasklet_status));
				atomic_dec(&sp->isr_cnt);
							     tasklet_status));
				return IRQ_HANDLED;
			}
			clear_bit(0, (&sp->tasklet_status));
		} else if (level == LOW) {
		} else if ((level == LOW)
			   && (!atomic_read(&sp->tasklet_status))) {
			tasklet_schedule(&sp->task);
		}

	}
#endif

	atomic_dec(&sp->isr_cnt);
	return IRQ_HANDLED;
}

/**
 * s2io_updt_stats -
 */
static void s2io_updt_stats(nic_t *sp)
{
	XENA_dev_config_t __iomem *bar0 = sp->bar0;
	u64 val64;
	int cnt = 0;

	if (atomic_read(&sp->card_state) == CARD_UP) {
		/* Apprx 30us on a 133 MHz bus */
		val64 = SET_UPDT_CLICKS(10) |
			STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
		writeq(val64, &bar0->stat_cfg);
		do {
			udelay(100);
			val64 = readq(&bar0->stat_cfg);
			if (!(val64 & BIT(0)))
				break;
			cnt++;
			if (cnt == 5)
				break; /* Updt failed */
		} while(1);
	}
}

/**
 *  s2io_get_stats - Updates the device statistics structure.
 *  @dev : pointer to the device structure.
 *  Description:
 *  This function updates the device statistics structure in the s2io_nic
 *  structure and returns a pointer to the same.
 *  Return value:
 *  pointer to the updated net_device_stats structure.

	mac_info_t *mac_control;
	struct config_param *config;


	mac_control = &sp->mac_control;
	config = &sp->config;

	/* Configure Stats for immediate updt */
	s2io_updt_stats(sp);

	sp->stats.tx_packets =
		le32_to_cpu(mac_control->stats_info->tmac_frms);
	sp->stats.tx_errors =
		le32_to_cpu(mac_control->stats_info->tmac_any_err_frms);
	sp->stats.rx_errors =
		le32_to_cpu(mac_control->stats_info->rmac_drop_frms);
	sp->stats.multicast =
		le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms);
	sp->stats.rx_length_errors =
		le32_to_cpu(mac_control->stats_info->rmac_long_frms);

	return (&sp->stats);
}

 *  s2io_set_multicast - entry point for multicast address enable/disable.
 *  @dev : pointer to the device structure
 *  Description:
 *  This function is a driver entry point which gets called by the kernel
 *  whenever multicast addresses must be enabled/disabled. This also gets
 *  called to set/reset promiscuous mode. Depending on the deivce flag, we
 *  determine, if multicast address must be enabled or if promiscuous mode
 *  is to be disabled etc.

	int i, j, prev_cnt;
	struct dev_mc_list *mclist;
	nic_t *sp = dev->priv;
	XENA_dev_config_t __iomem *bar0 = sp->bar0;
	u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
	    0xfeffffffffffULL;
	u64 dis_addr = 0xffffffffffffULL, mac_addr = 0;
	void __iomem *add;

	if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
		/*  Enable all Multicast addresses */

		/*  Disable all Multicast addresses */
		writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
		       &bar0->rmac_addr_data0_mem);
		writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
		       &bar0->rmac_addr_data1_mem);
		val64 = RMAC_ADDR_CMD_MEM_WE |
		    RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
		    RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);


	if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
		/*  Put the NIC into promiscuous mode */
		add = &bar0->mac_cfg;
		val64 = readq(&bar0->mac_cfg);
		val64 |= MAC_CFG_RMAC_PROM_ENABLE;



		val64 = readq(&bar0->mac_cfg);
		sp->promisc_flg = 1;
		DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
			  dev->name);
	} else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
		/*  Remove the NIC from promiscuous mode */
		add = &bar0->mac_cfg;
		val64 = readq(&bar0->mac_cfg);
		val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;



		val64 = readq(&bar0->mac_cfg);
		sp->promisc_flg = 0;
		DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n",
			  dev->name);
	}


		for (i = 0; i < prev_cnt; i++) {
			writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
			       &bar0->rmac_addr_data0_mem);
			writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
				&bar0->rmac_addr_data1_mem);
			val64 = RMAC_ADDR_CMD_MEM_WE |
			    RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
			    RMAC_ADDR_CMD_MEM_OFFSET

				mac_addr |= mclist->dmi_addr[j];
				mac_addr <<= 8;
			}
			mac_addr >>= 8;
			writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
			       &bar0->rmac_addr_data0_mem);
			writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
				&bar0->rmac_addr_data1_mem);
			val64 = RMAC_ADDR_CMD_MEM_WE |
			    RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
			    RMAC_ADDR_CMD_MEM_OFFSET

}

/**
 *  s2io_set_mac_addr - Programs the Xframe mac address
 *  @dev : pointer to the device structure.
 *  @addr: a uchar pointer to the new mac address which is to be set.
 *  Description : This procedure will program the Xframe to receive
 *  frames with new Mac Address
 *  Return value: SUCCESS on success and an appropriate (-)ve integer
 *  as defined in errno.h file on failure.
 */

int s2io_set_mac_addr(struct net_device *dev, u8 * addr)
{
	nic_t *sp = dev->priv;
	XENA_dev_config_t __iomem *bar0 = sp->bar0;
	register u64 val64, mac_addr = 0;
	int i;

	/*
	 * Set the new MAC address as the new unicast filter and reflect this
	 * change on the device address registered with the OS. It will be
	 * at offset 0.
	 */
	for (i = 0; i < ETH_ALEN; i++) {
		mac_addr <<= 8;

}

/**
 * s2io_ethtool_sset - Sets different link parameters.
 * @sp : private member of the device structure, which is a pointer to the  * s2io_nic structure.
 * @info: pointer to the structure with parameters given by ethtool to set
 * link information.
 * Description:
 * The function sets different link parameters provided by the user onto
 * the NIC.
 * Return value:
 * 0 on success.

}

/**
 * s2io_ethtol_gset - Return link specific information.
 * @sp : private member of the device structure, pointer to the
 *      s2io_nic structure.
 * @info : pointer to the structure with parameters given by ethtool
 * to return link information.
 * Description:
 * Returns link specific information like speed, duplex etc.. to ethtool.
 * Return value :
 * return 0 on success.
 */

static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
{
	nic_t *sp = dev->priv;
	info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);

}

/**
 * s2io_ethtool_gdrvinfo - Returns driver specific information.
 * @sp : private member of the device structure, which is a pointer to the
 * s2io_nic structure.
 * @info : pointer to the structure with parameters given by ethtool to
 * return driver information.

	strncpy(info->version, s2io_driver_version,
		sizeof(s2io_driver_version));
	strncpy(info->fw_version, "", 32);
	strncpy(info->bus_info, pci_name(sp->pdev), 32);
	info->regdump_len = XENA_REG_SPACE;
	info->eedump_len = XENA_EEPROM_SPACE;
	info->testinfo_len = S2IO_TEST_LEN;

}

/**
 *  s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
 *  @sp: private member of the device structure, which is a pointer to the
 *  s2io_nic structure.
 *  @regs : pointer to the structure with parameters given by ethtool for
 *  dumping the registers.
 *  @reg_space: The input argumnet into which all the registers are dumped.
 *  Description:

	regs->version = sp->pdev->subsystem_device;

	for (i = 0; i < regs->len; i += 8) {
		reg = readq(sp->bar0 + i);
		memcpy((reg_space + i), &reg, 8);
	}
}

/**
 *  s2io_phy_id  - timer function that alternates adapter LED.
 *  @data : address of the private member of the device structure, which
 *  is a pointer to the s2io_nic structure, provided as an u32.
 * Description: This is actually the timer function that alternates the
 * adapter LED bit of the adapter control bit to set/reset every time on
 * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
 *  once every second.
*/
static void s2io_phy_id(unsigned long data)
{
	nic_t *sp = (nic_t *) data;
	XENA_dev_config_t __iomem *bar0 = sp->bar0;
	u64 val64 = 0;
	u16 subid;

	subid = sp->pdev->subsystem_device;
	if ((sp->device_type == XFRAME_II_DEVICE) ||
		   ((subid & 0xFF) >= 0x07)) {
		val64 = readq(&bar0->gpio_control);
		val64 ^= GPIO_CTRL_GPIO_0;
		writeq(val64, &bar0->gpio_control);

}

/**
 * s2io_ethtool_idnic - To physically identify the nic on the system.
 * @sp : private member of the device structure, which is a pointer to the
 * s2io_nic structure.
 * @id : pointer to the structure with identification parameters given by
 * ethtool.
 * Description: Used to physically identify the NIC on the system.
 * The Link LED will blink for a time specified by the user for
 * identification.
 * NOTE: The Link has to be Up to be able to blink the LED. Hence
 * identification is possible only if it's link is up.
 * Return value:
 * int , returns 0 on success

{
	u64 val64 = 0, last_gpio_ctrl_val;
	nic_t *sp = dev->priv;
	XENA_dev_config_t __iomem *bar0 = sp->bar0;
	u16 subid;

	subid = sp->pdev->subsystem_device;
	last_gpio_ctrl_val = readq(&bar0->gpio_control);
	if ((sp->device_type == XFRAME_I_DEVICE) &&
		((subid & 0xFF) < 0x07)) {
		val64 = readq(&bar0->adapter_control);
		if (!(val64 & ADAPTER_CNTL_EN)) {
			printk(KERN_ERR

		sp->id_timer.data = (unsigned long) sp;
	}
	mod_timer(&sp->id_timer, jiffies);
	set_current_state(TASK_INTERRUPTIBLE);
	if (data)
		msleep_interruptible(data * HZ);
	else
		msleep_interruptible(MAX_FLICKER_TIME);
	del_timer_sync(&sp->id_timer);

	if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
		writeq(last_gpio_ctrl_val, &bar0->gpio_control);
		last_gpio_ctrl_val = readq(&bar0->gpio_control);
	}


/**
 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
 * @sp : private member of the device structure, which is a pointer to the
 *	s2io_nic structure.
 * @ep : pointer to the structure with pause parameters given by ethtool.
 * Description:
 * Returns the Pause frame generation and reception capability of the NIC.

{
	u64 val64;
	nic_t *sp = dev->priv;
	XENA_dev_config_t __iomem *bar0 = sp->bar0;

	val64 = readq(&bar0->rmac_pause_cfg);
	if (val64 & RMAC_PAUSE_GEN_ENABLE)

}

/**
 * s2io_ethtool_setpause_data -  set/reset pause frame generation.
 * @sp : private member of the device structure, which is a pointer to the
 *      s2io_nic structure.
 * @ep : pointer to the structure with pause parameters given by ethtool.
 * Description:

 * int, returns 0 on Success
 */

static int s2io_ethtool_setpause_data(struct net_device *dev,
			       struct ethtool_pauseparam *ep)
{
	u64 val64;
	nic_t *sp = dev->priv;
	XENA_dev_config_t __iomem *bar0 = sp->bar0;

	val64 = readq(&bar0->rmac_pause_cfg);
	if (ep->tx_pause)


/**
 * read_eeprom - reads 4 bytes of data from user given offset.
 * @sp : private member of the device structure, which is a pointer to the
 *      s2io_nic structure.
 * @off : offset at which the data must be written
 * @data : Its an output parameter where the data read at the given
 *	offset is stored.
 * Description:
 * Will read 4 bytes of data from the user given offset and return the
 * read data.
 * NOTE: Will allow to read only part of the EEPROM visible through the
 *   I2C bus.

	int ret = -1;
	u32 exit_cnt = 0;
	u64 val64;
	XENA_dev_config_t __iomem *bar0 = sp->bar0;

	val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
	    I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ |

			ret = 0;
			break;
		}
		msleep(50);
		schedule_timeout(HZ / 20);
		exit_cnt++;
	}


 *       s2io_nic structure.
 *  @off : offset at which the data must be written
 *  @data : The data that is to be written
 *  @cnt : Number of bytes of the data that are actually to be written into
 *  the Eeprom. (max of 3)
 * Description:
 *  Actually writes the relevant part of the data value into the Eeprom

{
	int exit_cnt = 0, ret = -1;
	u64 val64;
	XENA_dev_config_t __iomem *bar0 = sp->bar0;

	val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
	    I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA(data) |

				ret = 0;
			break;
		}
		msleep(50);
		schedule_timeout(HZ / 20);
		exit_cnt++;
	}


/**
 *  s2io_ethtool_geeprom  - reads the value stored in the Eeprom.
 *  @sp : private member of the device structure, which is a pointer to the *       s2io_nic structure.
 *  @eeprom : pointer to the user level structure provided by ethtool,
 *  containing all relevant information.
 *  @data_buf : user defined value to be written into Eeprom.
 *  Description: Reads the values stored in the Eeprom at given offset

 *  int  0 on success
 */

static int s2io_ethtool_geeprom(struct net_device *dev,
			 struct ethtool_eeprom *eeprom, u8 * data_buf)
{
	u32 data, i, valid;

 *  s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
 *  @sp : private member of the device structure, which is a pointer to the
 *  s2io_nic structure.
 *  @eeprom : pointer to the user level structure provided by ethtool,
 *  containing all relevant information.
 *  @data_buf ; user defined value to be written into Eeprom.
 *  Description:

}

/**
 * s2io_register_test - reads and writes into all clock domains.
 * @sp : private member of the device structure, which is a pointer to the
 * s2io_nic structure.
 * @data : variable that returns the result of each of the test conducted b
 * by the driver.


static int s2io_register_test(nic_t * sp, uint64_t * data)
{
	XENA_dev_config_t __iomem *bar0 = sp->bar0;
	u64 val64 = 0;
	int fail = 0;

	val64 = readq(&bar0->pif_rd_swapper_fb);
	if (val64 != 0x123456789abcdefULL) {
		fail = 1;
		DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n");
	}

}

/**
 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
 * @sp : private member of the device structure, which is a pointer to the
 * s2io_nic structure.
 * @data:variable that returns the result of each of the test conducted by
 * the driver.
 * Description:
 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
 * register.
 * Return value:
 * 0 on success.


/**
 * s2io_bist_test - invokes the MemBist test of the card .
 * @sp : private member of the device structure, which is a pointer to the
 * s2io_nic structure.
 * @data:variable that returns the result of each of the test conducted by
 * the driver.
 * Description:
 * This invokes the MemBist test of the card. We give around
 * 2 secs time for the Test to complete. If it's still not complete
 * within this peiod, we consider that the test failed.
 * Return value:
 * 0 on success and -1 on failure.
 */

			ret = 0;
			break;
		}
		msleep(100);
		schedule_timeout(HZ / 10);
		cnt++;
	}


}

/**
 * s2io-link_test - verifies the link state of the nic
 * @sp ; private member of the device structure, which is a pointer to the
 * s2io_nic structure.
 * @data: variable that returns the result of each of the test conducted by
 * the driver.
 * Description:
 * The function verifies the link state of the NIC and updates the input
 * argument 'data' appropriately.
 * Return value:
 * 0 on success.


static int s2io_link_test(nic_t * sp, uint64_t * data)
{
	XENA_dev_config_t __iomem *bar0 = sp->bar0;
	u64 val64;

	val64 = readq(&bar0->adapter_status);

}

/**
 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
 * @sp - private member of the device structure, which is a pointer to the
 * s2io_nic structure.
 * @data - variable that returns the result of each of the test
 * conducted by the driver.
 * Description:
 *  This is one of the offline test that tests the read and write
 *  access to the RldRam chip on the NIC.
 * Return value:
 *  0 on success.


static int s2io_rldram_test(nic_t * sp, uint64_t * data)
{
	XENA_dev_config_t __iomem *bar0 = sp->bar0;
	u64 val64;
	int cnt, iteration = 0, test_pass = 0;


			val64 = readq(&bar0->mc_rldram_test_ctrl);
			if (val64 & MC_RLDRAM_TEST_DONE)
				break;
			msleep(200);
			schedule_timeout(HZ / 5);
		}

		if (cnt == 5)

			val64 = readq(&bar0->mc_rldram_test_ctrl);
			if (val64 & MC_RLDRAM_TEST_DONE)
				break;
			msleep(500);
			schedule_timeout(HZ / 2);
		}

		if (cnt == 5)

 *  s2io_nic structure.
 *  @ethtest : pointer to a ethtool command specific structure that will be
 *  returned to the user.
 *  @data : variable that returns the result of each of the test
 * conducted by the driver.
 * Description:
 *  This function conducts 6 tests ( 4 offline and 2 online) to determine


	if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
		/* Offline Tests. */
		if (orig_state)
			s2io_close(sp->dev);
			s2io_set_swapper(sp);
		} else
			s2io_set_swapper(sp);

		if (s2io_register_test(sp, &data[0]))
			ethtest->flags |= ETH_TEST_FL_FAILED;

		s2io_reset(sp);
		s2io_set_swapper(sp);

		if (s2io_rldram_test(sp, &data[3]))
			ethtest->flags |= ETH_TEST_FL_FAILED;

		s2io_reset(sp);
		s2io_set_swapper(sp);

		if (s2io_eeprom_test(sp, &data[1]))
			ethtest->flags |= ETH_TEST_FL_FAILED;

	nic_t *sp = dev->priv;
	StatInfo_t *stat_info = sp->mac_control.stats_info;

	s2io_updt_stats(sp);
	tmp_stats[i++] =
		(u64)le32_to_cpu(stat_info->tmac_frms_oflow) << 32  |
		le32_to_cpu(stat_info->tmac_frms);
	tmp_stats[i++] =
		(u64)le32_to_cpu(stat_info->tmac_data_octets_oflow) << 32 |
		le32_to_cpu(stat_info->tmac_data_octets);
	tmp_stats[i++] = le64_to_cpu(stat_info->tmac_drop_frms);
	tmp_stats[i++] =
		(u64)le32_to_cpu(stat_info->tmac_mcst_frms_oflow) << 32 |
		le32_to_cpu(stat_info->tmac_mcst_frms);
	tmp_stats[i++] =
		(u64)le32_to_cpu(stat_info->tmac_bcst_frms_oflow) << 32 |
		le32_to_cpu(stat_info->tmac_bcst_frms);
	tmp_stats[i++] = le64_to_cpu(stat_info->tmac_pause_ctrl_frms);
	tmp_stats[i++] =
		(u64)le32_to_cpu(stat_info->tmac_any_err_frms_oflow) << 32 |
		le32_to_cpu(stat_info->tmac_any_err_frms);
	tmp_stats[i++] = le64_to_cpu(stat_info->tmac_vld_ip_octets);
	tmp_stats[i++] =
		(u64)le32_to_cpu(stat_info->tmac_vld_ip_oflow) << 32 |
		le32_to_cpu(stat_info->tmac_vld_ip);
	tmp_stats[i++] =
		(u64)le32_to_cpu(stat_info->tmac_drop_ip_oflow) << 32 |
		le32_to_cpu(stat_info->tmac_drop_ip);
	tmp_stats[i++] =
		(u64)le32_to_cpu(stat_info->tmac_icmp_oflow) << 32 |
		le32_to_cpu(stat_info->tmac_icmp);
	tmp_stats[i++] =
		(u64)le32_to_cpu(stat_info->tmac_rst_tcp_oflow) << 32 |
		le32_to_cpu(stat_info->tmac_rst_tcp);
	tmp_stats[i++] = le64_to_cpu(stat_info->tmac_tcp);
	tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_udp_oflow) << 32 |
		le32_to_cpu(stat_info->tmac_udp);
	tmp_stats[i++] =
		(u64)le32_to_cpu(stat_info->rmac_vld_frms_oflow) << 32 |
		le32_to_cpu(stat_info->rmac_vld_frms);
	tmp_stats[i++] =
		(u64)le32_to_cpu(stat_info->rmac_data_octets_oflow) << 32 |
		le32_to_cpu(stat_info->rmac_data_octets);
	tmp_stats[i++] = le64_to_cpu(stat_info->rmac_fcs_err_frms);
	tmp_stats[i++] = le64_to_cpu(stat_info->rmac_drop_frms);
	tmp_stats[i++] =
		(u64)le32_to_cpu(stat_info->rmac_vld_mcst_frms_oflow) << 32 |
		le32_to_cpu(stat_info->rmac_vld_mcst_frms);
	tmp_stats[i++] =
		(u64)le32_to_cpu(stat_info->rmac_vld_bcst_frms_oflow) << 32 |
		le32_to_cpu(stat_info->rmac_vld_bcst_frms);
	tmp_stats[i++] = le32_to_cpu(stat_info->rmac_in_rng_len_err_frms);
	tmp_stats[i++] = le64_to_cpu(stat_info->rmac_long_frms);
	tmp_stats[i++] = le64_to_cpu(stat_info->rmac_pause_ctrl_frms);
	tmp_stats[i++] =
		(u64)le32_to_cpu(stat_info->rmac_discarded_frms_oflow) << 32 |
		le32_to_cpu(stat_info->rmac_discarded_frms);
	tmp_stats[i++] =
		(u64)le32_to_cpu(stat_info->rmac_usized_frms_oflow) << 32 |
		le32_to_cpu(stat_info->rmac_usized_frms);
	tmp_stats[i++] =
		(u64)le32_to_cpu(stat_info->rmac_osized_frms_oflow) << 32 |
		le32_to_cpu(stat_info->rmac_osized_frms);
	tmp_stats[i++] =
		(u64)le32_to_cpu(stat_info->rmac_frag_frms_oflow) << 32 |
		le32_to_cpu(stat_info->rmac_frag_frms);
	tmp_stats[i++] =
		(u64)le32_to_cpu(stat_info->rmac_jabber_frms_oflow) << 32 |
		le32_to_cpu(stat_info->rmac_jabber_frms);
	tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_ip_oflow) << 32 |
		le32_to_cpu(stat_info->rmac_ip);
	tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ip_octets);
	tmp_stats[i++] = le32_to_cpu(stat_info->rmac_hdr_err_ip);
	tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_drop_ip_oflow) << 32 |
		le32_to_cpu(stat_info->rmac_drop_ip);
	tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_icmp_oflow) << 32 |
		le32_to_cpu(stat_info->rmac_icmp);
	tmp_stats[i++] = le64_to_cpu(stat_info->rmac_tcp);
	tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_udp_oflow) << 32 |
		le32_to_cpu(stat_info->rmac_udp);
	tmp_stats[i++] =
		(u64)le32_to_cpu(stat_info->rmac_err_drp_udp_oflow) << 32 |
		le32_to_cpu(stat_info->rmac_err_drp_udp);
	tmp_stats[i++] =
		(u64)le32_to_cpu(stat_info->rmac_pause_cnt_oflow) << 32 |
		le32_to_cpu(stat_info->rmac_pause_cnt);
	tmp_stats[i++] =
		(u64)le32_to_cpu(stat_info->rmac_accepted_ip_oflow) << 32 |
		le32_to_cpu(stat_info->rmac_accepted_ip);
	tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_tcp);
	tmp_stats[i++] = 0;
	tmp_stats[i++] = stat_info->sw_stat.single_ecc_errs;
	tmp_stats[i++] = stat_info->sw_stat.double_ecc_errs;
}

int s2io_ethtool_get_regs_len(struct net_device *dev)

};

/**
 *  s2io_ioctl - Entry point for the Ioctl
 *  @dev :  Device pointer.
 *  @ifr :  An IOCTL specefic structure, that can contain a pointer to
 *  a proprietary structure used to pass information to the driver.
 *  @cmd :  This is used to distinguish between the different commands that
 *  can be passed to the IOCTL functions.
 *  Description:
 *  Currently there are no special functionality supported in IOCTL, hence
 *  function always return EOPNOTSUPPORTED
 *  Return value:
 *  Currently the IOCTL supports no operations, hence by default this
 *  function returns OP NOT SUPPORTED value.
 */

int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)

int s2io_change_mtu(struct net_device *dev, int new_mtu)
{
	nic_t *sp = dev->priv;
	XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
	register u64 val64;

	if (netif_running(dev)) {
		DBG_PRINT(ERR_DBG, "%s: Must be stopped to ", dev->name);
		DBG_PRINT(ERR_DBG, "change its MTU \n");
		return -EBUSY;
	}

	if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
		DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n",

		return -EPERM;
	}

	/* Set the new MTU into the PYLD register of the NIC */
	val64 = new_mtu;
	writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);

	dev->mtu = new_mtu;
	if (netif_running(dev)) {
		s2io_card_down(sp);
		netif_stop_queue(dev);
		if (s2io_card_up(sp)) {
			DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
				  __FUNCTION__);
		}
		if (netif_queue_stopped(dev))
			netif_wake_queue(dev);
	} else { /* Device is down */
		XENA_dev_config_t __iomem *bar0 = sp->bar0;
		u64 val64 = new_mtu;

		writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
	}

	return 0;
}

 *  @dev_adr : address of the device structure in dma_addr_t format.
 *  Description:
 *  This is the tasklet or the bottom half of the ISR. This is
 *  an extension of the ISR which is scheduled by the scheduler to be run
 *  when the load on the CPU is low. All low priority tasks of the ISR can
 *  be pushed into the tasklet. For now the tasklet is used only to
 *  replenish the Rx buffers in the Rx buffer descriptors.
 *  Return value:
 *  void.

	config = &sp->config;

	if (!TASKLET_IN_USE) {
		for (i = 0; i < config->rx_ring_num; i++) {
			ret = fill_rx_buffers(sp, i);
			if (ret == -ENOMEM) {
				DBG_PRINT(ERR_DBG, "%s: Out of ",

				break;
			}
		}
		clear_bit(0, (&sp->tasklet_status));
	}
}


{
	nic_t *nic = (nic_t *) data;
	struct net_device *dev = nic->dev;
	XENA_dev_config_t __iomem *bar0 = nic->bar0;
	register u64 val64;
	u16 subid;

	if (test_and_set_bit(0, &(nic->link_state))) {
		/* The card is being reset, no point doing anything */
		return;
	}

	subid = nic->pdev->subsystem_device;
	if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
		/*
		 * Allow a small delay for the NICs self initiated
		 * cleanup to complete.
		 */
		msleep(100);
	}

	val64 = readq(&bar0->adapter_status);
	if (verify_xena_quiescence(nic, val64, nic->device_enabled_once)) {
		if (LINK_IS_UP(val64)) {
			val64 = readq(&bar0->adapter_control);
			val64 |= ADAPTER_CNTL_EN;
			writeq(val64, &bar0->adapter_control);
			if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
							     subid)) {
				val64 = readq(&bar0->gpio_control);
				val64 |= GPIO_CTRL_GPIO_0;
				writeq(val64, &bar0->gpio_control);

				val64 |= ADAPTER_LED_ON;
				writeq(val64, &bar0->adapter_control);
			}
			if (s2io_link_fault_indication(nic) ==
						MAC_RMAC_ERR_TIMER) {
				val64 = readq(&bar0->adapter_status);
				if (!LINK_IS_UP(val64)) {
					DBG_PRINT(ERR_DBG, "%s:", dev->name);
					DBG_PRINT(ERR_DBG, " Link down");
					DBG_PRINT(ERR_DBG, "after ");
					DBG_PRINT(ERR_DBG, "enabling ");
					DBG_PRINT(ERR_DBG, "device \n");
				}
			}
			if (nic->device_enabled_once == FALSE) {
				nic->device_enabled_once = TRUE;
			}
			s2io_link(nic, LINK_UP);
		} else {
			if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
							      subid)) {
				val64 = readq(&bar0->gpio_control);
				val64 &= ~GPIO_CTRL_GPIO_0;
				writeq(val64, &bar0->gpio_control);

		DBG_PRINT(ERR_DBG, "device is not Quiescent\n");
		netif_stop_queue(dev);
	}
	clear_bit(0, &(nic->link_state));
}

static void s2io_card_down(nic_t * sp)
{
	int cnt = 0;
	XENA_dev_config_t __iomem *bar0 = sp->bar0;
	unsigned long flags;
	register u64 val64 = 0;

	del_timer_sync(&sp->alarm_timer);
	/* If s2io_set_link task is executing, wait till it completes. */
	while (test_and_set_bit(0, &(sp->link_state))) {
		msleep(50);
	}
	atomic_set(&sp->card_state, CARD_DOWN);

	/* disable Tx and Rx traffic on the NIC */
	stop_nic(sp);

	/* Kill tasklet. */
	tasklet_kill(&sp->task);

	/* Check if the device is Quiescent and then Reset the NIC */
	do {
		val64 = readq(&bar0->adapter_status);
		if (verify_xena_quiescence(sp, val64, sp->device_enabled_once)) {
			break;
		}

		msleep(50);
		cnt++;
		if (cnt == 10) {
			DBG_PRINT(ERR_DBG,
				  "s2io_close:Device not Quiescent ");
			DBG_PRINT(ERR_DBG, "adaper status reads 0x%llx\n",
				  (unsigned long long) val64);
			break;
		}
	} while (1);
	s2io_reset(sp);

	/* Waiting till all Interrupt handlers are complete */
	cnt = 0;
	do {
		msleep(10);
		if (!atomic_read(&sp->isr_cnt))
			break;
		cnt++;
	} while(cnt < 5);

	spin_lock_irqsave(&sp->tx_lock, flags);
	/* Free all Tx buffers */
	free_tx_buffers(sp);
	spin_unlock_irqrestore(&sp->tx_lock, flags);

	/* Free all Rx buffers */
	spin_lock_irqsave(&sp->rx_lock, flags);
	free_rx_buffers(sp);
	spin_unlock_irqrestore(&sp->rx_lock, flags);

	clear_bit(0, &(sp->link_state));
}

static int s2io_card_up(nic_t * sp)
{
	int i, ret;
	mac_info_t *mac_control;
	struct config_param *config;
	struct net_device *dev = (struct net_device *) sp->dev;

	/* Initialize the H/W I/O registers */
	if (init_nic(sp) != 0) {
		DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
			  dev->name);
		return -ENODEV;
	}

	/*
	 * Initializing the Rx buffers. For now we are considering only 1
	 * Rx ring and initializing buffers into 30 Rx blocks
	 */
	mac_control = &sp->mac_control;
	config = &sp->config;

	for (i = 0; i < config->rx_ring_num; i++) {
		if ((ret = fill_rx_buffers(sp, i))) {
			DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
				  dev->name);
			s2io_reset(sp);
			free_rx_buffers(sp);
			return -ENOMEM;
		}
		DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
			  atomic_read(&sp->rx_bufs_left[i]));
	}

	/* Setting its receive mode */
	s2io_set_multicast(dev);

	/* Enable tasklet for the device */
	tasklet_init(&sp->task, s2io_tasklet, (unsigned long) dev);

	/* Enable Rx Traffic and interrupts on the NIC */
	if (start_nic(sp)) {
		DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
		tasklet_kill(&sp->task);
		s2io_reset(sp);
		free_irq(dev->irq, dev);
		free_rx_buffers(sp);
		return -ENODEV;
	}

	S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));

	atomic_set(&sp->card_state, CARD_UP);
	return 0;
}

/**
 * s2io_restart_nic - Resets the NIC.
 * @data : long pointer to the device private structure
 * Description:
 * This function is scheduled to be run by the s2io_tx_watchdog
 * function after 0.5 secs to reset the NIC. The idea is to reduce
 * the run time of the watch dog routine which is run holding a
 * spin lock.
 */

	struct net_device *dev = (struct net_device *) data;
	nic_t *sp = dev->priv;

	s2io_card_down(sp);
	if (s2io_card_up(sp)) {
		DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
			  dev->name);
	}
	netif_wake_queue(dev);
	DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n",
		  dev->name);

}

/**
 *  s2io_tx_watchdog - Watchdog for transmit side.
 *  @dev : Pointer to net device structure
 *  Description:
 *  This function is triggered if the Tx Queue is stopped

 *   @len : length of the packet
 *   @cksum : FCS checksum of the frame.
 *   @ring_no : the ring from which this RxD was extracted.
 *   Description:
 *   This function is called by the Tx interrupt serivce routine to perform
 *   some OS related operations on the SKB before passing it to the upper
 *   layers. It mainly checks if the checksum is OK, if so adds it to the

 *   Return value:
 *   SUCCESS on success and -1 on failure.
 */
static int rx_osm_handler(ring_info_t *ring_data, RxD_t * rxdp)
static int rx_osm_handler(nic_t * sp, u16 len, RxD_t * rxdp, int ring_no)
#else
static int rx_osm_handler(nic_t * sp, RxD_t * rxdp, int ring_no,
			  buffAdd_t * ba)
#endif
{
	nic_t *sp = ring_data->nic;
	struct net_device *dev = (struct net_device *) sp->dev;
	struct sk_buff *skb = (struct sk_buff *)
		((unsigned long) rxdp->Host_Control);
	int ring_no = ring_data->ring_no;
	u16 l3_csum, l4_csum;
#ifdef CONFIG_2BUFF_MODE
	int buf0_len = RXD_GET_BUFFER0_SIZE(rxdp->Control_2);
	int buf2_len = RXD_GET_BUFFER2_SIZE(rxdp->Control_2);
	int get_block = ring_data->rx_curr_get_info.block_index;
	int get_off = ring_data->rx_curr_get_info.offset;
	buffAdd_t *ba = &ring_data->ba[get_block][get_off];
	unsigned char *buff;
#else
	u16 len = (u16) ((RXD_GET_BUFFER0_SIZE(rxdp->Control_2)) >> 48);;
#endif
	skb->dev = dev;
	if (rxdp->Control_1 & RXD_T_CODE) {
		unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
		DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%llx\n",
			  dev->name, err);
		dev_kfree_skb(skb);
		sp->stats.rx_crc_errors++;
		atomic_dec(&sp->rx_bufs_left[ring_no]);
		rxdp->Host_Control = 0;
		return 0;
	}

	/* Updating statistics */
	rxdp->Host_Control = 0;
	sp->rx_pkt_count++;
	sp->stats.rx_packets++;
#ifndef CONFIG_2BUFF_MODE
	sp->stats.rx_bytes += len;
#else
	sp->stats.rx_bytes += buf0_len + buf2_len;
#endif

#ifndef CONFIG_2BUFF_MODE
	skb_put(skb, len);
#else
	buff = skb_push(skb, buf0_len);
	memcpy(buff, ba->ba_0, buf0_len);
	skb_put(skb, buf2_len);
#endif

	if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) &&
	    (sp->rx_csum)) {
		l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
		l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
		if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
			/*
			 * NIC verifies if the Checksum of the received
			 * frame is Ok or not and accordingly returns
			 * a flag in the RxD.
			 */
			skb->ip_summed = CHECKSUM_UNNECESSARY;
		} else {
			/*
			 * Packet with erroneous checksum, let the
			 * upper layers deal with it.
			 */
			skb->ip_summed = CHECKSUM_NONE;

		skb->ip_summed = CHECKSUM_NONE;
	}

	if (rxdp->Control_1 & RXD_T_CODE) {
		unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
		DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%llx\n",
			  dev->name, err);
	}
#ifdef CONFIG_2BUFF_MODE
	buf0_len = RXD_GET_BUFFER0_SIZE(rxdp->Control_2);
	buf2_len = RXD_GET_BUFFER2_SIZE(rxdp->Control_2);
#endif

	skb->dev = dev;
#ifndef CONFIG_2BUFF_MODE
	skb_put(skb, len);
	skb->protocol = eth_type_trans(skb, dev);
#else
	skb_put(skb, buf2_len);
	/* 
	 * Reproducing eth_type_trans functionality and running
	 * on the ethernet header 'eth' stripped and given to us
	 * by the hardware in 2Buff mode.
	 */
	if (*eth->h_dest & 1) {
		if (!memcmp(eth->h_dest, dev->broadcast, ETH_ALEN))
			skb->pkt_type = PACKET_BROADCAST;
		else
			skb->pkt_type = PACKET_MULTICAST;
	} else if (memcmp(eth->h_dest, dev->dev_addr, ETH_ALEN)) {
		skb->pkt_type = PACKET_OTHERHOST;
	}
	skb->protocol = eth->h_proto;
#endif

#ifdef CONFIG_S2IO_NAPI
	if (sp->vlgrp && RXD_GET_VLAN_TAG(rxdp->Control_2)) {
		/* Queueing the vlan frame to the upper layer */
		vlan_hwaccel_receive_skb(skb, sp->vlgrp,
			RXD_GET_VLAN_TAG(rxdp->Control_2));
	} else {
		netif_receive_skb(skb);
	}
#else
	if (sp->vlgrp && RXD_GET_VLAN_TAG(rxdp->Control_2)) {
		/* Queueing the vlan frame to the upper layer */
		vlan_hwaccel_rx(skb, sp->vlgrp,
			RXD_GET_VLAN_TAG(rxdp->Control_2));
	} else {
		netif_rx(skb);
	}
#endif

	dev->last_rx = jiffies;
	sp->rx_pkt_count++;
	sp->stats.rx_packets++;
#ifndef CONFIG_2BUFF_MODE
	sp->stats.rx_bytes += len;
#else
	sp->stats.rx_bytes += buf0_len + buf2_len;
#endif

	atomic_dec(&sp->rx_bufs_left[ring_no]);
	rxdp->Host_Control = 0;
	return SUCCESS;
}

int check_for_tx_space(nic_t * sp)
{
	u32 put_off, get_off, queue_len;
	int ret = TRUE, i;

	for (i = 0; i < sp->config.TxFIFONum; i++) {
		queue_len = sp->mac_control.tx_curr_put_info[i].fifo_len
		    + 1;
		put_off = sp->mac_control.tx_curr_put_info[i].offset;
		get_off = sp->mac_control.tx_curr_get_info[i].offset;
		if (((put_off + 1) % queue_len) == get_off) {
			ret = FALSE;
			break;
		}
	}

	return ret;
}

/**
 *  s2io_link - stops/starts the Tx queue.
 *  @sp : private member of the device structure, which is a pointer to the

 *  @link : inidicates whether link is UP/DOWN.
 *  Description:
 *  This function stops/starts the Tx queue depending on whether the link
 *  status of the NIC is is down or up. This is called by the Alarm
 *  interrupt handler whenever a link change interrupt comes up.
 *  Return value:
 *  void.
 */

}

/**
 *  get_xena_rev_id - to identify revision ID of xena.
 *  @pdev : PCI Dev structure
 *  Description:
 *  Function to identify the Revision ID of xena.

}

/**
 *  s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
 *  @sp : private member of the device structure, which is a pointer to the
 *  s2io_nic structure.
 *  Description:
 *  This function initializes a few of the PCI and PCI-X configuration registers


static void s2io_init_pci(nic_t * sp)
{
	u16 pci_cmd = 0, pcix_cmd = 0;

	/* Enable Data Parity Error Recovery in PCI-X command register. */
	pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
			     &(pcix_cmd));
	pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
			      (pcix_cmd | 1));
	pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
			     &(pcix_cmd));

	/* Set the PErr Response bit in PCI command register. */
	pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);

			      (pci_cmd | PCI_COMMAND_PARITY));
	pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);

	/* Set user specified value in Latency Timer */
	if (latency_timer) {
		pci_write_config_byte(sp->pdev, PCI_LATENCY_TIMER,
				      latency_timer);
		pci_read_config_byte(sp->pdev, PCI_LATENCY_TIMER,
				     &latency_timer);
	}

	/* Set MMRB count to 4096 in PCI-X Command register. */
	sp->pcix_cmd &= 0xFFF3;
	pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
			      (sp->pcix_cmd | (max_read_byte_cnt << 2)));
	pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
			     &(sp->pcix_cmd));

	/*  Setting Maximum outstanding splits based on system type. */
	sp->pcix_cmd &= 0xFF8F;

	sp->pcix_cmd |= XENA_MAX_OUTSTANDING_SPLITS(max_splits_trans);
	pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
			      sp->pcix_cmd);
	pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
			     &(sp->pcix_cmd));
	/* Forcibly disabling relaxed ordering capability of the card. */
	pcix_cmd &= 0xfffd;
	pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
			      pcix_cmd);
	pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
			     &(pcix_cmd));
}

MODULE_AUTHOR("Raghavendra Koushik <raghavendra.koushik@neterion.com>");
MODULE_LICENSE("GPL");
module_param(tx_fifo_num, int, 0);
module_param(rx_ring_num, int, 0);
module_param_array(tx_fifo_len, int, tx_fifo_num, 0);
module_param_array(rx_ring_sz, int, rx_ring_num, 0);
module_param_array(rts_frm_len, int, rx_ring_num, 0);
module_param(use_continuous_tx_intrs, int, 1);
module_param(rmac_pause_time, int, 0);
module_param(mc_pause_threshold_q0q3, int, 0);
module_param(mc_pause_threshold_q4q7, int, 0);
module_param(shared_splits, int, 0);
module_param(tmac_util_period, int, 0);
module_param(rmac_util_period, int, 0);
module_param(bimodal, bool, 0);
#ifndef CONFIG_S2IO_NAPI
module_param(indicate_max_pkts, int, 0);
#endif
module_param(rxsync_frequency, int, 0);

MODULE_PARM(TxFIFOLen_0, "i");
MODULE_PARM(TxFIFOLen_1, "i");
MODULE_PARM(TxFIFOLen_2, "i");
MODULE_PARM(TxFIFOLen_3, "i");
MODULE_PARM(TxFIFOLen_4, "i");
MODULE_PARM(TxFIFOLen_5, "i");
MODULE_PARM(TxFIFOLen_6, "i");
MODULE_PARM(TxFIFOLen_7, "i");
MODULE_PARM(MaxTxDs, "i");
MODULE_PARM(RxRingNum, "i");
MODULE_PARM(RxRingSz_0, "i");
MODULE_PARM(RxRingSz_1, "i");
MODULE_PARM(RxRingSz_2, "i");
MODULE_PARM(RxRingSz_3, "i");
MODULE_PARM(RxRingSz_4, "i");
MODULE_PARM(RxRingSz_5, "i");
MODULE_PARM(RxRingSz_6, "i");
MODULE_PARM(RxRingSz_7, "i");
MODULE_PARM(Stats_refresh_time, "i");
MODULE_PARM(rmac_pause_time, "i");
MODULE_PARM(mc_pause_threshold_q0q3, "i");
MODULE_PARM(mc_pause_threshold_q4q7, "i");
MODULE_PARM(shared_splits, "i");
MODULE_PARM(max_splits_trans, "i");
MODULE_PARM(tmac_util_period, "i");
MODULE_PARM(rmac_util_period, "i");
MODULE_PARM(tx_timer_val, "i");
MODULE_PARM(tx_utilz_periodic, "i");
MODULE_PARM(rx_timer_val, "i");
MODULE_PARM(rx_utilz_periodic, "i");
MODULE_PARM(tx_urange_a, "i");
MODULE_PARM(tx_ufc_a, "i");
MODULE_PARM(tx_urange_b, "i");
MODULE_PARM(tx_ufc_b, "i");
MODULE_PARM(tx_urange_c, "i");
MODULE_PARM(tx_ufc_c, "i");
MODULE_PARM(tx_ufc_d, "i");
MODULE_PARM(rx_urange_a, "i");
MODULE_PARM(rx_ufc_a, "i");
MODULE_PARM(rx_urange_b, "i");
MODULE_PARM(rx_ufc_b, "i");
MODULE_PARM(rx_urange_c, "i");
MODULE_PARM(rx_ufc_c, "i");
MODULE_PARM(rx_ufc_d, "i");
MODULE_PARM(latency_timer, "i");
MODULE_PARM(max_read_byte_cnt, "i");
/**
 *  s2io_init_nic - Initialization of the adapter .
 *  @pdev : structure containing the PCI related information of the device.
 *  @pre: List of PCI devices supported by the driver listed in s2io_tbl.
 *  Description:
 *  The function initializes an adapter identified by the pci_dec structure.
 *  All OS related initialization including memory and device structure and
 *  initlaization of the device private variable is done. Also the swapper
 *  control register is initialized to enable read and write into the I/O
 *  registers of the device.
 *  Return value:
 *  returns 0 on success and negative on failure.

{
	nic_t *sp;
	struct net_device *dev;
	char *dev_name = "S2IO 10GE NIC";
	int i, j, ret;
	int dma_flag = FALSE;
	u32 mac_up, mac_down;
	u64 val64 = 0, tmp64 = 0;
	XENA_dev_config_t __iomem *bar0 = NULL;
	u16 subid;
	mac_info_t *mac_control;
	struct config_param *config;
	int mode;

#ifdef CONFIG_S2IO_NAPI
	DBG_PRINT(ERR_DBG, "NAPI support has been enabled\n");
#endif

	if ((ret = pci_enable_device(pdev))) {
		DBG_PRINT(ERR_DBG,

		return ret;
	}

	if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
		DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n");
		dma_flag = TRUE;

		if (pci_set_consistent_dma_mask
		    (pdev, DMA_64BIT_MASK)) {
			DBG_PRINT(ERR_DBG,
				  "Unable to obtain 64bit DMA for \
					consistent allocations\n");
			pci_disable_device(pdev);
			return -ENOMEM;
		}
	} else if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
		DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 32bit DMA\n");
	} else {
		pci_disable_device(pdev);

	memset(sp, 0, sizeof(nic_t));
	sp->dev = dev;
	sp->pdev = pdev;
	sp->vendor_id = pdev->vendor;
	sp->device_id = pdev->device;
	sp->high_dma_flag = dma_flag;
	sp->irq = pdev->irq;
	sp->device_enabled_once = FALSE;

	if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
		(pdev->device == PCI_DEVICE_ID_HERC_UNI))
		sp->device_type = XFRAME_II_DEVICE;
	else
		sp->device_type = XFRAME_I_DEVICE;

	/* Initialize some PCI/PCI-X fields of the NIC. */
	s2io_init_pci(sp);

	/*
	 * Setting the device configuration parameters.
	 * Most of these parameters can be specified by the user during
	 * module insertion as they are module loadable parameters. If
	 * these parameters are not not specified during load time, they
	 * are initialized with default values.
	 */
	mac_control = &sp->mac_control;
	config = &sp->config;

	/* Tx side parameters. */
	if (tx_fifo_len[0] == 0)
		tx_fifo_len[0] = DEFAULT_FIFO_LEN; /* Default value. */
	config->tx_fifo_num = tx_fifo_num;
	for (i = 0; i < MAX_TX_FIFOS; i++) {
		config->tx_cfg[i].fifo_len = tx_fifo_len[i];
		config->tx_cfg[i].fifo_priority = i;
	}

	/* mapping the QoS priority to the configured fifos */
	for (i = 0; i < MAX_TX_FIFOS; i++)
		config->fifo_mapping[i] = fifo_map[config->tx_fifo_num][i];

	config->tx_intr_type = TXD_INT_TYPE_UTILZ;
	for (i = 0; i < config->tx_fifo_num; i++) {
		config->tx_cfg[i].f_no_snoop =
	config->tx_cfg[7].FifoLen = TxFIFOLen_7;
	config->tx_cfg[7].FifoPriority = 7;

	config->TxIntrType = TXD_INT_TYPE_UTILZ;
	for (i = 0; i < config->TxFIFONum; i++) {
		config->tx_cfg[i].fNoSnoop =
		    (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
		if (config->tx_cfg[i].fifo_len < 65) {
			config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
			break;
		}
	}
	config->max_txds = MAX_SKB_FRAGS + 1;
	config->TxFlow = TRUE;

	/* Rx side parameters. */
	if (rx_ring_sz[0] == 0)
		rx_ring_sz[0] = SMALL_BLK_CNT; /* Default value. */
	config->rx_ring_num = rx_ring_num;
	for (i = 0; i < MAX_RX_RINGS; i++) {
		config->rx_cfg[i].num_rxd = rx_ring_sz[i] *
		    (MAX_RXDS_PER_BLOCK + 1);
		config->rx_cfg[i].ring_priority = i;
	config->rx_cfg[3].NumRxd = RxRingSz_3 * (MAX_RXDS_PER_BLOCK + 1);
	config->rx_cfg[3].RingPriority = 3;
	config->rx_cfg[4].NumRxd = RxRingSz_4 * (MAX_RXDS_PER_BLOCK + 1);
	config->rx_cfg[4].RingPriority = 4;
	config->rx_cfg[5].NumRxd = RxRingSz_5 * (MAX_RXDS_PER_BLOCK + 1);
	config->rx_cfg[5].RingPriority = 5;
	config->rx_cfg[6].NumRxd = RxRingSz_6 * (MAX_RXDS_PER_BLOCK + 1);
	config->rx_cfg[6].RingPriority = 6;
	config->rx_cfg[7].NumRxd = RxRingSz_7 * (MAX_RXDS_PER_BLOCK + 1);
	config->rx_cfg[7].RingPriority = 7;

	for (i = 0; i < RxRingNum; i++) {
		config->rx_cfg[i].RingOrg = RING_ORG_BUFF1;
		config->rx_cfg[i].RxdThresh = DEFAULT_RXD_THRESHOLD;
		config->rx_cfg[i].fNoSnoop =
		    (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
		config->rx_cfg[i].RxD_BackOff_Interval = TBD;
	}

	for (i = 0; i < rx_ring_num; i++) {
		config->rx_cfg[i].ring_org = RING_ORG_BUFF1;
		config->rx_cfg[i].f_no_snoop =
		    (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
	}
	config->JumboEnable = FALSE;

	/*  Setting Mac Control parameters */
	mac_control->txdl_len = MAX_SKB_FRAGS;
	mac_control->rmac_pause_time = rmac_pause_time;
	mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
	mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;


	/* Initialize Ring buffer parameters. */
	for (i = 0; i < config->rx_ring_num; i++)
		atomic_set(&sp->rx_bufs_left[i], 0);

	/* Initialize the number of ISRs currently running */
	atomic_set(&sp->isr_cnt, 0);

	/*  initialize the shared memory used by the NIC and the host */
	if (init_shared_mem(sp)) {
		DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n",
			  __FUNCTION__);
		ret = -ENOMEM;
		goto mem_alloc_failed;
	}

	sp->bar0 = ioremap(pci_resource_start(pdev, 0),
				     pci_resource_len(pdev, 0));
	if (!sp->bar0) {
		DBG_PRINT(ERR_DBG, "%s: S2IO: cannot remap io mem1\n",
			  dev->name);
		ret = -ENOMEM;
		goto bar0_remap_failed;
	}

	sp->bar1 = ioremap(pci_resource_start(pdev, 2),
				     pci_resource_len(pdev, 2));
	if (!sp->bar1) {
		DBG_PRINT(ERR_DBG, "%s: S2IO: cannot remap io mem2\n",
			  dev->name);
		ret = -ENOMEM;
		goto bar1_remap_failed;
	}



	/* Initializing the BAR1 address as the start of the FIFO pointer. */
	for (j = 0; j < MAX_TX_FIFOS; j++) {
		mac_control->tx_FIFO_start[j] = (TxFIFO_element_t __iomem *)
		    (sp->bar1 + (j * 0x00020000));
	}


	dev->set_multicast_list = &s2io_set_multicast;
	dev->do_ioctl = &s2io_ioctl;
	dev->change_mtu = &s2io_change_mtu;
#ifdef SET_ETHTOOL_OPS
	SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
	dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
	dev->vlan_rx_register = s2io_vlan_rx_register;
	dev->vlan_rx_kill_vid = (void *)s2io_vlan_rx_kill_vid;

	/*
	 * will use eth_mac_addr() for  dev->set_mac_address
	 * mac address will be set every time dev->open() is called
	 */
#if defined(CONFIG_S2IO_NAPI)
	dev->poll = s2io_poll;
	dev->weight = 32;
#endif

	dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
	if (cksum_offload_enable)
		dev->features |= NETIF_F_IP_CSUM;
	if (sp->high_dma_flag == TRUE)
		dev->features |= NETIF_F_HIGHDMA;
#ifdef NETIF_F_TSO
	dev->features |= NETIF_F_TSO;
		dev->features |= NETIF_F_TSO;
#endif

	dev->tx_timeout = &s2io_tx_watchdog;

	if (s2io_set_swapper(sp)) {
		DBG_PRINT(ERR_DBG, "%s:swapper settings are wrong\n",
			  dev->name);
		ret = -EAGAIN;
		goto set_swap_failed;
	}

	/* Verify if the Herc works on the slot its placed into */
	if (sp->device_type & XFRAME_II_DEVICE) {
		mode = s2io_verify_pci_mode(sp);
		if (mode < 0) {
			DBG_PRINT(ERR_DBG, "%s: ", __FUNCTION__);
			DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
			ret = -EBADSLT;
			goto set_swap_failed;
		}
	}

	/* Not needed for Herc */
	if (sp->device_type & XFRAME_I_DEVICE) {
		/*
		 * Fix for all "FFs" MAC address problems observed on
		 * Alpha platforms
		 */
		fix_mac_address(sp);
		s2io_reset(sp);
	}

	/*
	 * MAC address initialization.
	 * For now only one mac address will be read and used.
	 */
	bar0 = sp->bar0;
	val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
	    RMAC_ADDR_CMD_MEM_OFFSET(0 + MAC_MAC_ADDR_START_OFFSET);
	writeq(val64, &bar0->rmac_addr_cmd_mem);

	sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
	sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);

	DBG_PRINT(INIT_DBG,
		  "DEFAULT MAC ADDR:0x%02x-%02x-%02x-%02x-%02x-%02x\n",
		  sp->def_mac_addr[0].mac_addr[0],
		  sp->def_mac_addr[0].mac_addr[1],
		  sp->def_mac_addr[0].mac_addr[2],
		  sp->def_mac_addr[0].mac_addr[3],
		  sp->def_mac_addr[0].mac_addr[4],
		  sp->def_mac_addr[0].mac_addr[5]);

	/*  Set the factory defined MAC address initially   */
	dev->addr_len = ETH_ALEN;
	memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);

	/*
	 * Initialize the tasklet status and link state flags
	 * and the card state parameter
	 */
	atomic_set(&(sp->card_state), 0);
	sp->tasklet_status = 0;
	sp->link_state = 0;

	/* Initialize spinlocks */
	spin_lock_init(&sp->tx_lock);
#ifndef CONFIG_S2IO_NAPI
	spin_lock_init(&sp->put_lock);
#endif
	spin_lock_init(&sp->rx_lock);

	/*
	 * SXE-002: Configure link and activity LED to init state
	 * on driver load.
	 */
	subid = sp->pdev->subsystem_device;
	if ((subid & 0xFF) >= 0x07) {

		val64 |= 0x0000800000000000ULL;
		writeq(val64, &bar0->gpio_control);
		val64 = 0x0411040400000000ULL;
		writeq(val64, (void __iomem *) bar0 + 0x2700);
		val64 = readq(&bar0->gpio_control);
	}

	sp->rx_csum = 1;	/* Rx chksum verify enabled by default */

	if (register_netdev(dev)) {
		DBG_PRINT(ERR_DBG, "Device registration failed\n");
		ret = -ENODEV;
		goto register_failed;
	}

	if (sp->device_type & XFRAME_II_DEVICE) {
		DBG_PRINT(ERR_DBG, "%s: Neterion Xframe II 10GbE adapter ",
			  dev->name);
		DBG_PRINT(ERR_DBG, "(rev %d), %s",
				get_xena_rev_id(sp->pdev),
				s2io_driver_version);
#ifdef CONFIG_2BUFF_MODE
		DBG_PRINT(ERR_DBG, ", Buffer mode %d",2);
#endif

		DBG_PRINT(ERR_DBG, "\nCopyright(c) 2002-2005 Neterion Inc.\n");
		DBG_PRINT(ERR_DBG, "MAC ADDR: %02x:%02x:%02x:%02x:%02x:%02x\n",
			  sp->def_mac_addr[0].mac_addr[0],
			  sp->def_mac_addr[0].mac_addr[1],
			  sp->def_mac_addr[0].mac_addr[2],
			  sp->def_mac_addr[0].mac_addr[3],
			  sp->def_mac_addr[0].mac_addr[4],
			  sp->def_mac_addr[0].mac_addr[5]);
		mode = s2io_print_pci_mode(sp);
		if (mode < 0) {
			DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode ");
			ret = -EBADSLT;
			goto set_swap_failed;
		}
	} else {
		DBG_PRINT(ERR_DBG, "%s: Neterion Xframe I 10GbE adapter ",
			  dev->name);
		DBG_PRINT(ERR_DBG, "(rev %d), %s",
					get_xena_rev_id(sp->pdev),
					s2io_driver_version);
#ifdef CONFIG_2BUFF_MODE
		DBG_PRINT(ERR_DBG, ", Buffer mode %d",2);
#endif
		DBG_PRINT(ERR_DBG, "\nCopyright(c) 2002-2005 Neterion Inc.\n");
		DBG_PRINT(ERR_DBG, "MAC ADDR: %02x:%02x:%02x:%02x:%02x:%02x\n",
			  sp->def_mac_addr[0].mac_addr[0],
			  sp->def_mac_addr[0].mac_addr[1],
			  sp->def_mac_addr[0].mac_addr[2],
			  sp->def_mac_addr[0].mac_addr[3],
			  sp->def_mac_addr[0].mac_addr[4],
			  sp->def_mac_addr[0].mac_addr[5]);
	}

	/* Initialize device name */
	strcpy(sp->name, dev->name);
	if (sp->device_type & XFRAME_II_DEVICE)
		strcat(sp->name, ": Neterion Xframe II 10GbE adapter");
	else
		strcat(sp->name, ": Neterion Xframe I 10GbE adapter");

	/* Initialize bimodal Interrupts */
	sp->config.bimodal = bimodal;
	if (!(sp->device_type & XFRAME_II_DEVICE) && bimodal) {
		sp->config.bimodal = 0;
		DBG_PRINT(ERR_DBG,"%s:Bimodal intr not supported by Xframe I\n",
			dev->name);
	}

	/*
	 * Make Link state as off at this point, when the Link change
	 * interrupt comes the state will be automatically changed to
	 * the right state.
	 */
	netif_carrier_off(dev);
	sp->last_link_state = LINK_DOWN;

	return 0;


	pci_set_drvdata(pdev, NULL);
	free_netdev(dev);

	return ret;
}

/**
 * s2io_rem_nic - Free the PCI device
 * @pdev: structure containing the PCI related information of the device.
 * Description: This function is called by the Pci subsystem to release a
 * PCI device and free up all resource held up by the device. This could
 * be in response to a Hot plug event or when the driver is to be removed
 * from memory.
 */


	pci_disable_device(pdev);
	pci_release_regions(pdev);
	pci_set_drvdata(pdev, NULL);
#ifdef SNMP_SUPPORT
	s2io_bdsnmp_rem(dev);
#endif

	free_netdev(dev);
}



int __init s2io_starter(void)
{
	if (verify_load_parm())
		return -ENODEV;
	return pci_module_init(&s2io_driver);
}

/**
 * s2io_closer - Cleanup routine for the driver
 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
 */



module_init(s2io_starter);
module_exit(s2io_closer);
/**
 * verify_load_parm -  verifies the module loadable parameters
 * Descriptions: Verifies the module loadable paramters and initializes the
 * Tx Fifo, Rx Ring and other paramters.
 */

int verify_load_parm()
{
	int fail = 0;
	if (!((lso_enable == 0) || (lso_enable == 1))) {
		printk("lso_enable can be either '1' or '0'\n");
		fail = 1;
	}
#ifndef CONFIG_S2IO_NAPI
	if ((indicate_max_pkts > (0xFFFFFFFF))) {
		printk
		    ("indicate_max_pkts can take value greater than zero but less than 2power(32)\n");
		fail = 1;
	}
#endif
	if (!((cksum_offload_enable == 0) || (cksum_offload_enable == 1))) {
		printk("cksum_offload_enable can be only '0' or '1' \n");
		fail = 1;
	}
	if ((TxFifoNum == 0) || (TxFifoNum > 8)) {
		printk("TxFifoNum can take value from 1 to 8\n");
		fail = 1;
	}
	switch (TxFifoNum) {
	case 8:
		if ((TxFIFOLen_7 == 0) || TxFIFOLen_7 > 8192) {
			printk
			    ("TxFIFOLen_7 can take value from 1 to 8192\n");
			fail = 1;
		}
	case 7:
		if ((TxFIFOLen_6 == 0) || TxFIFOLen_6 > 8192) {
			printk
			    ("TxFIFOLen_6 can take value from 1 to 8192\n");
			fail = 1;
		}
	case 6:
		if ((TxFIFOLen_5 == 0) || TxFIFOLen_5 > 8192) {
			printk
			    ("TxFIFOLen_5 can take value from 1 to 8192\n");
			fail = 1;
		}
	case 5:
		if ((TxFIFOLen_4 == 0) || TxFIFOLen_4 > 8192) {
			printk
			    ("TxFIFOLen_4 can take value from 1 to 8192\n");
			fail = 1;
		}
	case 4:
		if ((TxFIFOLen_3 == 0) || TxFIFOLen_3 > 8192) {
			printk
			    ("TxFIFOLen_3 can take value from 1 to 8192\n");
			fail = 1;
		}
	case 3:
		if ((TxFIFOLen_2 == 0) || TxFIFOLen_2 > 8192) {
			printk
			    ("TxFIFOLen_2 can take value from 1 to 8192\n");
			fail = 1;
		}
	case 2:
		if ((TxFIFOLen_1 == 0) || TxFIFOLen_1 > 8192) {
			printk
			    ("TxFIFOLen_1 can take value from 1 to 8192\n");
			fail = 1;
		}
	case 1:
		if ((TxFIFOLen_0 == 0) || TxFIFOLen_0 > 8192) {
			printk
			    ("TxFIFOLen_0 can take value from 1 to 8192\n");
			fail = 1;
		}
	}
	if ((MaxTxDs > 32) || (MaxTxDs < 1)) {
		printk("MaxTxDs can take falue from 1 to 32\n");
		fail = 1;
	}
	if ((RxRingNum > 8) || (RxRingNum < 1)) {
		printk("RxRingNum can take falue from 1 to 8\n");
		fail = 1;
	}
	switch (RxRingNum) {
	case 8:
		if (RxRingSz_7 < 1) {
			printk
			    ("RxRingSz_7 can take value greater than 0\n");
			fail = 1;
		}
	case 7:
		if (RxRingSz_6 < 1) {
			printk
			    ("RxRingSz_6 can take value greater than 0\n");
			fail = 1;
		}
	case 6:
		if (RxRingSz_5 < 1) {
			printk
			    ("RxRingSz_5 can take value greater than 0\n");
			fail = 1;
		}
	case 5:
		if (RxRingSz_4 < 1) {
			printk
			    ("RxRingSz_4 can take value greater than 0\n");
			fail = 1;
		}
	case 4:
		if (RxRingSz_3 < 1) {
			printk
			    ("RxRingSz_3 can take value greater than 0\n");
			fail = 1;
		}
	case 3:
		if (RxRingSz_2 < 1) {
			printk
			    ("RxRingSz_2 can take value greater than 0\n");
			fail = 1;
		}
	case 2:
		if (RxRingSz_1 < 1) {
			printk
			    ("RxRingSz_1 can take value greater than 0\n");
			fail = 1;
		}
	case 1:
		if (RxRingSz_0 < 1) {
			printk
			    ("RxRingSz_0 can take value greater than 0\n");
			fail = 1;
		}
	}
	if ((Stats_refresh_time < 1)) {
		printk
		    ("Stats_refresh_time cannot be less than 1 second \n");
		fail = 1;
	}
	if (((rmac_pause_time < 0x10) && (rmac_pause_time != 0)) ||
	    (rmac_pause_time > 0xFFFF)) {
		printk
		    ("rmac_pause_time can take value from 16 to 65535\n");
		fail = 1;
	}
	if ((max_splits_trans < 0) || (max_splits_trans > 7)) {
		printk("max_splits_trans can take value from 0 to 7\n");
		fail = 1;
	}
	if ((mc_pause_threshold_q0q3 > 0xFE)) {
		printk("mc_pause_threshold_q0q3 cannot exceed 254\n");
		fail = 1;
	}
	if ((mc_pause_threshold_q4q7 > 0xFE)) {
		printk("mc_pause_threshold_q4q7 cannot exceed 254\n");
		fail = 1;
	}
	if ((latency_timer)
	    && ((latency_timer < 8) /* || (latency_timer > 255) */)) {
		printk("latency_timer can take value from 8 to 255\n");
		fail = 1;
	}
	if (max_read_byte_cnt > 3) {
		printk("max_read_byte_cnt can take value from 0 to 3\n");
		fail = 1;
	}
	if ((shared_splits > 31)) {
		printk("shared_splits cannot exceed 31\n");
		fail = 1;
	}
	if (rmac_util_period > 0xF) {
		printk("rmac_util_period cannot exceed 15\n");
		fail = 1;
	}
	if (tmac_util_period > 0xF) {
		printk("tmac_util_period cannot exceed 15\n");
		fail = 1;
	}
	if ((tx_utilz_periodic > 1) || (rx_utilz_periodic > 1)) {
		printk
		    ("tx_utilz_periodic & rx_utilz_periodic can be either "
		     "'0' or '1'\n");
		fail = 1;
	}
	if ((tx_urange_a > 127) || (tx_urange_b > 127)
	    || (tx_urange_c > 127)) {
		printk
		    ("tx_urange_a, tx_urange_b & tx_urange_c can take value "
		     "from 0 to 127\n");
		fail = 1;
	}
	if ((rx_urange_a > 127) || (rx_urange_b > 127)
	    || (rx_urange_c > 127)) {
		printk
		    ("rx_urange_a, rx_urange_b & rx_urange_c can take value "
		     "from 0 to 127\n");
		fail = 1;
	}
	if ((tx_ufc_a > 0xffff) || (tx_ufc_b > 0xffff) ||
	    (tx_ufc_c > 0xffff) || (tx_ufc_d > 0xffff)) {
		printk
		    (" tx_ufc_a, tx_ufc_b, tx_ufc_c, tx_ufc_d can take value"
		     "from 0 to 65535(0xFFFF)\n");
		fail = 1;
	}
	if ((rx_ufc_a > 0xffff) || (rx_ufc_b > 0xffff) ||
	    (rx_ufc_c > 0xffff) || (rx_ufc_d > 0xffff)) {
		printk
		    (" rx_ufc_a, rx_ufc_b, rx_ufc_c, rx_ufc_d can take value"
		     "from 0 to 65535(0xFFFF)\n");
		fail = 1;
	}
	return fail;
}

#ifdef SNMP_SUPPORT
/**
 * fnBaseDrv - Get the driver information
 * @pBaseDrv -Pointer to Base driver structure which contains the offset 
 * and length of each of the field.
 * Description
 * This function copies the driver specific information from the dev structure
 * to the pBaseDrv stucture. It calculates the number of physical adapters by
 * parsing the dev_base global variable maintained by the kernel. This 
 * variable has to read locked before accesing.This function is called by
 * fnBaseReadProc function.
 *
 */

static void fnBaseDrv(struct stBaseDrv *pBaseDrv, struct net_device *dev)
{

	struct pci_dev *pdev = NULL;
	struct net_device *ndev;
	int nCount = 0;
	nic_t *sp = (nic_t *) dev->priv;

	strncpy(pBaseDrv->m_cName, sp->cName, 20);
	strncpy(pBaseDrv->m_cVersion, sp->cVersion, 20);
	pBaseDrv->m_nStatus = sp->nLinkStatus;
	pBaseDrv->m_nFeature = sp->nFeature;
	pBaseDrv->m_nMemorySize = sp->nMemorySize;
	sprintf(pBaseDrv->m_cDate, "%ld", sp->lDate);
	/* 
	 * Find all the ethernet devices on the system using 
	 * pci_find_class. Get the private data which will be the 
	 * net_device structure assigned by the driver.
	 */
	while ((pdev =
		pci_find_class((PCI_CLASS_NETWORK_ETHERNET << 8), pdev))) {
		ndev = (struct net_device *) pci_get_drvdata(pdev);
		if (ndev == NULL)
			break;
		memcpy(pBaseDrv->m_stPhyAdap[nCount].m_cName, ndev->name,
		       20);
		pBaseDrv->m_stPhyAdap[nCount].m_nIndex = ndev->ifindex;
		nCount++;
	}
	pBaseDrv->m_nPhyCnt = nCount;
}

/* 
 *  fnBaseReadProc - Read entry point for the proc file  
 *  @page - Buffer pointer where the data is written
 *  @start- Pointer to buffer ptr . It is used if the data is more than a page
 *  @off- the offset to the page where data is written
 *  @count - number of bytes to write
 *  @eof - to indicate end of file
 *  @data - pointer to device structure.
 *
 * Description - 
 * This function gets  Base driver specific information from the fnBaseDrv 
 * function and writes into the BDInfo file. This function is called whenever 
 * the user reads the file. The length of data written cannot exceed 4kb. 
 * If it exceeds then use the start pointer to write multiple pages
 * Return - the length of the string written to proc file
 */
static int fnBaseReadProc(char *page, char **start, off_t off, int count,
			  int *eof, void *data)
{
	struct stBaseDrv *pBaseDrv;
	int nLength = 0;
	int nCount = 0;
	struct net_device *dev = (struct net_device *) data;
	int nIndex = 0;

	pBaseDrv = kmalloc(sizeof(struct stBaseDrv), GFP_KERNEL);
	if (pBaseDrv == NULL) {
		printk("Error allocating memory\n");
		return -ENOMEM;
	}
	fnBaseDrv(pBaseDrv, dev);
	sprintf(page + nLength, "%-30s%-20s\n", "Base Driver Name",
		pBaseDrv->m_cName);
	nLength += 51;
	if (pBaseDrv->m_nStatus == 1)
		sprintf(page + nLength, "%-30s%-20s\n", "Load Status",
			"Loaded");
	else
		sprintf(page + nLength, "%-30s%-20s\n", "Load Status",
			"UnLoaded");
	nLength += 51;
	sprintf(page + nLength, "%-30s%-20s\n", "Base Driver Version",
		pBaseDrv->m_cVersion);
	nLength += 51;

	sprintf(page + nLength, "%-30s%-20d\n", "Feature Supported",
		pBaseDrv->m_nFeature);
	nLength += 51;

	sprintf(page + nLength, "%-30s%-20d\n",
		"Base Driver Memrory in Bytes", pBaseDrv->m_nMemorySize);
	nLength += 51;

	sprintf(page + nLength, "%-30s%-20s\n", "Base Driver Date",
		pBaseDrv->m_cDate);
	nLength += 51;

	sprintf(page + nLength, "%-30s%-20d\n", "No of Phy Adapter",
		pBaseDrv->m_nPhyCnt);
	nLength += 51;
	sprintf(page + nLength, "%-20s%-20s\n\n", "Phy Adapter Index",
		"Phy Adapter Name");
	nLength += 42;

	for (nIndex = 0, nCount = pBaseDrv->m_nPhyCnt; nCount != 0;
	     nCount--, nIndex++) {
		sprintf(page + nLength, "%-20d%-20s\n",
			pBaseDrv->m_stPhyAdap[nIndex].m_nIndex,
			pBaseDrv->m_stPhyAdap[nIndex].m_cName);
		nLength += 41;
	}

	*eof = 1;
	kfree(pBaseDrv);
	return nLength;
}

/* 
 *  fnPhyAdapReadProc - Read entry point for the proc file  
 *  @page - Buffer pointer where the data is written
 *  @start- Pointer to buffer ptr . It is used if the data is more than a page
 *  @off- the offset to the page where data is written
 *  @count - number of bytes to write
 *  @eof - to indicate end of file
 *  @data - pointer to device structure.
 *
 * Description - 
 * This function gets  physical adapter information. This function is called
 * whenever the use* r reads the file. The length of data written cannot
 * exceed 4kb. If it exceeds then use the start pointer to write multiple page 
 *
 * Return - the length of the string written to proc file
 */
static int fnPhyAdapReadProc(char *page, char **start, off_t off,
			     int count, int *eof, void *data)
{

	struct stPhyData *pPhyData;
	pPhyData = kmalloc(sizeof(struct stPhyData), GFP_KERNEL);
	if (pPhyData == NULL) {
		printk("Error allocating memory\n");
		return -ENOMEM;
	}

	struct net_device *pNetDev;
	struct net_device_stats *pNetStat;
	int nLength = 0;
	unsigned char cMAC[20];

	/* Print the header in the PhyAdap proc file */
	sprintf(page + nLength,
		"%-10s%-22s%-10s%-10s%-22s%-22s%-10s%-10s%-10s%-10s%-10s%-10s%-10s%-10s%-10s%-10s%-10s%-10s%-10s%-10s\n",
		"Index", "Description", "Mode", "Type", "Speed", "MAC",
		"Status", "Slot", "Bus", "IRQ", "Colis", "Multi",
		"RxBytes", "RxDrop", "RxError", "RxPacket", "TRxBytes",
		"TRxDrop", "TxError", "TxPacket");

	/* 237 is the lenght of the above string copied in the page  */
	nLength += 237;

	struct pci_dev *pdev = NULL;
	/* 
	 * pci_find_class will return to the pointer to the pdev structure
	 * for all the network devices using PCI_CLASS_NETWORK_ETHERNET.
	 * The third argument is pointer to previous pdev structure.Initailly
	 * it has to be null
	 */
	while ((pdev =
		pci_find_class((PCI_CLASS_NETWORK_ETHERNET << 8), pdev))) {
		/* Private data will point to the netdevice structure */
		pNetDev = (struct net_device *) pci_get_drvdata(pdev);
		if (pNetDev == NULL)
			continue;
		if (pNetDev->addr_len != 0) {
			pNetStat = pNetDev->get_stats(pNetDev);
			pPhyData->m_nIndex = pNetDev->ifindex;
			memcpy(pPhyData->m_cDesc, pNetDev->name, 20);
			pPhyData->m_nMode = 0;
			pPhyData->m_nType = 0;
			switch (pPhyData->m_nType) {
				/* case IFT_ETHER:
				   memcpy(pPhyData->m_cSpeed,"10000000",20);
				   break;

				   case 9:
				   memcpy(pPhyData->m_cSpeed,"4000000",20);
				   break; */
			default:
				memcpy(pPhyData->m_cSpeed, "10000000", 20);
				break;
			}
			memcpy(pPhyData->m_cPMAC, pNetDev->dev_addr,
			       ETH_ALEN);
			memcpy(pPhyData->m_cCMAC, pNetDev->dev_addr,
			       ETH_ALEN);
			pPhyData->m_nLinkStatus =
			    test_bit(__LINK_STATE_START, &pNetDev->state);
			pPhyData->m_nPCISlot = PCI_SLOT(pdev->devfn);
			pPhyData->m_nPCIBus = pdev->bus->number;
			pPhyData->m_nIRQ = pNetDev->irq;
			pPhyData->m_nCollision = pNetStat->collisions;
			pPhyData->m_nMulticast = pNetStat->multicast;

			pPhyData->m_nRxBytes = pNetStat->rx_bytes;
			pPhyData->m_nRxDropped = pNetStat->rx_dropped;
			pPhyData->m_nRxErrors = pNetStat->rx_errors;
			pPhyData->m_nRxPackets = pNetStat->rx_packets;

			pPhyData->m_nTxBytes = pNetStat->tx_bytes;
			pPhyData->m_nTxDropped = pNetStat->tx_dropped;
			pPhyData->m_nTxErrors = pNetStat->tx_errors;
			pPhyData->m_nTxPackets = pNetStat->tx_packets;

			sprintf(cMAC, "%02x:%02x:%02x:%02x:%02x:%02x",
				pPhyData->m_cPMAC[0], pPhyData->m_cPMAC[1],
				pPhyData->m_cPMAC[2], pPhyData->m_cPMAC[3],
				pPhyData->m_cPMAC[4],
				pPhyData->m_cPMAC[5]);

			sprintf(page + nLength,
				"%-10d%-22s%-10d%-10d%-22s%-22s%-10d%-10d%-10d%-10d%-10d%-10d%-10d%-10d%-10d%-10d%-10d%-10d%-10d%-10d\n",
				pPhyData->m_nIndex, pPhyData->m_cDesc,
				pPhyData->m_nMode, pPhyData->m_nType,
				pPhyData->m_cSpeed, cMAC,
				pPhyData->m_nLinkStatus,
				pPhyData->m_nPCISlot, pPhyData->m_nPCIBus,
				pPhyData->m_nIRQ, pPhyData->m_nCollision,
				pPhyData->m_nMulticast,
				pPhyData->m_nRxBytes,
				pPhyData->m_nRxDropped,
				pPhyData->m_nRxErrors,
				pPhyData->m_nRxPackets,
				pPhyData->m_nTxBytes,
				pPhyData->m_nTxDropped,
				pPhyData->m_nTxErrors,
				pPhyData->m_nTxPackets);
			nLength += 237;
		}
	}

	*eof = 1;

	kfree(pPhyData);
	return nLength;
}

/* 
 * s2io_bdsnmp_init - Entry point to create proc file
 * @dev-  Pointer to net device structure passed by the driver.
 * Return 
 * Success If creates all the files
 * ERROR_PROC_ENTRY /ERROR_PROC_DIR Error If could not create all the files
 * Description
 * This functon is called when the driver is loaded. It creates the S2IO
 * proc file system in the /proc/net/ directory. This directory is used to 
 * store the info about the base driver afm driver, lacp, vlan  and nplus.
 * It checks if S2IO directory already exists else creates it and creates 
 * the files BDInfo  files and assiciates read function to each of the files.
 */

int s2io_bdsnmp_init(struct net_device *dev)
{
	struct proc_dir_entry *S2ioDir;
	struct proc_dir_entry *BaseDrv;
	struct proc_dir_entry *PhyAdap;
	int nLength = 0;

	nLength = strlen(S2IODIRNAME);
	/* IF the directory already exists then just return */
	for (S2ioDir = proc_net->subdir; S2ioDir != NULL;
	     S2ioDir = S2ioDir->next) {
		if ((S2ioDir->namelen == nLength)
		    && (!memcmp(S2ioDir->name, S2IODIRNAME, nLength)))
			break;
	}
	if (S2ioDir == NULL)
		/* Create the s2io directory */
		if (!
		    (S2ioDir =
		     create_proc_entry(S2IODIRNAME, S_IFDIR, proc_net))) {
			DBG_PRINT(INIT_DBG,
				  "Error Creating Proc directory for SNMP\n");
			return ERROR_PROC_DIR;
		}
	/* 
	 * Create the BDInfo file to store driver info and associate 
	 * read funtion.
	 */
	if (!
	    (BaseDrv =
	     create_proc_read_entry(BDFILENAME, S_IFREG | S_IRUSR, S2ioDir,
				    fnBaseReadProc, (void *) dev))) {
		DBG_PRINT(INIT_DBG,
			  "Error Creating Proc File for Base Drvr\n");
		return ERROR_PROC_ENTRY;
	}
	if (!
	    (PhyAdap =
	     create_proc_read_entry(PADAPFILENAME, S_IFREG | S_IRUSR,
				    S2ioDir, fnPhyAdapReadProc,
				    (void *) dev))) {
		DBG_PRINT(INIT_DBG,
			  "Error Creating Proc File for Phys Adap\n");
		return ERROR_PROC_ENTRY;
	}


	return SUCCESS;
}

/**
 * s2io_bdsnmp_rem : Removes the proc file entry
 * @dev - pointer to netdevice structre
 * Return - void
 * Description
 * This functon is called when the driver is Unloaded. It checks if the 
 * S2IO directoy exists and deletes the files in the reverse order of 
 * creation.
 */

void s2io_bdsnmp_rem(struct net_device *dev)
{
	int nLength = 0;
	struct proc_dir_entry *S2ioDir;
	nLength = strlen(S2IODIRNAME);
	/* 
	 * Check if the S2IO directory exists or not and then delete 
	 * all the files in the S2IO Directory 
	 */
	for (S2ioDir = proc_net->subdir; S2ioDir != NULL;
	     S2ioDir = S2ioDir->next) {
		if ((S2ioDir->namelen == nLength)
		    && (!memcmp(S2ioDir->name, S2IODIRNAME, nLength)))

			break;
	}
	if (S2ioDir == NULL)
		return;
	remove_proc_entry(BDFILENAME, S2ioDir);
	remove_proc_entry(PADAPFILENAME, S2ioDir);
	if (S2ioDir->subdir == NULL) {
		remove_proc_entry(S2IODIRNAME, proc_net);
	}
}
#endif

Lines 1-6 Link Here

(-)old/drivers/net/s2io.h (-394 / +274 lines)
1	/************************************************************************	1	/************************************************************************
2	* s2io.h: A Linux PCI-X Ethernet driver for S2IO 10GbE Server NIC	2	* s2io.h: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
3	* Copyright 2002 Raghavendra Koushik (raghavendra.koushik@s2io.com)	3	* Copyright(c) 2002-2005 Neterion Inc.
4		4
5	* This software may be used and distributed according to the terms of	5	* This software may be used and distributed according to the terms of
6	* the GNU General Public License (GPL), incorporated herein by reference.	6	* the GNU General Public License (GPL), incorporated herein by reference.
Lines 31-36 Link Here
31	#define SUCCESS 0	31	#define SUCCESS 0
32	#define FAILURE -1	32	#define FAILURE -1
33		33
		34	#ifndef NET_IP_ALIGN
		35	#define NET_IP_ALIGN 2
		36	#endif
		37
		38	/* Maximum time to flicker LED when asked to identify NIC using ethtool */
		39	#define MAX_FLICKER_TIME 60000 /* 60 Secs */
		40
34	/* Maximum outstanding splits to be configured into xena. */	41	/* Maximum outstanding splits to be configured into xena. */
35	typedef enum xena_max_outstanding_splits {	42	typedef enum xena_max_outstanding_splits {
36	XENA_ONE_SPLIT_TRANSACTION = 0,	43	XENA_ONE_SPLIT_TRANSACTION = 0,
Lines 45-58 typedef enum xena_max_outstanding_splits Link Here
45	#define XENA_MAX_OUTSTANDING_SPLITS(n) (n << 4)	52	#define XENA_MAX_OUTSTANDING_SPLITS(n) (n << 4)
46		53
47	/* OS concerned variables and constants */	54	/* OS concerned variables and constants */
48	#define WATCH_DOG_TIMEOUT 5*HZ	55	#define WATCH_DOG_TIMEOUT 15*HZ
49	#define EFILL 0x1234	56	#define EFILL 0x1234
50	#define ALIGN_SIZE 127	57	#define ALIGN_SIZE 127
51	#define PCIX_COMMAND_REGISTER 0x62	58	#define PCIX_COMMAND_REGISTER 0x62
52
53	#ifndef SET_ETHTOOL_OPS
54	#define SUPPORTED_10000baseT_Full (1 << 12)
55	#endif
56		59
57	/*	60	/*
58	* Debug related variables.	61	* Debug related variables.
Lines 75-197 int debug_level = ERR_DBG; /* Default le Link Here
75	#define L4_CKSUM_OK 0xFFFF	78	#define L4_CKSUM_OK 0xFFFF
76	#define S2IO_JUMBO_SIZE 9600	79	#define S2IO_JUMBO_SIZE 9600
77		80
		81	/* Driver statistics maintained by driver */
		82	typedef struct {
		83	unsigned long long single_ecc_errs;
		84	unsigned long long double_ecc_errs;
		85	} swStat_t;
		86
78	/* The statistics block of Xena */	87	/* The statistics block of Xena */
79	typedef struct stat_block {	88	typedef struct stat_block {
80	#ifdef __BIG_ENDIAN
81	/* Tx MAC statistics counters. */
82	u32 tmac_frms;
83	u32 tmac_data_octets;
84	u64 tmac_drop_frms;
85	u32 tmac_mcst_frms;
86	u32 tmac_bcst_frms;
87	u64 tmac_pause_ctrl_frms;
88	u32 tmac_ttl_octets;
89	u32 tmac_ucst_frms;
90	u32 tmac_nucst_frms;
91	u32 tmac_any_err_frms;
92	u64 tmac_ttl_less_fb_octets;
93	u64 tmac_vld_ip_octets;
94	u32 tmac_vld_ip;
95	u32 tmac_drop_ip;
96	u32 tmac_icmp;
97	u32 tmac_rst_tcp;
98	u64 tmac_tcp;
99	u32 tmac_udp;
100	u32 reserved_0;
101
102	/* Rx MAC Statistics counters. */
103	u32 rmac_vld_frms;
104	u32 rmac_data_octets;
105	u64 rmac_fcs_err_frms;
106	u64 rmac_drop_frms;
107	u32 rmac_vld_mcst_frms;
108	u32 rmac_vld_bcst_frms;
109	u32 rmac_in_rng_len_err_frms;
110	u32 rmac_out_rng_len_err_frms;
111	u64 rmac_long_frms;
112	u64 rmac_pause_ctrl_frms;
113	u64 rmac_unsup_ctrl_frms;
114	u32 rmac_ttl_octets;
115	u32 rmac_accepted_ucst_frms;
116	u32 rmac_accepted_nucst_frms;
117	u32 rmac_discarded_frms;
118	u32 rmac_drop_events;
119	u32 reserved_1;
120	u64 rmac_ttl_less_fb_octets;
121	u64 rmac_ttl_frms;
122	u64 reserved_2;
123	u32 reserved_3;
124	u32 rmac_usized_frms;
125	u32 rmac_osized_frms;
126	u32 rmac_frag_frms;
127	u32 rmac_jabber_frms;
128	u32 reserved_4;
129	u64 rmac_ttl_64_frms;
130	u64 rmac_ttl_65_127_frms;
131	u64 reserved_5;
132	u64 rmac_ttl_128_255_frms;
133	u64 rmac_ttl_256_511_frms;
134	u64 reserved_6;
135	u64 rmac_ttl_512_1023_frms;
136	u64 rmac_ttl_1024_1518_frms;
137	u32 reserved_7;
138	u32 rmac_ip;
139	u64 rmac_ip_octets;
140	u32 rmac_hdr_err_ip;
141	u32 rmac_drop_ip;
142	u32 rmac_icmp;
143	u32 reserved_8;
144	u64 rmac_tcp;
145	u32 rmac_udp;
146	u32 rmac_err_drp_udp;
147	u64 rmac_xgmii_err_sym;
148	u64 rmac_frms_q0;
149	u64 rmac_frms_q1;
150	u64 rmac_frms_q2;
151	u64 rmac_frms_q3;
152	u64 rmac_frms_q4;
153	u64 rmac_frms_q5;
154	u64 rmac_frms_q6;
155	u64 rmac_frms_q7;
156	u16 rmac_full_q0;
157	u16 rmac_full_q1;
158	u16 rmac_full_q2;
159	u16 rmac_full_q3;
160	u16 rmac_full_q4;
161	u16 rmac_full_q5;
162	u16 rmac_full_q6;
163	u16 rmac_full_q7;
164	u32 rmac_pause_cnt;
165	u32 reserved_9;
166	u64 rmac_xgmii_data_err_cnt;
167	u64 rmac_xgmii_ctrl_err_cnt;
168	u32 rmac_accepted_ip;
169	u32 rmac_err_tcp;
170
171	/* PCI/PCI-X Read transaction statistics. */
172	u32 rd_req_cnt;
173	u32 new_rd_req_cnt;
174	u32 new_rd_req_rtry_cnt;
175	u32 rd_rtry_cnt;
176	u32 wr_rtry_rd_ack_cnt;
177
178	/* PCI/PCI-X write transaction statistics. */
179	u32 wr_req_cnt;
180	u32 new_wr_req_cnt;
181	u32 new_wr_req_rtry_cnt;
182	u32 wr_rtry_cnt;
183	u32 wr_disc_cnt;
184	u32 rd_rtry_wr_ack_cnt;
185
186	/* DMA Transaction statistics. */
187	u32 txp_wr_cnt;
188	u32 txd_rd_cnt;
189	u32 txd_wr_cnt;
190	u32 rxd_rd_cnt;
191	u32 rxd_wr_cnt;
192	u32 txf_rd_cnt;
193	u32 rxf_wr_cnt;
194	#else
195	/* Tx MAC statistics counters. */	89	/* Tx MAC statistics counters. */
196	u32 tmac_data_octets;	90	u32 tmac_data_octets;
197	u32 tmac_frms;	91	u32 tmac_frms;
Lines 305-321 typedef struct stat_block { Link Here
305	u32 rxd_rd_cnt;	199	u32 rxd_rd_cnt;
306	u32 rxf_wr_cnt;	200	u32 rxf_wr_cnt;
307	u32 txf_rd_cnt;	201	u32 txf_rd_cnt;
308	#endif	202
		203	/* Tx MAC statistics overflow counters. */
		204	u32 tmac_data_octets_oflow;
		205	u32 tmac_frms_oflow;
		206	u32 tmac_bcst_frms_oflow;
		207	u32 tmac_mcst_frms_oflow;
		208	u32 tmac_ucst_frms_oflow;
		209	u32 tmac_ttl_octets_oflow;
		210	u32 tmac_any_err_frms_oflow;
		211	u32 tmac_nucst_frms_oflow;
		212	u64 tmac_vlan_frms;
		213	u32 tmac_drop_ip_oflow;
		214	u32 tmac_vld_ip_oflow;
		215	u32 tmac_rst_tcp_oflow;
		216	u32 tmac_icmp_oflow;
		217	u32 tpa_unknown_protocol;
		218	u32 tmac_udp_oflow;
		219	u32 reserved_10;
		220	u32 tpa_parse_failure;
		221
		222	/* Rx MAC Statistics overflow counters. */
		223	u32 rmac_data_octets_oflow;
		224	u32 rmac_vld_frms_oflow;
		225	u32 rmac_vld_bcst_frms_oflow;
		226	u32 rmac_vld_mcst_frms_oflow;
		227	u32 rmac_accepted_ucst_frms_oflow;
		228	u32 rmac_ttl_octets_oflow;
		229	u32 rmac_discarded_frms_oflow;
		230	u32 rmac_accepted_nucst_frms_oflow;
		231	u32 rmac_usized_frms_oflow;
		232	u32 rmac_drop_events_oflow;
		233	u32 rmac_frag_frms_oflow;
		234	u32 rmac_osized_frms_oflow;
		235	u32 rmac_ip_oflow;
		236	u32 rmac_jabber_frms_oflow;
		237	u32 rmac_icmp_oflow;
		238	u32 rmac_drop_ip_oflow;
		239	u32 rmac_err_drp_udp_oflow;
		240	u32 rmac_udp_oflow;
		241	u32 reserved_11;
		242	u32 rmac_pause_cnt_oflow;
		243	u64 rmac_ttl_1519_4095_frms;
		244	u64 rmac_ttl_4096_8191_frms;
		245	u64 rmac_ttl_8192_max_frms;
		246	u64 rmac_ttl_gt_max_frms;
		247	u64 rmac_osized_alt_frms;
		248	u64 rmac_jabber_alt_frms;
		249	u64 rmac_gt_max_alt_frms;
		250	u64 rmac_vlan_frms;
		251	u32 rmac_len_discard;
		252	u32 rmac_fcs_discard;
		253	u32 rmac_pf_discard;
		254	u32 rmac_da_discard;
		255	u32 rmac_red_discard;
		256	u32 rmac_rts_discard;
		257	u32 reserved_12;
		258	u32 rmac_ingm_full_discard;
		259	u32 reserved_13;
		260	u32 rmac_accepted_ip_oflow;
		261	u32 reserved_14;
		262	u32 link_fault_cnt;
		263	swStat_t sw_stat;
309	} StatInfo_t;	264	} StatInfo_t;
310		265
311	/* Structures representing different init time configuration	266	/*
		267	* Structures representing different init time configuration
312	* parameters of the NIC.	268	* parameters of the NIC.
313	*/	269	*/
314		270
		271	#define MAX_TX_FIFOS 8
		272	#define MAX_RX_RINGS 8
		273
		274	/* FIFO mappings for all possible number of fifos configured */
		275	int fifo_map[][MAX_TX_FIFOS] = {
		276	{0, 0, 0, 0, 0, 0, 0, 0},
		277	{0, 0, 0, 0, 1, 1, 1, 1},
		278	{0, 0, 0, 1, 1, 1, 2, 2},
		279	{0, 0, 1, 1, 2, 2, 3, 3},
		280	{0, 0, 1, 1, 2, 2, 3, 4},
		281	{0, 0, 1, 1, 2, 3, 4, 5},
		282	{0, 0, 1, 2, 3, 4, 5, 6},
		283	{0, 1, 2, 3, 4, 5, 6, 7},
		284	};
		285
315	/* Maintains Per FIFO related information. */	286	/* Maintains Per FIFO related information. */
316	typedef struct tx_fifo_config {	287	typedef struct tx_fifo_config {
317	#define MAX_AVAILABLE_TXDS 8192	288	#define MAX_AVAILABLE_TXDS 8192
318	u32 FifoLen; /* specifies len of FIFO upto 8192, ie no of TxDLs */	289	u32 fifo_len; /* specifies len of FIFO upto 8192, ie no of TxDLs */
319	/* Priority definition */	290	/* Priority definition */
320	#define TX_FIFO_PRI_0 0 /Highest /	291	#define TX_FIFO_PRI_0 0 /Highest /
321	#define TX_FIFO_PRI_1 1	292	#define TX_FIFO_PRI_1 1
Lines 325-333 typedef struct tx_fifo_config { Link Here
325	#define TX_FIFO_PRI_5 5	296	#define TX_FIFO_PRI_5 5
326	#define TX_FIFO_PRI_6 6	297	#define TX_FIFO_PRI_6 6
327	#define TX_FIFO_PRI_7 7 /lowest /	298	#define TX_FIFO_PRI_7 7 /lowest /
328	u8 FifoPriority; /* specifies pointer level for FIFO */	299	u8 fifo_priority; /* specifies pointer level for FIFO */
329	/* user should not set twos fifos with same pri */	300	/* user should not set twos fifos with same pri */
330	u8 fNoSnoop;	301	u8 f_no_snoop;
331	#define NO_SNOOP_TXD 0x01	302	#define NO_SNOOP_TXD 0x01
332	#define NO_SNOOP_TXD_BUFFER 0x02	303	#define NO_SNOOP_TXD_BUFFER 0x02
333	} tx_fifo_config_t;	304	} tx_fifo_config_t;
Lines 335-341 typedef struct tx_fifo_config { Link Here
335		306
336	/* Maintains per Ring related information */	307	/* Maintains per Ring related information */
337	typedef struct rx_ring_config {	308	typedef struct rx_ring_config {
338	u32 NumRxd; /No of RxDs per Rx Ring /	309	u32 num_rxd; /No of RxDs per Rx Ring /
339	#define RX_RING_PRI_0 0 /* highest */	310	#define RX_RING_PRI_0 0 /* highest */
340	#define RX_RING_PRI_1 1	311	#define RX_RING_PRI_1 1
341	#define RX_RING_PRI_2 2	312	#define RX_RING_PRI_2 2
Lines 345-420 typedef struct rx_ring_config { Link Here
345	#define RX_RING_PRI_6 6	316	#define RX_RING_PRI_6 6
346	#define RX_RING_PRI_7 7 /* lowest */	317	#define RX_RING_PRI_7 7 /* lowest */
347		318
348	u8 RingPriority; /Specifies service priority of ring /	319	u8 ring_priority; /Specifies service priority of ring /
349	/* OSM should not set any two rings with same priority */	320	/* OSM should not set any two rings with same priority */
350	u8 RingOrg; /Organization of ring /	321	u8 ring_org; /Organization of ring /
351	#define RING_ORG_BUFF1 0x01	322	#define RING_ORG_BUFF1 0x01
352	#define RX_RING_ORG_BUFF3 0x03	323	#define RX_RING_ORG_BUFF3 0x03
353	#define RX_RING_ORG_BUFF5 0x05	324	#define RX_RING_ORG_BUFF5 0x05
354		325
355	/* In case of 3 buffer recv. mode, size of three buffers is expected as.. */	326	u8 f_no_snoop;
356	#define BUFF_SZ_1 22 /* ethernet header */
357	#define BUFF_SZ_2 (64+64) /* max. IP+TCP header size */
358	#define BUFF_SZ_3 (1500-20-20) /* TCP payload */
359	#define BUFF_SZ_3_JUMBO (9600-20-20) /* Jumbo TCP payload */
360
361	u32 RxdThresh; /No of used Rxds NIC can store before transfer to host /
362	#define DEFAULT_RXD_THRESHOLD 0x1 /* TODO */
363	u8 fNoSnoop;
364	#define NO_SNOOP_RXD 0x01	327	#define NO_SNOOP_RXD 0x01
365	#define NO_SNOOP_RXD_BUFFER 0x02	328	#define NO_SNOOP_RXD_BUFFER 0x02
366	u32 RxD_BackOff_Interval;
367	#define RXD_BACKOFF_INTERVAL_DEF 0x0
368	#define RXD_BACKOFF_INTERVAL_MIN 0x0
369	#define RXD_BACKOFF_INTERVAL_MAX 0x0
370	} rx_ring_config_t;	329	} rx_ring_config_t;
371		330
372	/* This structure provides contains values of the tunable parameters	331	/* This structure provides contains values of the tunable parameters
373	* of the H/W	332	* of the H/W
374	*/	333	*/
375	struct config_param {	334	struct config_param {
376
377	/* Tx Side */	335	/* Tx Side */
378	u32 TxFIFONum; /Number of Tx FIFOs /	336	u32 tx_fifo_num; /Number of Tx FIFOs /
379	#define MAX_TX_FIFOS 8
380		337
		338	u8 fifo_mapping[MAX_TX_FIFOS];
381	tx_fifo_config_t tx_cfg[MAX_TX_FIFOS]; /Per-Tx FIFO config /	339	tx_fifo_config_t tx_cfg[MAX_TX_FIFOS]; /Per-Tx FIFO config /
382	u32 MaxTxDs; /Max no. of Tx buffer descriptor per TxDL /	340	u32 max_txds; /Max no. of Tx buffer descriptor per TxDL /
383	BOOL TxVLANEnable; /TRUE: Insert VLAN ID, FALSE: Don't insert /	341	u64 tx_intr_type;
384	#define TX_REQ_TIMEOUT_DEFAULT 0x0	342	/* Specifies if Tx Intr is UTILZ or PER_LIST type. */
385	#define TX_REQ_TIMEOUT_MIN 0x0
386	#define TX_REQ_TIMEOUT_MAX 0x0
387	u32 TxReqTimeOut;
388	BOOL TxFlow; /Tx flow control enable /
389	BOOL RxFlow;
390	BOOL OverrideTxServiceState; /* TRUE: Overide, FALSE: Do not override
391	Use the new priority information
392	of service state. It is not recommended
393	to change but OSM can opt to do so */
394	#define MAX_SERVICE_STATES 36
395	u8 TxServiceState[MAX_SERVICE_STATES];
396	/* Array element represent 'priority'
397	* and array index represents
398	* 'Service state' e.g.
399	* TxServiceState[3]=7; it means
400	* Service state 3 is associated
401	* with priority 7 of a Tx FIFO */
402	u64 TxIntrType; /* Specifies if Tx Intr is UTILZ or PER_LIST type. */
403		343
404	/* Rx Side */	344	/* Rx Side */
405	u32 RxRingNum; /Number of receive rings /	345	u32 rx_ring_num; /Number of receive rings /
406	#define MAX_RX_RINGS 8
407	#define MAX_RX_BLOCKS_PER_RING 150	346	#define MAX_RX_BLOCKS_PER_RING 150
408		347
409	rx_ring_config_t rx_cfg[MAX_RX_RINGS]; /Per-Rx Ring config /	348	rx_ring_config_t rx_cfg[MAX_RX_RINGS]; /Per-Rx Ring config /
410	BOOL RxVLANEnable; /*TRUE: Strip off VLAN tag from the frame,	349	u8 bimodal; /Flag for setting bimodal interrupts/
411	FALSE: Don't strip off VLAN tag */
412		350
413	#define HEADER_ETHERNET_II_802_3_SIZE 14	351	#define HEADER_ETHERNET_II_802_3_SIZE 14
414	#define HEADER_802_2_SIZE 3	352	#define HEADER_802_2_SIZE 3
415	#define HEADER_SNAP_SIZE 5	353	#define HEADER_SNAP_SIZE 5
416	#define HEADER_VLAN_SIZE 4	354	#define HEADER_VLAN_SIZE 4
417	#define HEADER_ALIGN_LAYER_3 2
418		355
419	#define MIN_MTU 46	356	#define MIN_MTU 46
420	#define MAX_PYLD 1500	357	#define MAX_PYLD 1500
Lines 423-445 struct config_param { Link Here
423	#define MAX_PYLD_JUMBO 9600	360	#define MAX_PYLD_JUMBO 9600
424	#define MAX_MTU_JUMBO (MAX_PYLD_JUMBO+18)	361	#define MAX_MTU_JUMBO (MAX_PYLD_JUMBO+18)
425	#define MAX_MTU_JUMBO_VLAN (MAX_PYLD_JUMBO+22)	362	#define MAX_MTU_JUMBO_VLAN (MAX_PYLD_JUMBO+22)
426	u32 MTU; /Maximum Payload /	363	u16 bus_speed;
427	BOOL JumboEnable; /Enable Jumbo frames recv/send /
428	BOOL OverrideRxServiceState; /* TRUE: Overide, FALSE: Do not override
429	Use the new priority information
430	of service state. It is not recommended
431	to change but OSM can opt to do so */
432	#define MAX_SERVICE_STATES 36
433	u8 RxServiceState[MAX_SERVICE_STATES];
434	/* Array element represent 'priority'
435	* and array index represents
436	* 'Service state'e.g.
437	* RxServiceState[3]=7; it means
438	* Service state 3 is associated
439	* with priority 7 of a Rx FIFO */
440	BOOL StatAutoRefresh; /* When true, StatRefreshTime have valid value */
441	u32 StatRefreshTime; /Time for refreshing statistics /
442	#define STAT_TRSF_PER_1_SECOND 0x208D5
443	};	364	};
444		365
445	/* Structure representing MAC Addrs */	366	/* Structure representing MAC Addrs */
Lines 448-454 typedef struct mac_addr { Link Here
448	} macaddr_t;	369	} macaddr_t;
449		370
450	/* Structure that represent every FIFO element in the BAR1	371	/* Structure that represent every FIFO element in the BAR1
451	* Address location.	372	* Address location.
452	*/	373	*/
453	typedef struct _TxFIFO_element {	374	typedef struct _TxFIFO_element {
454	u64 TxDL_Pointer;	375	u64 TxDL_Pointer;
Lines 510-515 typedef struct _RxD_t { Link Here
510	#define RXD_FRAME_PROTO vBIT(0xFFFF,24,8)	431	#define RXD_FRAME_PROTO vBIT(0xFFFF,24,8)
511	#define RXD_FRAME_PROTO_IPV4 BIT(27)	432	#define RXD_FRAME_PROTO_IPV4 BIT(27)
512	#define RXD_FRAME_PROTO_IPV6 BIT(28)	433	#define RXD_FRAME_PROTO_IPV6 BIT(28)
		434	#define RXD_FRAME_IP_FRAG BIT(29)
513	#define RXD_FRAME_PROTO_TCP BIT(30)	435	#define RXD_FRAME_PROTO_TCP BIT(30)
514	#define RXD_FRAME_PROTO_UDP BIT(31)	436	#define RXD_FRAME_PROTO_UDP BIT(31)
515	#define TCP_OR_UDP_FRAME (RXD_FRAME_PROTO_TCP \| RXD_FRAME_PROTO_UDP)	437	#define TCP_OR_UDP_FRAME (RXD_FRAME_PROTO_TCP \| RXD_FRAME_PROTO_UDP)
Lines 517-527 typedef struct _RxD_t { Link Here
517	#define RXD_GET_L4_CKSUM(val) ((u16)(val) & 0xFFFF)	439	#define RXD_GET_L4_CKSUM(val) ((u16)(val) & 0xFFFF)
518		440
519	u64 Control_2;	441	u64 Control_2;
		442	#define THE_RXD_MARK 0x3
		443	#define SET_RXD_MARKER vBIT(THE_RXD_MARK, 0, 2)
		444	#define GET_RXD_MARKER(ctrl) ((ctrl & SET_RXD_MARKER) >> 62)
		445
520	#ifndef CONFIG_2BUFF_MODE	446	#ifndef CONFIG_2BUFF_MODE
521	#define MASK_BUFFER0_SIZE vBIT(0xFFFF,0,16)	447	#define MASK_BUFFER0_SIZE vBIT(0x3FFF,2,14)
522	#define SET_BUFFER0_SIZE(val) vBIT(val,0,16)	448	#define SET_BUFFER0_SIZE(val) vBIT(val,2,14)
523	#else	449	#else
524	#define MASK_BUFFER0_SIZE vBIT(0xFF,0,16)	450	#define MASK_BUFFER0_SIZE vBIT(0xFF,2,14)
525	#define MASK_BUFFER1_SIZE vBIT(0xFFFF,16,16)	451	#define MASK_BUFFER1_SIZE vBIT(0xFFFF,16,16)
526	#define MASK_BUFFER2_SIZE vBIT(0xFFFF,32,16)	452	#define MASK_BUFFER2_SIZE vBIT(0xFFFF,32,16)
527	#define SET_BUFFER0_SIZE(val) vBIT(val,8,8)	453	#define SET_BUFFER0_SIZE(val) vBIT(val,8,8)
Lines 534-540 typedef struct _RxD_t { Link Here
534	#define SET_NUM_TAG(val) vBIT(val,16,32)	460	#define SET_NUM_TAG(val) vBIT(val,16,32)
535		461
536	#ifndef CONFIG_2BUFF_MODE	462	#ifndef CONFIG_2BUFF_MODE
537	#define RXD_GET_BUFFER0_SIZE(Control_2) (u64)((Control_2 & vBIT(0xFFFF,0,16)))	463	#define RXD_GET_BUFFER0_SIZE(Control_2) (u64)((Control_2 & vBIT(0x3FFF,2,14)))
538	#else	464	#else
539	#define RXD_GET_BUFFER0_SIZE(Control_2) (u8)((Control_2 & MASK_BUFFER0_SIZE) \	465	#define RXD_GET_BUFFER0_SIZE(Control_2) (u8)((Control_2 & MASK_BUFFER0_SIZE) \
540	>> 48)	466	>> 48)
Lines 553-559 typedef struct _RxD_t { Link Here
553	#endif	479	#endif
554	} RxD_t;	480	} RxD_t;
555		481
556	/* Structure that represents the Rx descriptor block which contains	482	/* Structure that represents the Rx descriptor block which contains
557	* 128 Rx descriptors.	483	* 128 Rx descriptors.
558	*/	484	*/
559	#ifndef CONFIG_2BUFF_MODE	485	#ifndef CONFIG_2BUFF_MODE
Lines 563-573 typedef struct _RxD_block { Link Here
563		489
564	u64 reserved_0;	490	u64 reserved_0;
565	#define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL	491	#define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL
566	u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last	492	u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last
567	* Rxd in this blk */	493	* Rxd in this blk */
568	u64 reserved_2_pNext_RxD_block; /* Logical ptr to next */	494	u64 reserved_2_pNext_RxD_block; /* Logical ptr to next */
569	u64 pNext_RxD_Blk_physical; /* Buff0_ptr.In a 32 bit arch	495	u64 pNext_RxD_Blk_physical; /* Buff0_ptr.In a 32 bit arch
570	* the upper 32 bits should	496	* the upper 32 bits should
571	* be 0 */	497	* be 0 */
572	} RxD_block_t;	498	} RxD_block_t;
573	#else	499	#else
Lines 576-588 typedef struct _RxD_block { Link Here
576	RxD_t rxd[MAX_RXDS_PER_BLOCK];	502	RxD_t rxd[MAX_RXDS_PER_BLOCK];
577		503
578	#define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL	504	#define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL
579	u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last Rxd	505	u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last Rxd
580	* in this blk */	506	* in this blk */
581	u64 pNext_RxD_Blk_physical; /* Phy ponter to next blk. */	507	u64 pNext_RxD_Blk_physical; /* Phy ponter to next blk. */
582	} RxD_block_t;	508	} RxD_block_t;
583	#define SIZE_OF_BLOCK 4096	509	#define SIZE_OF_BLOCK 4096
584		510
585	/* Structure to hold virtual addresses of Buf0 and Buf1 in	511	/* Structure to hold virtual addresses of Buf0 and Buf1 in
586	* 2buf mode. */	512	* 2buf mode. */
587	typedef struct bufAdd {	513	typedef struct bufAdd {
588	void *ba_0_org;	514	void *ba_0_org;
Lines 594-601 typedef struct bufAdd { Link Here
594		520
595	/* Structure which stores all the MAC control parameters */	521	/* Structure which stores all the MAC control parameters */
596		522
597	/* This structure stores the offset of the RxD in the ring	523	/* This structure stores the offset of the RxD in the ring
598	* from which the Rx Interrupt processor can start picking	524	* from which the Rx Interrupt processor can start picking
599	* up the RxDs for processing.	525	* up the RxDs for processing.
600	*/	526	*/
601	typedef struct _rx_curr_get_info_t {	527	typedef struct _rx_curr_get_info_t {
Lines 607-613 typedef struct _rx_curr_get_info_t { Link Here
607	typedef rx_curr_get_info_t rx_curr_put_info_t;	533	typedef rx_curr_get_info_t rx_curr_put_info_t;
608		534
609	/* This structure stores the offset of the TxDl in the FIFO	535	/* This structure stores the offset of the TxDl in the FIFO
610	* from which the Tx Interrupt processor can start picking	536	* from which the Tx Interrupt processor can start picking
611	* up the TxDLs for send complete interrupt processing.	537	* up the TxDLs for send complete interrupt processing.
612	*/	538	*/
613	typedef struct {	539	typedef struct {
Lines 617-673 typedef struct { Link Here
617		543
618	typedef tx_curr_get_info_t tx_curr_put_info_t;	544	typedef tx_curr_get_info_t tx_curr_put_info_t;
619		545
620	/* Infomation related to the Tx and Rx FIFOs and Rings of Xena	546	/* Structure that holds the Phy and virt addresses of the Blocks */
621	* is maintained in this structure.	547	typedef struct rx_block_info {
622	*/	548	RxD_t *block_virt_addr;
623	typedef struct mac_info {	549	dma_addr_t block_dma_addr;
624	/* rx side stuff */	550	} rx_block_info_t;
625	u32 rxd_ring_mem_sz;	551
		552	/* pre declaration of the nic structure */
		553	typedef struct s2io_nic nic_t;
		554
		555	/* Ring specific structure */
		556	typedef struct ring_info {
		557	/* The ring number */
		558	int ring_no;
		559
		560	/*
		561	* Place holders for the virtual and physical addresses of
		562	* all the Rx Blocks
		563	*/
		564	rx_block_info_t rx_blocks[MAX_RX_BLOCKS_PER_RING];
		565	int block_count;
		566	int pkt_cnt;
626		567
627	/* Put pointer info which indictes which RxD has to be replenished	568	/*
		569	* Put pointer info which indictes which RxD has to be replenished
628	* with a new buffer.	570	* with a new buffer.
629	*/	571	*/
630	rx_curr_put_info_t rx_curr_put_info[MAX_RX_RINGS];	572	rx_curr_put_info_t rx_curr_put_info;
631		573
632	/* Get pointer info which indictes which is the last RxD that was	574	/*
		575	* Get pointer info which indictes which is the last RxD that was
633	* processed by the driver.	576	* processed by the driver.
634	*/	577	*/
635	rx_curr_get_info_t rx_curr_get_info[MAX_RX_RINGS];	578	rx_curr_get_info_t rx_curr_get_info;
636		579
637	u16 rmac_pause_time;	580	#ifndef CONFIG_S2IO_NAPI
638	u16 mc_pause_threshold_q0q3;	581	/* Index to the absolute position of the put pointer of Rx ring */
639	u16 mc_pause_threshold_q4q7;	582	int put_pos;
		583	#endif
640		584
		585	#ifdef CONFIG_2BUFF_MODE
		586	/* Buffer Address store. */
		587	buffAdd_t **ba;
		588	#endif
		589	nic_t *nic;
		590	} ring_info_t;
		591
		592	/* Fifo specific structure */
		593	typedef struct fifo_info {
		594	/* FIFO number */
		595	int fifo_no;
		596
		597	/* Maximum TxDs per TxDL */
		598	int max_txds;
		599
		600	/* Place holder of all the TX List's Phy and Virt addresses. */
		601	list_info_hold_t *list_info;
641		602
642	/* this will be used in receive function, this decides which ring would	603	/*
643	be processed first. eg: ring with priority value 0 (highest) should	604	* Current offset within the tx FIFO where driver would write
644	be processed first.	605	* new Tx frame
645	first 3 LSB bits represent ring number which should be processed
646	first, similarly next 3 bits represent next ring to be processed.
647	eg: value of _rx_ring_pri_map = 0x0000 003A means
648	ring #2 would be processed first and #7 would be processed next
649	*/	606	*/
650	u32 _rx_ring_pri_map;	607	tx_curr_put_info_t tx_curr_put_info;
651		608
652	/* tx side stuff */	609	/*
653	void txd_list_mem; / orignal pointer to allocated mem */	610	* Current offset within tx FIFO from where the driver would start freeing
654	dma_addr_t txd_list_mem_phy;	611	* the buffers
655	u32 txd_list_mem_sz;	612	*/
		613	tx_curr_get_info_t tx_curr_get_info;
656		614
		615	nic_t *nic;
		616	}fifo_info_t;
		617
		618	/* Infomation related to the Tx and Rx FIFOs and Rings of Xena
		619	* is maintained in this structure.
		620	*/
		621	typedef struct mac_info {
		622	/* tx side stuff */
657	/* logical pointer of start of each Tx FIFO */	623	/* logical pointer of start of each Tx FIFO */
658	TxFIFO_element_t *tx_FIFO_start[MAX_TX_FIFOS];	624	TxFIFO_element_t __iomem *tx_FIFO_start[MAX_TX_FIFOS];
659		625
660	/* logical pointer of start of TxDL which corresponds to each Tx FIFO */	626	/* Fifo specific structure */
661	TxD_t *txdl_start[MAX_TX_FIFOS];	627	fifo_info_t fifos[MAX_TX_FIFOS];
662		628
663	/* Same as txdl_start but phy addr */	629	/* Save virtual address of TxD page with zero DMA addr(if any) */
664	dma_addr_t txdl_start_phy[MAX_TX_FIFOS];	630	void *zerodma_virt_addr;
665		631
666	/* Current offset within tx_FIFO_start, where driver would write new Tx frame*/	632	/* rx side stuff */
667	tx_curr_put_info_t tx_curr_put_info[MAX_TX_FIFOS];	633	/* Ring specific structure */
668	tx_curr_get_info_t tx_curr_get_info[MAX_TX_FIFOS];	634	ring_info_t rings[MAX_RX_RINGS];
669		635
670	u16 txdl_len; /* length of a TxDL, same for all */	636	u16 rmac_pause_time;
		637	u16 mc_pause_threshold_q0q3;
		638	u16 mc_pause_threshold_q4q7;
671		639
672	void stats_mem; / orignal pointer to allocated mem */	640	void stats_mem; / orignal pointer to allocated mem */
673	dma_addr_t stats_mem_phy; /* Physical address of the stat block */	641	dma_addr_t stats_mem_phy; /* Physical address of the stat block */
Lines 681-692 typedef struct { Link Here
681	int usage_cnt;	649	int usage_cnt;
682	} usr_addr_t;	650	} usr_addr_t;
683		651
684	/* Structure that holds the Phy and virt addresses of the Blocks */
685	typedef struct rx_block_info {
686	RxD_t *block_virt_addr;
687	dma_addr_t block_dma_addr;
688	} rx_block_info_t;
689
690	/* Default Tunable parameters of the NIC. */	652	/* Default Tunable parameters of the NIC. */
691	#define DEFAULT_FIFO_LEN 4096	653	#define DEFAULT_FIFO_LEN 4096
692	#define SMALL_RXD_CNT 30 * (MAX_RXDS_PER_BLOCK+1)	654	#define SMALL_RXD_CNT 30 * (MAX_RXDS_PER_BLOCK+1)
Lines 695-701 typedef struct rx_block_info { Link Here
695	#define LARGE_BLK_CNT 100	657	#define LARGE_BLK_CNT 100
696		658
697	/* Structure representing one instance of the NIC */	659	/* Structure representing one instance of the NIC */
698	typedef struct s2io_nic {	660	struct s2io_nic {
		661	#ifdef CONFIG_S2IO_NAPI
		662	/*
		663	* Count of packets to be processed in a given iteration, it will be indicated
		664	* by the quota field of the device structure when NAPI is enabled.
		665	*/
		666	int pkts_to_process;
		667	#endif
		668	struct net_device *dev;
		669	mac_info_t mac_control;
		670	struct config_param config;
		671	struct pci_dev *pdev;
		672	void __iomem *bar0;
		673	void __iomem *bar1;
699	#define MAX_MAC_SUPPORTED 16	674	#define MAX_MAC_SUPPORTED 16
700	#define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED	675	#define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED
701		676
Lines 703-736 typedef struct s2io_nic { Link Here
703	macaddr_t pre_mac_addr[MAX_MAC_SUPPORTED];	678	macaddr_t pre_mac_addr[MAX_MAC_SUPPORTED];
704		679
705	struct net_device_stats stats;	680	struct net_device_stats stats;
706	caddr_t bar0;
707	caddr_t bar1;
708	struct config_param config;
709	mac_info_t mac_control;
710	int high_dma_flag;	681	int high_dma_flag;
711	int device_close_flag;	682	int device_close_flag;
712	int device_enabled_once;	683	int device_enabled_once;
713		684
714	char name[32];	685	char name[50];
715	struct tasklet_struct task;	686	struct tasklet_struct task;
716	atomic_t tasklet_status;	687	volatile unsigned long tasklet_status;
717	struct timer_list timer;	688
718	struct net_device *dev;	689	/* Timer that handles I/O errors/exceptions */
719	struct pci_dev *pdev;	690	struct timer_list alarm_timer;
720		691
721	u16 vendor_id;	692	/* Space to back up the PCI config space */
722	u16 device_id;
723	u16 ccmd;
724	u32 cbar0_1;
725	u32 cbar0_2;
726	u32 cbar1_1;
727	u32 cbar1_2;
728	u32 cirq;
729	u8 cache_line;
730	u32 rom_expansion;
731	u16 pcix_cmd;
732	u32 config_space[256 / sizeof(u32)];	693	u32 config_space[256 / sizeof(u32)];
733	u32 irq;	694
734	atomic_t rx_bufs_left[MAX_RX_RINGS];	695	atomic_t rx_bufs_left[MAX_RX_RINGS];
735		696
736	spinlock_t tx_lock;	697	spinlock_t tx_lock;
Lines 755-781 typedef struct s2io_nic { Link Here
755	u16 tx_err_count;	716	u16 tx_err_count;
756	u16 rx_err_count;	717	u16 rx_err_count;
757		718
758	#ifndef CONFIG_S2IO_NAPI
759	/* Index to the absolute position of the put pointer of Rx ring. */
760	int put_pos;
761	#endif
762
763	/*
764	* Place holders for the virtual and physical addresses of
765	* all the Rx Blocks
766	*/
767	rx_block_info_t rx_blocks[MAX_RX_RINGS][MAX_RX_BLOCKS_PER_RING];
768	int block_count[MAX_RX_RINGS];
769	int pkt_cnt[MAX_RX_RINGS];
770
771	/* Place holder of all the TX List's Phy and Virt addresses. */
772	list_info_hold_t *list_info[MAX_TX_FIFOS];
773
774	/* Id timer, used to blink NIC to physically identify NIC. */	719	/* Id timer, used to blink NIC to physically identify NIC. */
775	struct timer_list id_timer;	720	struct timer_list id_timer;
776		721
777	/* Restart timer, used to restart NIC if the device is stuck and	722	/* Restart timer, used to restart NIC if the device is stuck and
778	* a schedule task that will set the correct Link state once the	723	* a schedule task that will set the correct Link state once the
779	* NIC's PHY has stabilized after a state change.	724	* NIC's PHY has stabilized after a state change.
780	*/	725	*/
781	#ifdef INIT_TQUEUE	726	#ifdef INIT_TQUEUE
Lines 786-797 typedef struct s2io_nic { Link Here
786	struct work_struct set_link_task;	731	struct work_struct set_link_task;
787	#endif	732	#endif
788		733
789	/* Flag that can be used to turn on or turn off the Rx checksum	734	/* Flag that can be used to turn on or turn off the Rx checksum
790	* offload feature.	735	* offload feature.
791	*/	736	*/
792	int rx_csum;	737	int rx_csum;
793		738
794	/* after blink, the adapter must be restored with original	739	/* after blink, the adapter must be restored with original
795	* values.	740	* values.
796	*/	741	*/
797	u64 adapt_ctrl_org;	742	u64 adapt_ctrl_org;
Lines 801-828 typedef struct s2io_nic { Link Here
801	#define LINK_DOWN 1	746	#define LINK_DOWN 1
802	#define LINK_UP 2	747	#define LINK_UP 2
803		748
804	#ifdef CONFIG_2BUFF_MODE
805	/* Buffer Address store. */
806	buffAdd_t **ba[MAX_RX_RINGS];
807	#endif
808	int task_flag;	749	int task_flag;
809	#ifdef SNMP_SUPPORT	750	#define CARD_DOWN 1
810	char cName[20];	751	#define CARD_UP 2
811	int nMemorySize;	752	atomic_t card_state;
812	int nLinkStatus;	753	volatile unsigned long link_state;
813	int nFeature;	754	struct vlan_group *vlgrp;
814	char cVersion[20];	755	#define XFRAME_I_DEVICE 1
815	long lDate;	756	#define XFRAME_II_DEVICE 2
816	#endif	757	u8 device_type;
817		758
818	} nic_t;	759	spinlock_t rx_lock;
		760	atomic_t isr_cnt;
		761	};
819		762
820	#define RESET_ERROR 1;	763	#define RESET_ERROR 1;
821	#define CMD_ERROR 2;	764	#define CMD_ERROR 2;
822		765
823	/* OS related system calls */	766	/* OS related system calls */
824	#ifndef readq	767	#ifndef readq
825	static inline u64 readq(void *addr)	768	static inline u64 readq(void __iomem *addr)
826	{	769	{
827	u64 ret = 0;	770	u64 ret = 0;
828	ret = readl(addr + 4);	771	ret = readl(addr + 4);
Lines 834-861 static inline u64 readq(void *addr) Link Here
834	#endif	777	#endif
835		778
836	#ifndef writeq	779	#ifndef writeq
837	static inline void writeq(u64 val, void *addr)	780	static inline void writeq(u64 val, void __iomem *addr)
838	{	781	{
839	writel((u32) (val), addr);	782	writel((u32) (val), addr);
840	writel((u32) (val >> 32), (addr + 4));	783	writel((u32) (val >> 32), (addr + 4));
841	}	784	}
842		785
843	/* In 32 bit modes, some registers have to be written in a	786	/* In 32 bit modes, some registers have to be written in a
844	* particular order to expect correct hardware operation. The	787	* particular order to expect correct hardware operation. The
845	* macro SPECIAL_REG_WRITE is used to perform such ordered	788	* macro SPECIAL_REG_WRITE is used to perform such ordered
846	* writes. Defines UF (Upper First) and LF (Lower First) will	789	* writes. Defines UF (Upper First) and LF (Lower First) will
847	* be used to specify the required write order.	790	* be used to specify the required write order.
848	*/	791	*/
849	#define UF 1	792	#define UF 1
850	#define LF 2	793	#define LF 2
851	#define SPECIAL_REG_WRITE(val, addr, order) \	794	static inline void SPECIAL_REG_WRITE(u64 val, void __iomem *addr, int order)
852	if (order == LF) { \	795	{
853	writel((u32) (val), addr); \	796	if (order == LF) {
854	writel((u32) (val >> 32), (addr + 4)); \	797	writel((u32) (val), addr);
855	} else { \	798	writel((u32) (val >> 32), (addr + 4));
856	writel((u32) (val >> 32), (addr + 4)); \	799	} else {
857	writel((u32) (val), addr); \	800	writel((u32) (val >> 32), (addr + 4));
858	}	801	writel((u32) (val), addr);
		802	}
		803	}
859	#else	804	#else
860	#define SPECIAL_REG_WRITE(val, addr, dummy) writeq(val, addr)	805	#define SPECIAL_REG_WRITE(val, addr, dummy) writeq(val, addr)
861	#endif	806	#endif
Lines 917-922 static inline void writeq(u64 val, void Link Here
917	#define PCC_FB_ECC_ERR vBIT(0xff, 16, 8) /* Interrupt to indicate	862	#define PCC_FB_ECC_ERR vBIT(0xff, 16, 8) /* Interrupt to indicate
918	PCC_FB_ECC Error. */	863	PCC_FB_ECC Error. */
919		864
		865	#define RXD_GET_VLAN_TAG(Control_2) (u16)(Control_2 & MASK_VLAN_TAG)
920	/*	866	/*
921	* Prototype declaration.	867	* Prototype declaration.
922	*/	868	*/
Lines 926-935 static void __devexit s2io_rem_nic(struc Link Here
926	static int init_shared_mem(struct s2io_nic *sp);	872	static int init_shared_mem(struct s2io_nic *sp);
927	static void free_shared_mem(struct s2io_nic *sp);	873	static void free_shared_mem(struct s2io_nic *sp);
928	static int init_nic(struct s2io_nic *nic);	874	static int init_nic(struct s2io_nic *nic);
929	#ifndef CONFIG_S2IO_NAPI	875	static void rx_intr_handler(ring_info_t *ring_data);
930	static void rx_intr_handler(struct s2io_nic *sp);	876	static void tx_intr_handler(fifo_info_t *fifo_data);
931	#endif
932	static void tx_intr_handler(struct s2io_nic *sp);
933	static void alarm_intr_handler(struct s2io_nic *sp);	877	static void alarm_intr_handler(struct s2io_nic *sp);
934		878
935	static int s2io_starter(void);	879	static int s2io_starter(void);
Lines 937-1021 void s2io_closer(void); Link Here
937	static void s2io_tx_watchdog(struct net_device *dev);	881	static void s2io_tx_watchdog(struct net_device *dev);
938	static void s2io_tasklet(unsigned long dev_addr);	882	static void s2io_tasklet(unsigned long dev_addr);
939	static void s2io_set_multicast(struct net_device *dev);	883	static void s2io_set_multicast(struct net_device *dev);
940	#ifndef CONFIG_2BUFF_MODE	884	static int rx_osm_handler(ring_info_t ring_data, RxD_t rxdp);
941	static int rx_osm_handler(nic_t * sp, u16 len, RxD_t * rxdp, int ring_no);
942	#else
943	static int rx_osm_handler(nic_t * sp, RxD_t * rxdp, int ring_no,
944	buffAdd_t * ba);
945	#endif
946	void s2io_link(nic_t * sp, int link);	885	void s2io_link(nic_t * sp, int link);
947	void s2io_reset(nic_t * sp);	886	void s2io_reset(nic_t * sp);
948	#ifdef CONFIG_S2IO_NAPI	887	#if defined(CONFIG_S2IO_NAPI)
949	static int s2io_poll(struct net_device dev, int budget);	888	static int s2io_poll(struct net_device dev, int budget);
950	#endif	889	#endif
951	static void s2io_init_pci(nic_t * sp);	890	static void s2io_init_pci(nic_t * sp);
952	int s2io_set_mac_addr(struct net_device dev, u8 addr);	891	int s2io_set_mac_addr(struct net_device dev, u8 addr);
		892	static void s2io_alarm_handle(unsigned long data);
953	static irqreturn_t s2io_isr(int irq, void dev_id, struct pt_regs regs);	893	static irqreturn_t s2io_isr(int irq, void dev_id, struct pt_regs regs);
954	static int verify_xena_quiescence(u64 val64, int flag);	894	static int verify_xena_quiescence(nic_t *sp, u64 val64, int flag);
955	int verify_load_parm(void);
956	#ifdef SET_ETHTOOL_OPS
957	static struct ethtool_ops netdev_ethtool_ops;	895	static struct ethtool_ops netdev_ethtool_ops;
958	#endif
959	static void s2io_set_link(unsigned long data);	896	static void s2io_set_link(unsigned long data);
960		897	int s2io_set_swapper(nic_t * sp);
961	#ifdef SNMP_SUPPORT	898	static void s2io_card_down(nic_t *nic);
962		899	static int s2io_card_up(nic_t *nic);
963	#define S2IODIRNAME "S2IO"	900	int get_xena_rev_id(struct pci_dev *pdev);
964	#define BDFILENAME "BDInfo"
965	#define PADAPFILENAME "PhyAdap"
966	#define ERROR_PROC_DIR -20
967	#define ERROR_PROC_ENTRY -21
968
969	struct stDrvData {
970	struct stBaseDrv *pBaseDrv;
971	};
972
973	struct stPhyAdap {
974	int m_nIndex;
975	char m_cName[20];
976	};
977	struct stBaseDrv {
978	char m_cName[21];
979	int m_nStatus;
980	char m_cVersion[21];
981	int m_nFeature;
982	int m_nMemorySize;
983	char m_cDate[21];
984	int m_nPhyCnt;
985	char m_cPhyIndex[21];
986	struct stPhyAdap m_stPhyAdap[5];
987	};
988
989	struct stPhyData {
990	int m_nIndex;
991	unsigned char m_cDesc[20];
992	int m_nMode;
993	int m_nType;
994	char m_cSpeed[20];
995	unsigned char m_cPMAC[20];
996	unsigned char m_cCMAC[20];
997	int m_nLinkStatus;
998	int m_nPCISlot;
999	int m_nPCIBus;
1000	int m_nIRQ;
1001	int m_nCollision;
1002	int m_nMulticast;
1003
1004	int m_nRxBytes;
1005	int m_nRxDropped;
1006	int m_nRxErrors;
1007	int m_nRxPackets;
1008	int m_nTxBytes;
1009	int m_nTxDropped;
1010	int m_nTxErrors;
1011	int m_nTxPackets;
1012
1013
1014	};
1015
1016	static int s2io_bdsnmp_init(struct net_device *dev);
1017	static void s2io_bdsnmp_rem(struct net_device *dev);
1018	#endif
1019
1020
1021	#endif /* _S2IO_H */	901	#endif /* _S2IO_H */

Lines 1912-1917 Link Here

(-)old/include/linux/pci_ids.h (+2 lines)
1912	#define PCI_VENDOR_ID_S2IO 0x17d5	1912	#define PCI_VENDOR_ID_S2IO 0x17d5
1913	#define PCI_DEVICE_ID_S2IO_WIN 0x5731	1913	#define PCI_DEVICE_ID_S2IO_WIN 0x5731
1914	#define PCI_DEVICE_ID_S2IO_UNI 0x5831	1914	#define PCI_DEVICE_ID_S2IO_UNI 0x5831
		1915	#define PCI_DEVICE_ID_HERC_WIN 0x5732
		1916	#define PCI_DEVICE_ID_HERC_UNI 0x5832
1915		1917
1916	#define PCI_VENDOR_ID_ARC 0x192E	1918	#define PCI_VENDOR_ID_ARC 0x192E
1917	#define PCI_DEVICE_ID_ARC_EHCI 0x0101	1919	#define PCI_DEVICE_ID_ARC_EHCI 0x0101

Return to bug 116305

Lines 1-6 Link Here

(-)old/drivers/net/s2io-regs.h (-24 / +68 lines)
1	/************************************************************************	1	/************************************************************************
2	* regs.h: A Linux PCI-X Ethernet driver for S2IO 10GbE Server NIC	2	* regs.h: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
3	* Copyright 2002 Raghavendra Koushik (raghavendra.koushik@s2io.com)	3	* Copyright(c) 2002-2005 Neterion Inc.
4		4
5	* This software may be used and distributed according to the terms of	5	* This software may be used and distributed according to the terms of
6	* the GNU General Public License (GPL), incorporated herein by reference.	6	* the GNU General Public License (GPL), incorporated herein by reference.
Lines 62-67 typedef struct _XENA_dev_config { Link Here
62	#define ADAPTER_STATUS_RMAC_REMOTE_FAULT BIT(6)	62	#define ADAPTER_STATUS_RMAC_REMOTE_FAULT BIT(6)
63	#define ADAPTER_STATUS_RMAC_LOCAL_FAULT BIT(7)	63	#define ADAPTER_STATUS_RMAC_LOCAL_FAULT BIT(7)
64	#define ADAPTER_STATUS_RMAC_PCC_IDLE vBIT(0xFF,8,8)	64	#define ADAPTER_STATUS_RMAC_PCC_IDLE vBIT(0xFF,8,8)
		65	#define ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE vBIT(0x0F,8,8)
65	#define ADAPTER_STATUS_RC_PRC_QUIESCENT vBIT(0xFF,16,8)	66	#define ADAPTER_STATUS_RC_PRC_QUIESCENT vBIT(0xFF,16,8)
66	#define ADAPTER_STATUS_MC_DRAM_READY BIT(24)	67	#define ADAPTER_STATUS_MC_DRAM_READY BIT(24)
67	#define ADAPTER_STATUS_MC_QUEUES_READY BIT(25)	68	#define ADAPTER_STATUS_MC_QUEUES_READY BIT(25)
Lines 77-97 typedef struct _XENA_dev_config { Link Here
77	#define ADAPTER_ECC_EN BIT(55)	78	#define ADAPTER_ECC_EN BIT(55)
78		79
79	u64 serr_source;	80	u64 serr_source;
80	#define SERR_SOURCE_PIC BIT(0)	81	#define SERR_SOURCE_PIC BIT(0)
81	#define SERR_SOURCE_TXDMA BIT(1)	82	#define SERR_SOURCE_TXDMA BIT(1)
82	#define SERR_SOURCE_RXDMA BIT(2)	83	#define SERR_SOURCE_RXDMA BIT(2)
83	#define SERR_SOURCE_MAC BIT(3)	84	#define SERR_SOURCE_MAC BIT(3)
84	#define SERR_SOURCE_MC BIT(4)	85	#define SERR_SOURCE_MC BIT(4)
85	#define SERR_SOURCE_XGXS BIT(5)	86	#define SERR_SOURCE_XGXS BIT(5)
86	#define SERR_SOURCE_ANY (SERR_SOURCE_PIC \| \	87	#define SERR_SOURCE_ANY (SERR_SOURCE_PIC \| \
87	SERR_SOURCE_TXDMA \| \	88	SERR_SOURCE_TXDMA \| \
88	SERR_SOURCE_RXDMA \| \	89	SERR_SOURCE_RXDMA \| \
89	SERR_SOURCE_MAC \| \	90	SERR_SOURCE_MAC \| \
90	SERR_SOURCE_MC \| \	91	SERR_SOURCE_MC \| \
91	SERR_SOURCE_XGXS)	92	SERR_SOURCE_XGXS)
		93
		94	u64 pci_mode;
		95	#define GET_PCI_MODE(val) ((val & vBIT(0xF, 0, 4)) >> 60)
		96	#define PCI_MODE_PCI_33 0
		97	#define PCI_MODE_PCI_66 0x1
		98	#define PCI_MODE_PCIX_M1_66 0x2
		99	#define PCI_MODE_PCIX_M1_100 0x3
		100	#define PCI_MODE_PCIX_M1_133 0x4
		101	#define PCI_MODE_PCIX_M2_66 0x5
		102	#define PCI_MODE_PCIX_M2_100 0x6
		103	#define PCI_MODE_PCIX_M2_133 0x7
		104	#define PCI_MODE_UNSUPPORTED BIT(0)
		105	#define PCI_MODE_32_BITS BIT(8)
		106	#define PCI_MODE_UNKNOWN_MODE BIT(9)
92		107
93		108	u8 unused_0[0x800 - 0x128];
94	u8 unused_0[0x800 - 0x120];
95		109
96	/* PCI-X Controller registers */	110	/* PCI-X Controller registers */
97	u64 pic_int_status;	111	u64 pic_int_status;
Lines 153-159 typedef struct _XENA_dev_config { Link Here
153	u8 unused4[0x08];	167	u8 unused4[0x08];
154		168
155	u64 gpio_int_reg;	169	u64 gpio_int_reg;
		170	#define GPIO_INT_REG_LINK_DOWN BIT(1)
		171	#define GPIO_INT_REG_LINK_UP BIT(2)
156	u64 gpio_int_mask;	172	u64 gpio_int_mask;
		173	#define GPIO_INT_MASK_LINK_DOWN BIT(1)
		174	#define GPIO_INT_MASK_LINK_UP BIT(2)
157	u64 gpio_alarms;	175	u64 gpio_alarms;
158		176
159	u8 unused5[0x38];	177	u8 unused5[0x38];
Lines 223-241 typedef struct _XENA_dev_config { Link Here
223	u64 xmsi_data;	241	u64 xmsi_data;
224		242
225	u64 rx_mat;	243	u64 rx_mat;
		244	#define RX_MAT_SET(ring, msi) vBIT(msi, (8 * ring), 8)
226		245
227	u8 unused6[0x8];	246	u8 unused6[0x8];
228		247
229	u64 tx_mat0_7;	248	u64 tx_mat0_n[0x8];
230	u64 tx_mat8_15;	249	#define TX_MAT_SET(fifo, msi) vBIT(msi, (8 * fifo), 8)
231	u64 tx_mat16_23;
232	u64 tx_mat24_31;
233	u64 tx_mat32_39;
234	u64 tx_mat40_47;
235	u64 tx_mat48_55;
236	u64 tx_mat56_63;
237		250
238	u8 unused_1[0x10];	251	u8 unused_1[0x8];
		252	u64 stat_byte_cnt;
		253	#define STAT_BC(n) vBIT(n,4,12)
239		254
240	/* Automated statistics collection */	255	/* Automated statistics collection */
241	u64 stat_cfg;	256	u64 stat_cfg;
Lines 246-251 typedef struct _XENA_dev_config { Link Here
246	#define STAT_TRSF_PER(n) TBD	261	#define STAT_TRSF_PER(n) TBD
247	#define PER_SEC 0x208d5	262	#define PER_SEC 0x208d5
248	#define SET_UPDT_PERIOD(n) vBIT((PER_SEC*n),32,32)	263	#define SET_UPDT_PERIOD(n) vBIT((PER_SEC*n),32,32)
		264	#define SET_UPDT_CLICKS(val) vBIT(val, 32, 32)
249		265
250	u64 stat_addr;	266	u64 stat_addr;
251		267
Lines 267-274 typedef struct _XENA_dev_config { Link Here
267		283
268	u64 gpio_control;	284	u64 gpio_control;
269	#define GPIO_CTRL_GPIO_0 BIT(8)	285	#define GPIO_CTRL_GPIO_0 BIT(8)
		286	u64 misc_control;
		287	#define MISC_LINK_STABILITY_PRD(val) vBIT(val,29,3)
		288
		289	u8 unused7_1[0x240 - 0x208];
		290
		291	u64 wreq_split_mask;
		292	#define WREQ_SPLIT_MASK_SET_MASK(val) vBIT(val, 52, 12)
270		293
271	u8 unused7[0x600];	294	u8 unused7_2[0x800 - 0x248];
272		295
273	/* TxDMA registers */	296	/* TxDMA registers */
274	u64 txdma_int_status;	297	u64 txdma_int_status;
Lines 290-295 typedef struct _XENA_dev_config { Link Here
290		313
291	u64 pcc_err_reg;	314	u64 pcc_err_reg;
292	#define PCC_FB_ECC_DB_ERR vBIT(0xFF, 16, 8)	315	#define PCC_FB_ECC_DB_ERR vBIT(0xFF, 16, 8)
		316	#define PCC_ENABLE_FOUR vBIT(0x0F,0,8)
293		317
294	u64 pcc_err_mask;	318	u64 pcc_err_mask;
295	u64 pcc_err_alarm;	319	u64 pcc_err_alarm;
Lines 468-473 typedef struct _XENA_dev_config { Link Here
468	#define PRC_CTRL_NO_SNOOP (BIT(22)\|BIT(23))	492	#define PRC_CTRL_NO_SNOOP (BIT(22)\|BIT(23))
469	#define PRC_CTRL_NO_SNOOP_DESC BIT(22)	493	#define PRC_CTRL_NO_SNOOP_DESC BIT(22)
470	#define PRC_CTRL_NO_SNOOP_BUFF BIT(23)	494	#define PRC_CTRL_NO_SNOOP_BUFF BIT(23)
		495	#define PRC_CTRL_BIMODAL_INTERRUPT BIT(37)
471	#define PRC_CTRL_RXD_BACKOFF_INTERVAL(val) vBIT(val,40,24)	496	#define PRC_CTRL_RXD_BACKOFF_INTERVAL(val) vBIT(val,40,24)
472		497
473	u64 prc_alarm_action;	498	u64 prc_alarm_action;
Lines 688-696 typedef struct _XENA_dev_config { Link Here
688	u64 mc_err_reg;	713	u64 mc_err_reg;
689	#define MC_ERR_REG_ECC_DB_ERR_L BIT(14)	714	#define MC_ERR_REG_ECC_DB_ERR_L BIT(14)
690	#define MC_ERR_REG_ECC_DB_ERR_U BIT(15)	715	#define MC_ERR_REG_ECC_DB_ERR_U BIT(15)
		716	#define MC_ERR_REG_MIRI_ECC_DB_ERR_0 BIT(18)
		717	#define MC_ERR_REG_MIRI_ECC_DB_ERR_1 BIT(20)
691	#define MC_ERR_REG_MIRI_CRI_ERR_0 BIT(22)	718	#define MC_ERR_REG_MIRI_CRI_ERR_0 BIT(22)
692	#define MC_ERR_REG_MIRI_CRI_ERR_1 BIT(23)	719	#define MC_ERR_REG_MIRI_CRI_ERR_1 BIT(23)
693	#define MC_ERR_REG_SM_ERR BIT(31)	720	#define MC_ERR_REG_SM_ERR BIT(31)
		721	#define MC_ERR_REG_ECC_ALL_SNG (BIT(2) \| BIT(3) \| BIT(4) \| BIT(5) \|\
		722	BIT(6) \| BIT(7) \| BIT(17) \| BIT(19))
		723	#define MC_ERR_REG_ECC_ALL_DBL (BIT(10) \| BIT(11) \| BIT(12) \|\
		724	BIT(13) \| BIT(14) \| BIT(15) \|\
		725	BIT(18) \| BIT(20))
694	u64 mc_err_mask;	726	u64 mc_err_mask;
695	u64 mc_err_alarm;	727	u64 mc_err_alarm;
696		728
Lines 736-742 typedef struct _XENA_dev_config { Link Here
736	u64 mc_rldram_test_d1;	768	u64 mc_rldram_test_d1;
737	u8 unused24[0x300 - 0x288];	769	u8 unused24[0x300 - 0x288];
738	u64 mc_rldram_test_d2;	770	u64 mc_rldram_test_d2;
739	u8 unused25[0x700 - 0x308];	771
		772	u8 unused24_1[0x360 - 0x308];
		773	u64 mc_rldram_ctrl;
		774	#define MC_RLDRAM_ENABLE_ODT BIT(7)
		775
		776	u8 unused24_2[0x640 - 0x368];
		777	u64 mc_rldram_ref_per_herc;
		778	#define MC_RLDRAM_SET_REF_PERIOD(val) vBIT(val, 0, 16)
		779
		780	u8 unused24_3[0x660 - 0x648];
		781	u64 mc_rldram_mrs_herc;
		782
		783	u8 unused25[0x700 - 0x668];
740	u64 mc_debug_ctrl;	784	u64 mc_debug_ctrl;
741		785
742	u8 unused26[0x3000 - 0x2f08];	786	u8 unused26[0x3000 - 0x2f08];