Attachment 49501 Details for Bug 116305

[patch] driver patch, generated on driver in SLES9 SP2

SLESSP3_2081.patch (text/plain), 253.94 KB, created by leonid grossman on 2005-09-10 02:43:18 UTC

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Creator: leonid grossman

Created: 2005-09-10 02:43:18 UTC

Size: 253.94 KB

patch

obsolete

>diff -urpN old/drivers/net/s2io-regs.h new/drivers/net/s2io-regs.h
>--- old/drivers/net/s2io-regs.h	2005-09-08 15:45:42.271721376 -0700
>+++ new/drivers/net/s2io-regs.h	2005-09-06 04:39:14.000000000 -0700
>@@ -1,6 +1,6 @@
> /************************************************************************
>- * regs.h: A Linux PCI-X Ethernet driver for S2IO 10GbE Server NIC
>- * Copyright 2002 Raghavendra Koushik (raghavendra.koushik@s2io.com)
>+ * regs.h: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
>+ * Copyright(c) 2002-2005 Neterion Inc.
> 
>  * This software may be used and distributed according to the terms of
>  * the GNU General Public License (GPL), incorporated herein by reference.
>@@ -62,6 +62,7 @@ typedef struct _XENA_dev_config {
> #define ADAPTER_STATUS_RMAC_REMOTE_FAULT   BIT(6)
> #define ADAPTER_STATUS_RMAC_LOCAL_FAULT    BIT(7)
> #define ADAPTER_STATUS_RMAC_PCC_IDLE       vBIT(0xFF,8,8)
>+#define ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE  vBIT(0x0F,8,8)
> #define ADAPTER_STATUS_RC_PRC_QUIESCENT    vBIT(0xFF,16,8)
> #define ADAPTER_STATUS_MC_DRAM_READY       BIT(24)
> #define ADAPTER_STATUS_MC_QUEUES_READY     BIT(25)
>@@ -77,21 +78,34 @@ typedef struct _XENA_dev_config {
> #define ADAPTER_ECC_EN                     BIT(55)
> 
> 	u64 serr_source;
>-#define SERR_SOURCE_PIC					BIT(0)
>-#define SERR_SOURCE_TXDMA				BIT(1)
>-#define SERR_SOURCE_RXDMA				BIT(2)
>+#define SERR_SOURCE_PIC			BIT(0)
>+#define SERR_SOURCE_TXDMA		BIT(1)
>+#define SERR_SOURCE_RXDMA		BIT(2)
> #define SERR_SOURCE_MAC                 BIT(3)
> #define SERR_SOURCE_MC                  BIT(4)
> #define SERR_SOURCE_XGXS                BIT(5)
>-#define	SERR_SOURCE_ANY					(SERR_SOURCE_PIC		| \
>-										SERR_SOURCE_TXDMA	| \
>-										SERR_SOURCE_RXDMA	| \
>-										SERR_SOURCE_MAC		| \
>-										SERR_SOURCE_MC      | \
>-										SERR_SOURCE_XGXS)
>+#define	SERR_SOURCE_ANY			(SERR_SOURCE_PIC	| \
>+					SERR_SOURCE_TXDMA	| \
>+					SERR_SOURCE_RXDMA	| \
>+					SERR_SOURCE_MAC		| \
>+					SERR_SOURCE_MC		| \
>+					SERR_SOURCE_XGXS)
>+
>+	u64 pci_mode;
>+#define	GET_PCI_MODE(val)		((val & vBIT(0xF, 0, 4)) >> 60)
>+#define	PCI_MODE_PCI_33			0
>+#define	PCI_MODE_PCI_66			0x1
>+#define	PCI_MODE_PCIX_M1_66		0x2
>+#define	PCI_MODE_PCIX_M1_100		0x3
>+#define	PCI_MODE_PCIX_M1_133		0x4
>+#define	PCI_MODE_PCIX_M2_66		0x5
>+#define	PCI_MODE_PCIX_M2_100		0x6
>+#define	PCI_MODE_PCIX_M2_133		0x7
>+#define	PCI_MODE_UNSUPPORTED		BIT(0)
>+#define	PCI_MODE_32_BITS		BIT(8)
>+#define	PCI_MODE_UNKNOWN_MODE		BIT(9)
> 
>-
>-	u8 unused_0[0x800 - 0x120];
>+	u8 unused_0[0x800 - 0x128];
> 
> /* PCI-X Controller registers */
> 	u64 pic_int_status;
>@@ -153,7 +167,11 @@ typedef struct _XENA_dev_config {
> 	u8 unused4[0x08];
> 
> 	u64 gpio_int_reg;
>+#define GPIO_INT_REG_LINK_DOWN                 BIT(1)
>+#define GPIO_INT_REG_LINK_UP                   BIT(2)
> 	u64 gpio_int_mask;
>+#define GPIO_INT_MASK_LINK_DOWN                BIT(1)
>+#define GPIO_INT_MASK_LINK_UP                  BIT(2)
> 	u64 gpio_alarms;
> 
> 	u8 unused5[0x38];
>@@ -223,19 +241,16 @@ typedef struct _XENA_dev_config {
> 	u64 xmsi_data;
> 
> 	u64 rx_mat;
>+#define RX_MAT_SET(ring, msi)			vBIT(msi, (8 * ring), 8)
> 
> 	u8 unused6[0x8];
> 
>-	u64 tx_mat0_7;
>-	u64 tx_mat8_15;
>-	u64 tx_mat16_23;
>-	u64 tx_mat24_31;
>-	u64 tx_mat32_39;
>-	u64 tx_mat40_47;
>-	u64 tx_mat48_55;
>-	u64 tx_mat56_63;
>+	u64 tx_mat0_n[0x8];
>+#define TX_MAT_SET(fifo, msi)			vBIT(msi, (8 * fifo), 8)
> 
>-	u8 unused_1[0x10];
>+	u8 unused_1[0x8];
>+	u64 stat_byte_cnt;
>+#define STAT_BC(n)                              vBIT(n,4,12)
> 
> 	/* Automated statistics collection */
> 	u64 stat_cfg;
>@@ -246,6 +261,7 @@ typedef struct _XENA_dev_config {
> #define STAT_TRSF_PER(n)           TBD
> #define	PER_SEC					   0x208d5
> #define	SET_UPDT_PERIOD(n)		   vBIT((PER_SEC*n),32,32)
>+#define	SET_UPDT_CLICKS(val)		   vBIT(val, 32, 32)
> 
> 	u64 stat_addr;
> 
>@@ -267,8 +283,15 @@ typedef struct _XENA_dev_config {
> 
> 	u64 gpio_control;
> #define GPIO_CTRL_GPIO_0		BIT(8)
>+	u64 misc_control;
>+#define MISC_LINK_STABILITY_PRD(val)   vBIT(val,29,3)
>+
>+	u8 unused7_1[0x240 - 0x208];
>+
>+	u64 wreq_split_mask;
>+#define	WREQ_SPLIT_MASK_SET_MASK(val)	vBIT(val, 52, 12)
> 
>-	u8 unused7[0x600];
>+	u8 unused7_2[0x800 - 0x248];
> 
> /* TxDMA registers */
> 	u64 txdma_int_status;
>@@ -290,6 +313,7 @@ typedef struct _XENA_dev_config {
> 
> 	u64 pcc_err_reg;
> #define PCC_FB_ECC_DB_ERR		vBIT(0xFF, 16, 8)
>+#define PCC_ENABLE_FOUR			vBIT(0x0F,0,8)
> 
> 	u64 pcc_err_mask;
> 	u64 pcc_err_alarm;
>@@ -468,6 +492,7 @@ typedef struct _XENA_dev_config {
> #define PRC_CTRL_NO_SNOOP                      (BIT(22)|BIT(23))
> #define PRC_CTRL_NO_SNOOP_DESC                 BIT(22)
> #define PRC_CTRL_NO_SNOOP_BUFF                 BIT(23)
>+#define PRC_CTRL_BIMODAL_INTERRUPT             BIT(37)
> #define PRC_CTRL_RXD_BACKOFF_INTERVAL(val)     vBIT(val,40,24)
> 
> 	u64 prc_alarm_action;
>@@ -688,9 +713,16 @@ typedef struct _XENA_dev_config {
> 	u64 mc_err_reg;
> #define MC_ERR_REG_ECC_DB_ERR_L            BIT(14)
> #define MC_ERR_REG_ECC_DB_ERR_U            BIT(15)
>+#define MC_ERR_REG_MIRI_ECC_DB_ERR_0       BIT(18)
>+#define MC_ERR_REG_MIRI_ECC_DB_ERR_1       BIT(20)
> #define MC_ERR_REG_MIRI_CRI_ERR_0          BIT(22)
> #define MC_ERR_REG_MIRI_CRI_ERR_1          BIT(23)
> #define MC_ERR_REG_SM_ERR                  BIT(31)
>+#define MC_ERR_REG_ECC_ALL_SNG		   (BIT(2) | BIT(3) | BIT(4) | BIT(5) |\
>+					    BIT(6) | BIT(7) | BIT(17) | BIT(19))
>+#define MC_ERR_REG_ECC_ALL_DBL		   (BIT(10) | BIT(11) | BIT(12) |\
>+					    BIT(13) | BIT(14) | BIT(15) |\
>+					    BIT(18) | BIT(20))
> 	u64 mc_err_mask;
> 	u64 mc_err_alarm;
> 
>@@ -736,7 +768,19 @@ typedef struct _XENA_dev_config {
> 	u64 mc_rldram_test_d1;
> 	u8 unused24[0x300 - 0x288];
> 	u64 mc_rldram_test_d2;
>-	u8 unused25[0x700 - 0x308];
>+
>+	u8 unused24_1[0x360 - 0x308];
>+	u64 mc_rldram_ctrl;
>+#define	MC_RLDRAM_ENABLE_ODT		BIT(7)
>+
>+	u8 unused24_2[0x640 - 0x368];
>+	u64 mc_rldram_ref_per_herc;
>+#define	MC_RLDRAM_SET_REF_PERIOD(val)	vBIT(val, 0, 16)
>+
>+	u8 unused24_3[0x660 - 0x648];
>+	u64 mc_rldram_mrs_herc;
>+
>+	u8 unused25[0x700 - 0x668];
> 	u64 mc_debug_ctrl;
> 
> 	u8 unused26[0x3000 - 0x2f08];
>diff -urpN old/drivers/net/s2io.c new/drivers/net/s2io.c
>--- old/drivers/net/s2io.c	2005-09-08 15:45:42.273721072 -0700
>+++ new/drivers/net/s2io.c	2005-09-09 07:19:53.767598792 -0700
>@@ -1,6 +1,6 @@
> /************************************************************************
>- * s2io.c: A Linux PCI-X Ethernet driver for S2IO 10GbE Server NIC
>- * Copyright(c) 2002-2005 S2IO Technologies
>+ * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
>+ * Copyright(c) 2002-2005 Neterion Inc.
> 
>  * This software may be used and distributed according to the terms of
>  * the GNU General Public License (GPL), incorporated herein by reference.
>@@ -11,88 +11,99 @@
>  * See the file COPYING in this distribution for more information.
>  *
>  * Credits:
>- * Jeff Garzik		: For pointing out the improper error condition 
>- *			  check in the s2io_xmit routine and also some 
>- * 			  issues in the Tx watch dog function. Also for
>- *			  patiently answering all those innumerable 
>+ * Jeff Garzik		: For pointing out the improper error condition
>+ *			  check in the s2io_xmit routine and also some
>+ *			  issues in the Tx watch dog function. Also for
>+ *			  patiently answering all those innumerable
>  *			  questions regaring the 2.6 porting issues.
>  * Stephen Hemminger	: Providing proper 2.6 porting mechanism for some
>  *			  macros available only in 2.6 Kernel.
>- * Francois Romieu	: For pointing out all code part that were 
>+ * Francois Romieu	: For pointing out all code part that were
>  *			  deprecated and also styling related comments.
>- * Grant Grundler	: For helping me get rid of some Architecture 
>+ * Grant Grundler	: For helping me get rid of some Architecture
>  *			  dependent code.
>  * Christopher Hellwig	: Some more 2.6 specific issues in the driver.
>- *			  	
>+ *
>  * The module loadable parameters that are supported by the driver and a brief
>  * explaination of all the variables.
>- * ring_num : This can be used to program the number of receive rings used 
>- * in the driver.  					
>- * frame_len: This is an array of size 8. Using this we can set the maximum 
>- * size of the received frame that can be steered into the corrsponding 
>- * receive ring.
>- * ring_len: This defines the number of descriptors each ring can have. This 
>+ * rx_ring_num : This can be used to program the number of receive rings used
>+ * in the driver.
>+ * rx_ring_sz: This defines the number of descriptors each ring can have. This
>  * is also an array of size 8.
>- * fifo_num: This defines the number of Tx FIFOs thats used int the driver.
>- * fifo_len: This too is an array of 8. Each element defines the number of 
>+ * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
>+ * tx_fifo_len: This too is an array of 8. Each element defines the number of
>  * Tx descriptors that can be associated with each corresponding FIFO.
>- * latency_timer: This input is programmed into the Latency timer register
>- * in PCI Configuration space.
>  ************************************************************************/
> 
>-#include<linux/config.h>
>-#include<linux/module.h>
>-#include<linux/types.h>
>-#include<linux/errno.h>
>-#include<linux/ioport.h>
>-#include<linux/pci.h>
>-#include<linux/kernel.h>
>-#include<linux/netdevice.h>
>-#include<linux/etherdevice.h>
>-#include<linux/skbuff.h>
>-#include<linux/init.h>
>-#include<linux/delay.h>
>-#include<linux/stddef.h>
>-#include<linux/ioctl.h>
>-#include<linux/timex.h>
>-#include<linux/sched.h>
>-#include<linux/ethtool.h>
>-#include<asm/system.h>
>-#include<asm/uaccess.h>
>-#include<linux/version.h>
>-#include<asm/io.h>
>-#include<linux/proc_fs.h>
>-#include<linux/workqueue.h>
>+#include <linux/config.h>
>+#include <linux/module.h>
>+#include <linux/types.h>
>+#include <linux/errno.h>
>+#include <linux/ioport.h>
>+#include <linux/pci.h>
>+#include <linux/dma-mapping.h>
>+#include <linux/kernel.h>
>+#include <linux/netdevice.h>
>+#include <linux/etherdevice.h>
>+#include <linux/skbuff.h>
>+#include <linux/init.h>
>+#include <linux/delay.h>
>+#include <linux/stddef.h>
>+#include <linux/ioctl.h>
>+#include <linux/timex.h>
>+#include <linux/sched.h>
>+#include <linux/ethtool.h>
>+#include <linux/version.h>
>+#include <linux/workqueue.h>
>+#include <linux/if_vlan.h>
>+#include <linux/moduleparam.h>
>+
>+#include <asm/system.h>
>+#include <asm/uaccess.h>
>+#include <asm/io.h>
> 
> /* local include */
> #include "s2io.h"
> #include "s2io-regs.h"
> 
> /* S2io Driver name & version. */
>-static char s2io_driver_name[] = "s2io";
>-static char s2io_driver_version[] = "Version 1.7.5.1";
>+static char s2io_driver_name[] = "Neterion";
>+static char s2io_driver_version[] = "Version 2.0.8.1";
>+
>+static inline int RXD_IS_UP2DT(RxD_t *rxdp)
>+{
>+	int ret;
>+
>+	ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
>+		(GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
>+
>+	return ret;
>+}
> 
>-/* 
>+/*
>  * Cards with following subsystem_id have a link state indication
>  * problem, 600B, 600C, 600D, 640B, 640C and 640D.
>  * macro below identifies these cards given the subsystem_id.
>  */
>-#define CARDS_WITH_FAULTY_LINK_INDICATORS(subid) \
>-		(((subid >= 0x600B) && (subid <= 0x600D)) || \
>-		 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0
>+#define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
>+	(dev_type == XFRAME_I_DEVICE) ?			\
>+		((((subid >= 0x600B) && (subid <= 0x600D)) || \
>+		 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
> 
> #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
> 				      ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
>-#define TASKLET_IN_USE test_and_set_bit(0, \
>-				(unsigned long *)(&sp->tasklet_status))
>+#define TASKLET_IN_USE test_and_set_bit(0, (&sp->tasklet_status))
> #define PANIC	1
> #define LOW	2
> static inline int rx_buffer_level(nic_t * sp, int rxb_size, int ring)
> {
> 	int level = 0;
>-	if ((sp->pkt_cnt[ring] - rxb_size) > 16) {
>+	mac_info_t *mac_control;
>+
>+	mac_control = &sp->mac_control;
>+	if ((mac_control->rings[ring].pkt_cnt - rxb_size) > 16) {
> 		level = LOW;
>-		if ((sp->pkt_cnt[ring] - rxb_size) < MAX_RXDS_PER_BLOCK) {
>+		if (rxb_size <= MAX_RXDS_PER_BLOCK) {
> 			level = PANIC;
> 		}
> 	}
>@@ -149,6 +160,9 @@ static char ethtool_stats_keys[][ETH_GST
> 	{"rmac_pause_cnt"},
> 	{"rmac_accepted_ip"},
> 	{"rmac_err_tcp"},
>+	{"\n DRIVER STATISTICS"},
>+	{"single_bit_ecc_errs"},
>+	{"double_bit_ecc_errs"},
> };
> 
> #define S2IO_STAT_LEN sizeof(ethtool_stats_keys)/ ETH_GSTRING_LEN
>@@ -157,16 +171,66 @@ static char ethtool_stats_keys[][ETH_GST
> #define S2IO_TEST_LEN	sizeof(s2io_gstrings) / ETH_GSTRING_LEN
> #define S2IO_STRINGS_LEN	S2IO_TEST_LEN * ETH_GSTRING_LEN
> 
>+#define S2IO_TIMER_CONF(timer, handle, arg, exp)		\
>+			init_timer(&timer);			\
>+			timer.function = handle;		\
>+			timer.data = (unsigned long) arg;	\
>+			mod_timer(&timer, (jiffies + exp))	\
>+
>+/* Add the vlan */
>+static void s2io_vlan_rx_register(struct net_device *dev,
>+					struct vlan_group *grp)
>+{
>+	nic_t *nic = dev->priv;
>+	unsigned long flags;
>+
>+	spin_lock_irqsave(&nic->tx_lock, flags);
>+	nic->vlgrp = grp;
>+	spin_unlock_irqrestore(&nic->tx_lock, flags);
>+}
>+
>+/* Unregister the vlan */
>+static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned long vid)
>+{
>+	nic_t *nic = dev->priv;
>+	unsigned long flags;
>+
>+	spin_lock_irqsave(&nic->tx_lock, flags);
>+	if (nic->vlgrp)
>+		nic->vlgrp->vlan_devices[vid] = NULL;
>+	spin_unlock_irqrestore(&nic->tx_lock, flags);
>+}
> 
>-/* 
>- * Constants to be programmed into the Xena's registers to configure
>+/*
>+ * Constants to be programmed into the Xena's registers, to configure
>  * the XAUI.
>  */
> 
> #define SWITCH_SIGN	0xA5A5A5A5A5A5A5A5ULL
> #define	END_SIGN	0x0
> 
>-static u64 default_mdio_cfg[] = {
>+static u64 herc_act_dtx_cfg[] = {
>+	/* Set address */
>+	0x8000051536750000ULL, 0x80000515367500E0ULL,
>+	/* Write data */
>+	0x8000051536750004ULL, 0x80000515367500E4ULL,
>+	/* Set address */
>+	0x80010515003F0000ULL, 0x80010515003F00E0ULL,
>+	/* Write data */
>+	0x80010515003F0004ULL, 0x80010515003F00E4ULL,
>+	/* Set address */
>+	0x801205150D440000ULL, 0x801205150D4400E0ULL,
>+	/* Write data */
>+	0x801205150D440004ULL, 0x801205150D4400E4ULL,
>+	/* Set address */
>+	0x80020515F2100000ULL, 0x80020515F21000E0ULL,
>+	/* Write data */
>+	0x80020515F2100004ULL, 0x80020515F21000E4ULL,
>+	/* Done */
>+	END_SIGN
>+};
>+
>+static u64 xena_mdio_cfg[] = {
> 	/* Reset PMA PLL */
> 	0xC001010000000000ULL, 0xC0010100000000E0ULL,
> 	0xC0010100008000E4ULL,
>@@ -176,7 +240,7 @@ static u64 default_mdio_cfg[] = {
> 	END_SIGN
> };
> 
>-static u64 default_dtx_cfg[] = {
>+static u64 xena_dtx_cfg[] = {
> 	0x8000051500000000ULL, 0x80000515000000E0ULL,
> 	0x80000515D93500E4ULL, 0x8001051500000000ULL,
> 	0x80010515000000E0ULL, 0x80010515001E00E4ULL,
>@@ -200,8 +264,7 @@ static u64 default_dtx_cfg[] = {
> 	END_SIGN
> };
> 
>-
>-/* 
>+/*
>  * Constants for Fixing the MacAddress problem seen mostly on
>  * Alpha machines.
>  */
>@@ -224,96 +287,61 @@ static u64 fix_mac[] = {
> };
> 
> /* Module Loadable parameters. */
>-static u32 frame_len[MAX_RX_RINGS];
>-static u32 rx_prio;
>-static u32 tx_prio;
>-
>-static unsigned int lso_enable = 1;
>-#ifndef CONFIG_S2IO_NAPI
>-static unsigned int indicate_max_pkts = 0;
>-#endif
>-static unsigned int cksum_offload_enable = 1;
>-static unsigned int TxFifoNum = 1;
>-static unsigned int TxFIFOLen_0 = DEFAULT_FIFO_LEN;
>-static unsigned int TxFIFOLen_1 = 0;
>-static unsigned int TxFIFOLen_2 = 0;
>-static unsigned int TxFIFOLen_3 = 0;
>-static unsigned int TxFIFOLen_4 = 0;
>-static unsigned int TxFIFOLen_5 = 0;
>-static unsigned int TxFIFOLen_6 = 0;
>-static unsigned int TxFIFOLen_7 = 0;
>-static unsigned int MaxTxDs = MAX_SKB_FRAGS;
>-static unsigned int RxRingNum = 1;
>-static unsigned int RxRingSz_0 = SMALL_BLK_CNT;
>-static unsigned int RxRingSz_1 = 0;
>-static unsigned int RxRingSz_2 = 0;
>-static unsigned int RxRingSz_3 = 0;
>-static unsigned int RxRingSz_4 = 0;
>-static unsigned int RxRingSz_5 = 0;
>-static unsigned int RxRingSz_6 = 0;
>-static unsigned int RxRingSz_7 = 0;
>-static unsigned int Stats_refresh_time = 4;
>+static unsigned int tx_fifo_num = 1;
>+static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
>+    {[0 ...(MAX_TX_FIFOS - 1)] = 0 };
>+static unsigned int rx_ring_num = 1;
>+static unsigned int rx_ring_sz[MAX_RX_RINGS] =
>+    {[0 ...(MAX_RX_RINGS - 1)] = 0 };
>+static unsigned int rts_frm_len[MAX_RX_RINGS] =
>+    {[0 ...(MAX_RX_RINGS - 1)] = 0 };
>+static unsigned int use_continuous_tx_intrs = 1;
> static unsigned int rmac_pause_time = 65535;
> static unsigned int mc_pause_threshold_q0q3 = 187;
> static unsigned int mc_pause_threshold_q4q7 = 187;
>-static unsigned int shared_splits = 0;
>-#if defined(__ia64__)
>-static unsigned int max_splits_trans = XENA_THREE_SPLIT_TRANSACTION;
>-#else
>-static unsigned int max_splits_trans = XENA_TWO_SPLIT_TRANSACTION;
>-#endif
>+static unsigned int shared_splits;
> static unsigned int tmac_util_period = 5;
> static unsigned int rmac_util_period = 5;
>-static unsigned int tx_timer_val = 0xFFF;
>-static unsigned int tx_utilz_periodic = 1;
>-static unsigned int rx_timer_val = 0xFFF;
>-static unsigned int rx_utilz_periodic = 1;
>-static unsigned int tx_urange_a = 0xA;
>-static unsigned int tx_ufc_a = 0x10;
>-static unsigned int tx_urange_b = 0x10;
>-static unsigned int tx_ufc_b = 0x20;
>-static unsigned int tx_urange_c = 0x30;
>-static unsigned int tx_ufc_c = 0x40;
>-static unsigned int tx_ufc_d = 0x80;
>-static unsigned int rx_urange_a = 0xA;
>-static unsigned int rx_ufc_a = 0x1;
>-static unsigned int rx_urange_b = 0x10;
>-static unsigned int rx_ufc_b = 0x2;
>-static unsigned int rx_urange_c = 0x30;
>-static unsigned int rx_ufc_c = 0x40;
>-static unsigned int rx_ufc_d = 0x80;
>-static u8 latency_timer = 0xf8;
>-static u8 max_read_byte_cnt = 2;
>+static unsigned int bimodal = 0;
>+#ifndef CONFIG_S2IO_NAPI
>+static unsigned int indicate_max_pkts;
>+#endif
>+/* Frequency of Rx desc syncs expressed as power of 2 */
>+static unsigned int rxsync_frequency = 3;
> 
>-/* 
>+/*
>  * S2IO device table.
>- * This table lists all the devices that this driver supports. 
>+ * This table lists all the devices that this driver supports.
>  */
> static struct pci_device_id s2io_tbl[] __devinitdata = {
> 	{PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
> 	 PCI_ANY_ID, PCI_ANY_ID},
> 	{PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
> 	 PCI_ANY_ID, PCI_ANY_ID},
>+	{PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
>+         PCI_ANY_ID, PCI_ANY_ID},
>+        {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
>+         PCI_ANY_ID, PCI_ANY_ID},
> 	{0,}
> };
> 
> MODULE_DEVICE_TABLE(pci, s2io_tbl);
> 
> static struct pci_driver s2io_driver = {
>-	name:"S2IO",
>-	id_table:s2io_tbl,
>-	probe:s2io_init_nic,
>-	remove:__devexit_p(s2io_rem_nic),
>+      .name = "S2IO",
>+      .id_table = s2io_tbl,
>+      .probe = s2io_init_nic,
>+      .remove = __devexit_p(s2io_rem_nic),
> };
> 
> /* A simplifier macro used both by init and free shared_mem Fns(). */
>-#define container_index(len, per_each) ((len+per_each - 1) / per_each)
>+#define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
> 
> /**
>  * init_shared_mem - Allocation and Initialization of Memory
>  * @nic: Device private variable.
>- * Description: The function allocates the all memory areas shared 
>- * between the NIC and the driver. This includes Tx descriptors, 
>+ * Description: The function allocates all the memory areas shared
>+ * between the NIC and the driver. This includes Tx descriptors,
>  * Rx descriptors and the statistics block.
>  */
> 
>@@ -323,7 +351,7 @@ static int init_shared_mem(struct s2io_n
> 	void *tmp_v_addr, *tmp_v_addr_next;
> 	dma_addr_t tmp_p_addr, tmp_p_addr_next;
> 	RxD_block_t *pre_rxd_blk = NULL;
>-	int i, j, blk_cnt;
>+	int i, j, blk_cnt, rx_sz, tx_sz;
> 	int lst_size, lst_per_page;
> 	struct net_device *dev = nic->dev;
> #ifdef CONFIG_2BUFF_MODE
>@@ -340,40 +368,45 @@ static int init_shared_mem(struct s2io_n
> 
> 	/* Allocation and initialization of TXDLs in FIOFs */
> 	size = 0;
>-	for (i = 0; i < config->TxFIFONum; i++) {
>-		size += config->tx_cfg[i].FifoLen;
>+	for (i = 0; i < config->tx_fifo_num; i++) {
>+		size += config->tx_cfg[i].fifo_len;
> 	}
> 	if (size > MAX_AVAILABLE_TXDS) {
>-		DBG_PRINT(ERR_DBG, "%s: Total number of Tx FIFOs ",
>-			  dev->name);
>-		DBG_PRINT(ERR_DBG, "exceeds the maximum value ");
>-		DBG_PRINT(ERR_DBG, "that can be used\n");
>+		DBG_PRINT(ERR_DBG, "%s: Requested TxDs too high, ",
>+			  __FUNCTION__);
>+		DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
> 		return FAILURE;
> 	}
> 
>-	lst_size = (sizeof(TxD_t) * config->MaxTxDs);
>+	lst_size = (sizeof(TxD_t) * config->max_txds);
>+	tx_sz = lst_size * size;
> 	lst_per_page = PAGE_SIZE / lst_size;
> 
>-	for (i = 0; i < config->TxFIFONum; i++) {
>-		int fifo_len = config->tx_cfg[i].FifoLen;
>+	for (i = 0; i < config->tx_fifo_num; i++) {
>+		int fifo_len = config->tx_cfg[i].fifo_len;
> 		int list_holder_size = fifo_len * sizeof(list_info_hold_t);
>-		nic->list_info[i] = kmalloc(list_holder_size, GFP_KERNEL);
>-		if (!nic->list_info[i]) {
>+		mac_control->fifos[i].list_info = kmalloc(list_holder_size,
>+							  GFP_KERNEL);
>+		if (!mac_control->fifos[i].list_info) {
> 			DBG_PRINT(ERR_DBG,
> 				  "Malloc failed for list_info\n");
> 			return -ENOMEM;
> 		}
>-		memset(nic->list_info[i], 0, list_holder_size);
>+		memset(mac_control->fifos[i].list_info, 0, list_holder_size);
> 	}
>-	for (i = 0; i < config->TxFIFONum; i++) {
>-		int page_num = container_index(config->tx_cfg[i].FifoLen,
>-					       lst_per_page);
>-		mac_control->tx_curr_put_info[i].offset = 0;
>-		mac_control->tx_curr_put_info[i].fifo_len =
>-		    config->tx_cfg[i].FifoLen - 1;
>-		mac_control->tx_curr_get_info[i].offset = 0;
>-		mac_control->tx_curr_get_info[i].fifo_len =
>-		    config->tx_cfg[i].FifoLen - 1;
>+	for (i = 0; i < config->tx_fifo_num; i++) {
>+		int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
>+						lst_per_page);
>+		mac_control->fifos[i].tx_curr_put_info.offset = 0;
>+		mac_control->fifos[i].tx_curr_put_info.fifo_len =
>+		    config->tx_cfg[i].fifo_len - 1;
>+		mac_control->fifos[i].tx_curr_get_info.offset = 0;
>+		mac_control->fifos[i].tx_curr_get_info.fifo_len =
>+		    config->tx_cfg[i].fifo_len - 1;
>+		mac_control->fifos[i].fifo_no = i;
>+		mac_control->fifos[i].nic = nic;
>+		mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 1;
>+
> 		for (j = 0; j < page_num; j++) {
> 			int k = 0;
> 			dma_addr_t tmp_p;
>@@ -386,50 +419,72 @@ static int init_shared_mem(struct s2io_n
> 				DBG_PRINT(ERR_DBG, "failed for TxDL\n");
> 				return -ENOMEM;
> 			}
>+			/* If we got a zero DMA address(can happen on
>+			 * certain platforms like PPC), reallocate.
>+			 * Store virtual address of page we don't want,
>+			 * to be freed later.
>+			 */
>+			if (!tmp_p) {
>+				mac_control->zerodma_virt_addr = tmp_v;
>+				DBG_PRINT(INIT_DBG, 
>+				"%s: Zero DMA address for TxDL. ", dev->name);
>+				DBG_PRINT(INIT_DBG, 
>+				"Virtual address %llx\n", (u64)tmp_v);
>+				tmp_v = pci_alloc_consistent(nic->pdev,
>+						     PAGE_SIZE, &tmp_p);
>+				if (!tmp_v) {
>+					DBG_PRINT(ERR_DBG,
>+					  "pci_alloc_consistent ");
>+					DBG_PRINT(ERR_DBG, "failed for TxDL\n");
>+					return -ENOMEM;
>+				}
>+			}
> 			while (k < lst_per_page) {
> 				int l = (j * lst_per_page) + k;
>-				if (l == config->tx_cfg[i].FifoLen)
>-					goto end_txd_alloc;
>-				nic->list_info[i][l].list_virt_addr =
>+				if (l == config->tx_cfg[i].fifo_len)
>+					break;
>+				mac_control->fifos[i].list_info[l].list_virt_addr =
> 				    tmp_v + (k * lst_size);
>-				nic->list_info[i][l].list_phy_addr =
>+				mac_control->fifos[i].list_info[l].list_phy_addr =
> 				    tmp_p + (k * lst_size);
> 				k++;
> 			}
> 		}
> 	}
>-      end_txd_alloc:
> 
> 	/* Allocation and initialization of RXDs in Rings */
> 	size = 0;
>-	for (i = 0; i < config->RxRingNum; i++) {
>-		if (config->rx_cfg[i].NumRxd % (MAX_RXDS_PER_BLOCK + 1)) {
>+	for (i = 0; i < config->rx_ring_num; i++) {
>+		if (config->rx_cfg[i].num_rxd % (MAX_RXDS_PER_BLOCK + 1)) {
> 			DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
> 			DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
> 				  i);
> 			DBG_PRINT(ERR_DBG, "RxDs per Block");
> 			return FAILURE;
> 		}
>-		size += config->rx_cfg[i].NumRxd;
>-		nic->block_count[i] =
>-		    config->rx_cfg[i].NumRxd / (MAX_RXDS_PER_BLOCK + 1);
>-		nic->pkt_cnt[i] =
>-		    config->rx_cfg[i].NumRxd - nic->block_count[i];
>+		size += config->rx_cfg[i].num_rxd;
>+		mac_control->rings[i].block_count =
>+		    config->rx_cfg[i].num_rxd / (MAX_RXDS_PER_BLOCK + 1);
>+		mac_control->rings[i].pkt_cnt =
>+		    config->rx_cfg[i].num_rxd - mac_control->rings[i].block_count;
> 	}
> 	size = (size * (sizeof(RxD_t)));
>-	mac_control->rxd_ring_mem_sz = size;
>+	rx_sz = size;
>+
>+	for (i = 0; i < config->rx_ring_num; i++) {
>+		mac_control->rings[i].rx_curr_get_info.block_index = 0;
>+		mac_control->rings[i].rx_curr_get_info.offset = 0;
>+		mac_control->rings[i].rx_curr_get_info.ring_len =
>+		    config->rx_cfg[i].num_rxd - 1;
>+		mac_control->rings[i].rx_curr_put_info.block_index = 0;
>+		mac_control->rings[i].rx_curr_put_info.offset = 0;
>+		mac_control->rings[i].rx_curr_put_info.ring_len =
>+		    config->rx_cfg[i].num_rxd - 1;
>+		mac_control->rings[i].nic = nic;
>+		mac_control->rings[i].ring_no = i;
> 
>-	for (i = 0; i < config->RxRingNum; i++) {
>-		mac_control->rx_curr_get_info[i].block_index = 0;
>-		mac_control->rx_curr_get_info[i].offset = 0;
>-		mac_control->rx_curr_get_info[i].ring_len =
>-		    config->rx_cfg[i].NumRxd - 1;
>-		mac_control->rx_curr_put_info[i].block_index = 0;
>-		mac_control->rx_curr_put_info[i].offset = 0;
>-		mac_control->rx_curr_put_info[i].ring_len =
>-		    config->rx_cfg[i].NumRxd - 1;
> 		blk_cnt =
>-		    config->rx_cfg[i].NumRxd / (MAX_RXDS_PER_BLOCK + 1);
>+		    config->rx_cfg[i].num_rxd / (MAX_RXDS_PER_BLOCK + 1);
> 		/*  Allocating all the Rx blocks */
> 		for (j = 0; j < blk_cnt; j++) {
> #ifndef CONFIG_2BUFF_MODE
>@@ -441,32 +496,36 @@ static int init_shared_mem(struct s2io_n
> 							  &tmp_p_addr);
> 			if (tmp_v_addr == NULL) {
> 				/*
>-				 * In case of failure, free_shared_mem() 
>-				 * is called, which should free any 
>-				 * memory that was alloced till the 
>+				 * In case of failure, free_shared_mem()
>+				 * is called, which should free any
>+				 * memory that was alloced till the
> 				 * failure happened.
> 				 */
>-				nic->rx_blocks[i][j].block_virt_addr =
>+				mac_control->rings[i].rx_blocks[j].block_virt_addr =
> 				    tmp_v_addr;
> 				return -ENOMEM;
> 			}
> 			memset(tmp_v_addr, 0, size);
>-			nic->rx_blocks[i][j].block_virt_addr = tmp_v_addr;
>-			nic->rx_blocks[i][j].block_dma_addr = tmp_p_addr;
>+			mac_control->rings[i].rx_blocks[j].block_virt_addr =
>+				tmp_v_addr;
>+			mac_control->rings[i].rx_blocks[j].block_dma_addr =
>+				tmp_p_addr;
> 		}
> 		/* Interlinking all Rx Blocks */
> 		for (j = 0; j < blk_cnt; j++) {
>-			tmp_v_addr = nic->rx_blocks[i][j].block_virt_addr;
>+			tmp_v_addr =
>+				mac_control->rings[i].rx_blocks[j].block_virt_addr;
> 			tmp_v_addr_next =
>-			    nic->rx_blocks[i][(j + 1) %
>+				mac_control->rings[i].rx_blocks[(j + 1) %
> 					      blk_cnt].block_virt_addr;
>-			tmp_p_addr = nic->rx_blocks[i][j].block_dma_addr;
>+			tmp_p_addr =
>+				mac_control->rings[i].rx_blocks[j].block_dma_addr;
> 			tmp_p_addr_next =
>-			    nic->rx_blocks[i][(j + 1) %
>+				mac_control->rings[i].rx_blocks[(j + 1) %
> 					      blk_cnt].block_dma_addr;
> 
> 			pre_rxd_blk = (RxD_block_t *) tmp_v_addr;
>-			pre_rxd_blk->reserved_1 = END_OF_BLOCK;	/* last RxD 
>+			pre_rxd_blk->reserved_1 = END_OF_BLOCK;	/* last RxD
> 								 * marker.
> 								 */
> #ifndef	CONFIG_2BUFF_MODE
>@@ -479,29 +538,29 @@ static int init_shared_mem(struct s2io_n
> 	}
> 
> #ifdef CONFIG_2BUFF_MODE
>-	/* 
>+	/*
> 	 * Allocation of Storages for buffer addresses in 2BUFF mode
> 	 * and the buffers as well.
> 	 */
>-	for (i = 0; i < config->RxRingNum; i++) {
>+	for (i = 0; i < config->rx_ring_num; i++) {
> 		blk_cnt =
>-		    config->rx_cfg[i].NumRxd / (MAX_RXDS_PER_BLOCK + 1);
>-		nic->ba[i] = kmalloc((sizeof(buffAdd_t *) * blk_cnt),
>+		    config->rx_cfg[i].num_rxd / (MAX_RXDS_PER_BLOCK + 1);
>+		mac_control->rings[i].ba = kmalloc((sizeof(buffAdd_t *) * blk_cnt),
> 				     GFP_KERNEL);
>-		if (!nic->ba[i])
>+		if (!mac_control->rings[i].ba)
> 			return -ENOMEM;
> 		for (j = 0; j < blk_cnt; j++) {
> 			int k = 0;
>-			nic->ba[i][j] = kmalloc((sizeof(buffAdd_t) *
>+			mac_control->rings[i].ba[j] = kmalloc((sizeof(buffAdd_t) *
> 						 (MAX_RXDS_PER_BLOCK + 1)),
> 						GFP_KERNEL);
>-			if (!nic->ba[i][j])
>+			if (!mac_control->rings[i].ba[j])
> 				return -ENOMEM;
> 			while (k != MAX_RXDS_PER_BLOCK) {
>-				ba = &nic->ba[i][j][k];
>+				ba = &mac_control->rings[i].ba[j][k];
> 
> 				ba->ba_0_org = (void *) kmalloc
>-				    (BUF0_LEN + ALIGN_SIZE, GFP_ATOMIC);
>+				    (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
> 				if (!ba->ba_0_org)
> 					return -ENOMEM;
> 				tmp = (u64) ba->ba_0_org;
>@@ -510,7 +569,7 @@ static int init_shared_mem(struct s2io_n
> 				ba->ba_0 = (void *) tmp;
> 
> 				ba->ba_1_org = (void *) kmalloc
>-				    (BUF1_LEN + ALIGN_SIZE, GFP_ATOMIC);
>+				    (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
> 				if (!ba->ba_1_org)
> 					return -ENOMEM;
> 				tmp = (u64) ba->ba_1_org;
>@@ -529,9 +588,9 @@ static int init_shared_mem(struct s2io_n
> 	    (nic->pdev, size, &mac_control->stats_mem_phy);
> 
> 	if (!mac_control->stats_mem) {
>-		/* 
>-		 * In case of failure, free_shared_mem() is called, which 
>-		 * should free any memory that was alloced till the 
>+		/*
>+		 * In case of failure, free_shared_mem() is called, which
>+		 * should free any memory that was alloced till the
> 		 * failure happened.
> 		 */
> 		return -ENOMEM;
>@@ -541,19 +600,14 @@ static int init_shared_mem(struct s2io_n
> 	tmp_v_addr = mac_control->stats_mem;
> 	mac_control->stats_info = (StatInfo_t *) tmp_v_addr;
> 	memset(tmp_v_addr, 0, size);
>-#ifdef SNMP_SUPPORT
>-	nic->nMemorySize = mac_control->txd_list_mem_sz +
>-	    mac_control->stats_mem_sz + mac_control->rxd_ring_mem_sz;
>-#endif
>-
> 	DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
> 		  (unsigned long long) tmp_p_addr);
> 
> 	return SUCCESS;
> }
> 
>-/**  
>- * free_shared_mem - Free the allocated Memory 
>+/**
>+ * free_shared_mem - Free the allocated Memory
>  * @nic:  Device private variable.
>  * Description: This function is to free all memory locations allocated by
>  * the init_shared_mem() function and return it to the kernel.
>@@ -567,7 +621,7 @@ static void free_shared_mem(struct s2io_
> 	mac_info_t *mac_control;
> 	struct config_param *config;
> 	int lst_size, lst_per_page;
>-
>+	struct net_device *dev = nic->dev;
> 
> 	if (!nic)
> 		return;
>@@ -575,23 +629,40 @@ static void free_shared_mem(struct s2io_
> 	mac_control = &nic->mac_control;
> 	config = &nic->config;
> 
>-	lst_size = (sizeof(TxD_t) * config->MaxTxDs);
>+	lst_size = (sizeof(TxD_t) * config->max_txds);
> 	lst_per_page = PAGE_SIZE / lst_size;
> 
>-	for (i = 0; i < config->TxFIFONum; i++) {
>-		int page_num = container_index(config->tx_cfg[i].FifoLen,
>-					       lst_per_page);
>+	for (i = 0; i < config->tx_fifo_num; i++) {
>+		int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
>+						lst_per_page);
> 		for (j = 0; j < page_num; j++) {
> 			int mem_blks = (j * lst_per_page);
>-			if (!nic->list_info[i][mem_blks].list_virt_addr)
>+			if (!mac_control->fifos[i].list_info)
>+				return;	
>+			if (!mac_control->fifos[i].list_info[mem_blks].
>+				 list_virt_addr)
> 				break;
> 			pci_free_consistent(nic->pdev, PAGE_SIZE,
>-					    nic->list_info[i][mem_blks].
>+					    mac_control->fifos[i].
>+					    list_info[mem_blks].
> 					    list_virt_addr,
>-					    nic->list_info[i][mem_blks].
>+					    mac_control->fifos[i].
>+					    list_info[mem_blks].
> 					    list_phy_addr);
> 		}
>-		kfree(nic->list_info[i]);
>+		/* If we got a zero DMA address during allocation,
>+		 * free the page now
>+		 */
>+		if (mac_control->zerodma_virt_addr) {
>+			pci_free_consistent(nic->pdev, PAGE_SIZE,
>+					    mac_control->zerodma_virt_addr,
>+					    (dma_addr_t)0);
>+			DBG_PRINT(INIT_DBG, 
>+			"%s: Freeing TxDL with zero DMA addr. ", dev->name);
>+			DBG_PRINT(INIT_DBG, "Virtual address %llx\n",
>+			(u64)(mac_control->zerodma_virt_addr));
>+		}
>+		kfree(mac_control->fifos[i].list_info);
> 	}
> 
> #ifndef CONFIG_2BUFF_MODE
>@@ -599,11 +670,13 @@ static void free_shared_mem(struct s2io_
> #else
> 	size = SIZE_OF_BLOCK;
> #endif
>-	for (i = 0; i < config->RxRingNum; i++) {
>-		blk_cnt = nic->block_count[i];
>+	for (i = 0; i < config->rx_ring_num; i++) {
>+		blk_cnt = mac_control->rings[i].block_count;
> 		for (j = 0; j < blk_cnt; j++) {
>-			tmp_v_addr = nic->rx_blocks[i][j].block_virt_addr;
>-			tmp_p_addr = nic->rx_blocks[i][j].block_dma_addr;
>+			tmp_v_addr = mac_control->rings[i].rx_blocks[j].
>+				block_virt_addr;
>+			tmp_p_addr = mac_control->rings[i].rx_blocks[j].
>+				block_dma_addr;
> 			if (tmp_v_addr == NULL)
> 				break;
> 			pci_free_consistent(nic->pdev, size,
>@@ -613,23 +686,23 @@ static void free_shared_mem(struct s2io_
> 
> #ifdef CONFIG_2BUFF_MODE
> 	/* Freeing buffer storage addresses in 2BUFF mode. */
>-	for (i = 0; i < config->RxRingNum; i++) {
>+	for (i = 0; i < config->rx_ring_num; i++) {
> 		blk_cnt =
>-		    config->rx_cfg[i].NumRxd / (MAX_RXDS_PER_BLOCK + 1);
>+		    config->rx_cfg[i].num_rxd / (MAX_RXDS_PER_BLOCK + 1);
> 		for (j = 0; j < blk_cnt; j++) {
> 			int k = 0;
>-			if (!nic->ba[i][j])
>+			if (!mac_control->rings[i].ba[j])
> 				continue;
> 			while (k != MAX_RXDS_PER_BLOCK) {
>-				buffAdd_t *ba = &nic->ba[i][j][k];
>+				buffAdd_t *ba = &mac_control->rings[i].ba[j][k];
> 				kfree(ba->ba_0_org);
> 				kfree(ba->ba_1_org);
> 				k++;
> 			}
>-			kfree(nic->ba[i][j]);
>+			kfree(mac_control->rings[i].ba[j]);
> 		}
>-		if (nic->ba[i])
>-			kfree(nic->ba[i]);
>+		if (mac_control->rings[i].ba)
>+			kfree(mac_control->rings[i].ba);
> 	}
> #endif
> 
>@@ -641,110 +714,137 @@ static void free_shared_mem(struct s2io_
> 	}
> }
> 
>-/**  
>- *  init_nic - Initialization of hardware 
>+/**
>+ * s2io_verify_pci_mode -
>+ */
>+
>+static int s2io_verify_pci_mode(nic_t *nic)
>+{
>+	XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
>+	register u64 val64 = 0;
>+	int     mode;
>+
>+	val64 = readq(&bar0->pci_mode);
>+	mode = (u8)GET_PCI_MODE(val64);
>+
>+	if ( val64 & PCI_MODE_UNKNOWN_MODE)
>+		return -1;      /* Unknown PCI mode */
>+	return mode;
>+}
>+
>+
>+/**
>+ * s2io_print_pci_mode -
>+ */
>+static int s2io_print_pci_mode(nic_t *nic)
>+{
>+	XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
>+	register u64 val64 = 0;
>+	int	mode;
>+	struct config_param *config = &nic->config;
>+
>+	val64 = readq(&bar0->pci_mode);
>+	mode = (u8)GET_PCI_MODE(val64);
>+
>+	if ( val64 & PCI_MODE_UNKNOWN_MODE)
>+		return -1;	/* Unknown PCI mode */
>+
>+	if (val64 & PCI_MODE_32_BITS) {
>+		DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
>+	} else {
>+		DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
>+	}
>+
>+	switch(mode) {
>+		case PCI_MODE_PCI_33:
>+			DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
>+			config->bus_speed = 33;
>+			break;
>+		case PCI_MODE_PCI_66:
>+			DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
>+			config->bus_speed = 133;
>+			break;
>+		case PCI_MODE_PCIX_M1_66:
>+			DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
>+			config->bus_speed = 133; /* Herc doubles the clock rate */
>+			break;
>+		case PCI_MODE_PCIX_M1_100:
>+			DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
>+			config->bus_speed = 200;
>+			break;
>+		case PCI_MODE_PCIX_M1_133:
>+			DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
>+			config->bus_speed = 266;
>+			break;
>+		case PCI_MODE_PCIX_M2_66:
>+			DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
>+			config->bus_speed = 133;
>+			break;
>+		case PCI_MODE_PCIX_M2_100:
>+			DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
>+			config->bus_speed = 200;
>+			break;
>+		case PCI_MODE_PCIX_M2_133:
>+			DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
>+			config->bus_speed = 266;
>+			break;
>+		default:
>+			return -1;	/* Unsupported bus speed */
>+	}
>+
>+	return mode;
>+}
>+
>+/**
>+ *  init_nic - Initialization of hardware
>  *  @nic: device peivate variable
>- *  Description: The function sequentially configures every block 
>- *  of the H/W from their reset values. 
>- *  Returns:  SUCCESS on success and 
>+ *  Description: The function sequentially configures every block
>+ *  of the H/W from their reset values.
>+ *  Return Value:  SUCCESS on success and
>  *  '-1' on failure (endian settings incorrect).
>  */
> 
> static int init_nic(struct s2io_nic *nic)
> {
>-	XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
>+	XENA_dev_config_t __iomem *bar0 = nic->bar0;
> 	struct net_device *dev = nic->dev;
> 	register u64 val64 = 0;
>-	void *add;
>+	void __iomem *add;
> 	u32 time;
> 	int i, j;
> 	mac_info_t *mac_control;
> 	struct config_param *config;
> 	int mdio_cnt = 0, dtx_cnt = 0;
>-	unsigned long long print_var, mem_share;
>+	unsigned long long mem_share;
>+	int mem_size;
> 
> 	mac_control = &nic->mac_control;
> 	config = &nic->config;
> 
>-	/* 
>-	 * Set proper endian settings and verify the same by 
>-	 * reading the PIF Feed-back register.
>-	 */
>-#ifdef  __BIG_ENDIAN
>-	/*
>-	 * The device by default set to a big endian format, so 
>-	 * a big endian driver need not set anything.
>-	 */
>-	writeq(0xffffffffffffffffULL, &bar0->swapper_ctrl);
>-	val64 = (SWAPPER_CTRL_PIF_R_FE |
>-		 SWAPPER_CTRL_PIF_R_SE |
>-		 SWAPPER_CTRL_PIF_W_FE |
>-		 SWAPPER_CTRL_PIF_W_SE |
>-		 SWAPPER_CTRL_TXP_FE |
>-		 SWAPPER_CTRL_TXP_SE |
>-		 SWAPPER_CTRL_TXD_R_FE |
>-		 SWAPPER_CTRL_TXD_W_FE |
>-		 SWAPPER_CTRL_TXF_R_FE |
>-		 SWAPPER_CTRL_RXD_R_FE |
>-		 SWAPPER_CTRL_RXD_W_FE |
>-		 SWAPPER_CTRL_RXF_W_FE |
>-		 SWAPPER_CTRL_XMSI_FE |
>-		 SWAPPER_CTRL_XMSI_SE |
>-		 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
>-	writeq(val64, &bar0->swapper_ctrl);
>-#else
>-	/* 
>-	 * Initially we enable all bits to make it accessible by 
>-	 * the driver, then we selectively enable only those bits 
>-	 * that we want to set.
>-	 */
>-	writeq(0xffffffffffffffffULL, &bar0->swapper_ctrl);
>-	val64 = (SWAPPER_CTRL_PIF_R_FE |
>-		 SWAPPER_CTRL_PIF_R_SE |
>-		 SWAPPER_CTRL_PIF_W_FE |
>-		 SWAPPER_CTRL_PIF_W_SE |
>-		 SWAPPER_CTRL_TXP_FE |
>-		 SWAPPER_CTRL_TXP_SE |
>-		 SWAPPER_CTRL_TXD_R_FE |
>-		 SWAPPER_CTRL_TXD_R_SE |
>-		 SWAPPER_CTRL_TXD_W_FE |
>-		 SWAPPER_CTRL_TXD_W_SE |
>-		 SWAPPER_CTRL_TXF_R_FE |
>-		 SWAPPER_CTRL_RXD_R_FE |
>-		 SWAPPER_CTRL_RXD_R_SE |
>-		 SWAPPER_CTRL_RXD_W_FE |
>-		 SWAPPER_CTRL_RXD_W_SE |
>-		 SWAPPER_CTRL_RXF_W_FE |
>-		 SWAPPER_CTRL_XMSI_FE |
>-		 SWAPPER_CTRL_XMSI_SE |
>-		 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
>-	writeq(val64, &bar0->swapper_ctrl);
>-#endif
>+	/* to set the swapper controle on the card */
>+	if(s2io_set_swapper(nic)) {
>+		DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
>+		return -1;
>+	}
> 
>-	/* 
>-	 * Verifying if endian settings are accurate by 
>-	 * reading a feedback register.
>+	/*
>+	 * Herc requires EOI to be removed from reset before XGXS, so..
> 	 */
>-	val64 = readq(&bar0->pif_rd_swapper_fb);
>-	if (val64 != 0x0123456789ABCDEFULL) {
>-		/* Endian settings are incorrect, calls for another dekko. */
>-		print_var = (unsigned long long) val64;
>-		DBG_PRINT(INIT_DBG, "%s: Endian settings are wrong",
>-			  dev->name);
>-		DBG_PRINT(ERR_DBG, ", feedback read %llx\n", print_var);
>-
>-		return FAILURE;
>+	if (nic->device_type & XFRAME_II_DEVICE) {
>+		val64 = 0xA500000000ULL;
>+		writeq(val64, &bar0->sw_reset);
>+		msleep(500);
>+		val64 = readq(&bar0->sw_reset);
> 	}
> 
> 	/* Remove XGXS from reset state */
> 	val64 = 0;
> 	writeq(val64, &bar0->sw_reset);
>+	msleep(500);
> 	val64 = readq(&bar0->sw_reset);
>-	set_current_state(TASK_UNINTERRUPTIBLE);
>-	schedule_timeout(HZ / 2);
> 
> 	/*  Enable Receiving broadcasts */
>-	add = (void *) &bar0->mac_cfg;
>+	add = &bar0->mac_cfg;
> 	val64 = readq(&bar0->mac_cfg);
> 	val64 |= MAC_RMAC_BCAST_ENABLE;
> 	writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
>@@ -761,48 +861,58 @@ static int init_nic(struct s2io_nic *nic
> 	val64 = dev->mtu;
> 	writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
> 
>-	/* 
>-	 * Configuring the XAUI Interface of Xena. 
>+	/*
>+	 * Configuring the XAUI Interface of Xena.
> 	 * ***************************************
>-	 * To Configure the Xena's XAUI, one has to write a series 
>-	 * of 64 bit values into two registers in a particular 
>-	 * sequence. Hence a macro 'SWITCH_SIGN' has been defined 
>-	 * which will be defined in the array of configuration values 
>-	 * (default_dtx_cfg & default_mdio_cfg) at appropriate places 
>-	 * to switch writing from one regsiter to another. We continue 
>+	 * To Configure the Xena's XAUI, one has to write a series
>+	 * of 64 bit values into two registers in a particular
>+	 * sequence. Hence a macro 'SWITCH_SIGN' has been defined
>+	 * which will be defined in the array of configuration values
>+	 * (xena_dtx_cfg & xena_mdio_cfg) at appropriate places
>+	 * to switch writing from one regsiter to another. We continue
> 	 * writing these values until we encounter the 'END_SIGN' macro.
>-	 * For example, After making a series of 21 writes into 
>-	 * dtx_control register the 'SWITCH_SIGN' appears and hence we 
>+	 * For example, After making a series of 21 writes into
>+	 * dtx_control register the 'SWITCH_SIGN' appears and hence we
> 	 * start writing into mdio_control until we encounter END_SIGN.
> 	 */
>-	while (1) {
>-	      dtx_cfg:
>-		while (default_dtx_cfg[dtx_cnt] != END_SIGN) {
>-			if (default_dtx_cfg[dtx_cnt] == SWITCH_SIGN) {
>-				dtx_cnt++;
>-				goto mdio_cfg;
>-			}
>-			SPECIAL_REG_WRITE(default_dtx_cfg[dtx_cnt],
>+	if (nic->device_type & XFRAME_II_DEVICE) {
>+		while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
>+			SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
> 					  &bar0->dtx_control, UF);
>-			val64 = readq(&bar0->dtx_control);
>+			if (dtx_cnt & 0x1)
>+				msleep(1); /* Necessary!! */
> 			dtx_cnt++;
> 		}
>-	      mdio_cfg:
>-		while (default_mdio_cfg[mdio_cnt] != END_SIGN) {
>-			if (default_mdio_cfg[mdio_cnt] == SWITCH_SIGN) {
>+	} else {
>+		while (1) {
>+		      dtx_cfg:
>+			while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
>+				if (xena_dtx_cfg[dtx_cnt] == SWITCH_SIGN) {
>+					dtx_cnt++;
>+					goto mdio_cfg;
>+				}
>+				SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
>+						  &bar0->dtx_control, UF);
>+				val64 = readq(&bar0->dtx_control);
>+				dtx_cnt++;
>+			}
>+		      mdio_cfg:
>+			while (xena_mdio_cfg[mdio_cnt] != END_SIGN) {
>+				if (xena_mdio_cfg[mdio_cnt] == SWITCH_SIGN) {
>+					mdio_cnt++;
>+					goto dtx_cfg;
>+				}
>+				SPECIAL_REG_WRITE(xena_mdio_cfg[mdio_cnt],
>+						  &bar0->mdio_control, UF);
>+				val64 = readq(&bar0->mdio_control);
> 				mdio_cnt++;
>+			}
>+			if ((xena_dtx_cfg[dtx_cnt] == END_SIGN) &&
>+			    (xena_mdio_cfg[mdio_cnt] == END_SIGN)) {
>+				break;
>+			} else {
> 				goto dtx_cfg;
> 			}
>-			SPECIAL_REG_WRITE(default_mdio_cfg[mdio_cnt],
>-					  &bar0->mdio_control, UF);
>-			val64 = readq(&bar0->mdio_control);
>-			mdio_cnt++;
>-		}
>-		if ((default_dtx_cfg[dtx_cnt] == END_SIGN) &&
>-		    (default_mdio_cfg[mdio_cnt] == END_SIGN)) {
>-			break;
>-		} else {
>-			goto dtx_cfg;
> 		}
> 	}
> 
>@@ -814,13 +924,13 @@ static int init_nic(struct s2io_nic *nic
> 	writeq(val64, &bar0->tx_fifo_partition_3);
> 
> 
>-	for (i = 0, j = 0; i < config->TxFIFONum; i++) {
>+	for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
> 		val64 |=
>-		    vBIT(config->tx_cfg[i].FifoLen - 1, ((i * 32) + 19),
>-			 13) | vBIT(config->tx_cfg[i].FifoPriority,
>+		    vBIT(config->tx_cfg[i].fifo_len - 1, ((i * 32) + 19),
>+			 13) | vBIT(config->tx_cfg[i].fifo_priority,
> 				    ((i * 32) + 5), 3);
> 
>-		if (i == (config->TxFIFONum - 1)) {
>+		if (i == (config->tx_fifo_num - 1)) {
> 			if (i % 2 == 0)
> 				i++;
> 		}
>@@ -849,12 +959,20 @@ static int init_nic(struct s2io_nic *nic
> 	val64 |= BIT(0);	/* To enable the FIFO partition. */
> 	writeq(val64, &bar0->tx_fifo_partition_0);
> 
>+	/*
>+	 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
>+	 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
>+	 */
>+	if ((nic->device_type == XFRAME_I_DEVICE) &&
>+		(get_xena_rev_id(nic->pdev) < 4))
>+		writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
>+
> 	val64 = readq(&bar0->tx_fifo_partition_0);
> 	DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
> 		  &bar0->tx_fifo_partition_0, (unsigned long long) val64);
> 
>-	/* 
>-	 * Initialization of Tx_PA_CONFIG register to ignore packet 
>+	/*
>+	 * Initialization of Tx_PA_CONFIG register to ignore packet
> 	 * integrity checking.
> 	 */
> 	val64 = readq(&bar0->tx_pa_cfg);
>@@ -864,100 +982,311 @@ static int init_nic(struct s2io_nic *nic
> 
> 	/* Rx DMA intialization. */
> 	val64 = 0;
>-	for (i = 0; i < config->RxRingNum; i++) {
>+	for (i = 0; i < config->rx_ring_num; i++) {
> 		val64 |=
>-		    vBIT(config->rx_cfg[i].RingPriority, (5 + (i * 8)), 3);
>+		    vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)),
>+			 3);
> 	}
> 	writeq(val64, &bar0->rx_queue_priority);
> 
>-	/* 
>-	 * Allocating equal share of memory to all the 
>+	/*
>+	 * Allocating equal share of memory to all the
> 	 * configured Rings.
> 	 */
> 	val64 = 0;
>-	for (i = 0; i < config->RxRingNum; i++) {
>+	if (nic->device_type & XFRAME_II_DEVICE)
>+		mem_size = 32;
>+	else
>+		mem_size = 64;
>+
>+	for (i = 0; i < config->rx_ring_num; i++) {
> 		switch (i) {
> 		case 0:
>-			mem_share = (64 / config->RxRingNum +
>-				     64 % config->RxRingNum);
>+			mem_share = (mem_size / config->rx_ring_num +
>+				     mem_size % config->rx_ring_num);
> 			val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
> 			continue;
> 		case 1:
>-			mem_share = (64 / config->RxRingNum);
>+			mem_share = (mem_size / config->rx_ring_num);
> 			val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
> 			continue;
> 		case 2:
>-			mem_share = (64 / config->RxRingNum);
>+			mem_share = (mem_size / config->rx_ring_num);
> 			val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
> 			continue;
> 		case 3:
>-			mem_share = (64 / config->RxRingNum);
>+			mem_share = (mem_size / config->rx_ring_num);
> 			val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
> 			continue;
> 		case 4:
>-			mem_share = (64 / config->RxRingNum);
>+			mem_share = (mem_size / config->rx_ring_num);
> 			val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
> 			continue;
> 		case 5:
>-			mem_share = (64 / config->RxRingNum);
>+			mem_share = (mem_size / config->rx_ring_num);
> 			val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
> 			continue;
> 		case 6:
>-			mem_share = (64 / config->RxRingNum);
>+			mem_share = (mem_size / config->rx_ring_num);
> 			val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
> 			continue;
> 		case 7:
>-			mem_share = (64 / config->RxRingNum);
>+			mem_share = (mem_size / config->rx_ring_num);
> 			val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
> 			continue;
> 		}
> 	}
> 	writeq(val64, &bar0->rx_queue_cfg);
> 
>-	/* 
>-	 * Initializing the Tx round robin registers to 0.
>-	 * Filling Tx and Rx round robin registers as per the 
>-	 * number of FIFOs and Rings is still TODO.
>-	 */
>-	writeq(0, &bar0->tx_w_round_robin_0);
>-	writeq(0, &bar0->tx_w_round_robin_1);
>-	writeq(0, &bar0->tx_w_round_robin_2);
>-	writeq(0, &bar0->tx_w_round_robin_3);
>-	writeq(0, &bar0->tx_w_round_robin_4);
>-
>-	/* 
>-	 * TODO
>-	 * Disable Rx steering. Hard coding all packets be steered to
>-	 * Queue 0 for now. 
>-	 */
>-	if (rx_prio) {
>-		u64 def = 0x8000000000000000ULL, tmp;
>-		for (i = 0; i < MAX_RX_RINGS; i++) {
>-			tmp = (u64) (def >> (i % config->RxRingNum));
>-			val64 |= (u64) (tmp >> (i * 8));
>-		}
>-		writeq(val64, &bar0->rts_qos_steering);
>-	} else {
>+	/*
>+	 * Filling Tx round robin registers
>+	 * as per the number of FIFOs
>+	 */
>+	switch (config->tx_fifo_num) {
>+	case 1:
>+		val64 = 0x0000000000000000ULL;
>+		writeq(val64, &bar0->tx_w_round_robin_0);
>+		writeq(val64, &bar0->tx_w_round_robin_1);
>+		writeq(val64, &bar0->tx_w_round_robin_2);
>+		writeq(val64, &bar0->tx_w_round_robin_3);
>+		writeq(val64, &bar0->tx_w_round_robin_4);
>+		break;
>+	case 2:
>+		val64 = 0x0000010000010000ULL;
>+		writeq(val64, &bar0->tx_w_round_robin_0);
>+		val64 = 0x0100000100000100ULL;
>+		writeq(val64, &bar0->tx_w_round_robin_1);
>+		val64 = 0x0001000001000001ULL;
>+		writeq(val64, &bar0->tx_w_round_robin_2);
>+		val64 = 0x0000010000010000ULL;
>+		writeq(val64, &bar0->tx_w_round_robin_3);
>+		val64 = 0x0100000000000000ULL;
>+		writeq(val64, &bar0->tx_w_round_robin_4);
>+		break;
>+	case 3:
>+		val64 = 0x0001000102000001ULL;
>+		writeq(val64, &bar0->tx_w_round_robin_0);
>+		val64 = 0x0001020000010001ULL;
>+		writeq(val64, &bar0->tx_w_round_robin_1);
>+		val64 = 0x0200000100010200ULL;
>+		writeq(val64, &bar0->tx_w_round_robin_2);
>+		val64 = 0x0001000102000001ULL;
>+		writeq(val64, &bar0->tx_w_round_robin_3);
>+		val64 = 0x0001020000000000ULL;
>+		writeq(val64, &bar0->tx_w_round_robin_4);
>+		break;
>+	case 4:
>+		val64 = 0x0001020300010200ULL;
>+		writeq(val64, &bar0->tx_w_round_robin_0);
>+		val64 = 0x0100000102030001ULL;
>+		writeq(val64, &bar0->tx_w_round_robin_1);
>+		val64 = 0x0200010000010203ULL;
>+		writeq(val64, &bar0->tx_w_round_robin_2);
>+		val64 = 0x0001020001000001ULL;
>+		writeq(val64, &bar0->tx_w_round_robin_3);
>+		val64 = 0x0203000100000000ULL;
>+		writeq(val64, &bar0->tx_w_round_robin_4);
>+		break;
>+	case 5:
>+		val64 = 0x0001000203000102ULL;
>+		writeq(val64, &bar0->tx_w_round_robin_0);
>+		val64 = 0x0001020001030004ULL;
>+		writeq(val64, &bar0->tx_w_round_robin_1);
>+		val64 = 0x0001000203000102ULL;
>+		writeq(val64, &bar0->tx_w_round_robin_2);
>+		val64 = 0x0001020001030004ULL;
>+		writeq(val64, &bar0->tx_w_round_robin_3);
>+		val64 = 0x0001000000000000ULL;
>+		writeq(val64, &bar0->tx_w_round_robin_4);
>+		break;
>+	case 6:
>+		val64 = 0x0001020304000102ULL;
>+		writeq(val64, &bar0->tx_w_round_robin_0);
>+		val64 = 0x0304050001020001ULL;
>+		writeq(val64, &bar0->tx_w_round_robin_1);
>+		val64 = 0x0203000100000102ULL;
>+		writeq(val64, &bar0->tx_w_round_robin_2);
>+		val64 = 0x0304000102030405ULL;
>+		writeq(val64, &bar0->tx_w_round_robin_3);
>+		val64 = 0x0001000200000000ULL;
>+		writeq(val64, &bar0->tx_w_round_robin_4);
>+		break;
>+	case 7:
>+		val64 = 0x0001020001020300ULL;
>+		writeq(val64, &bar0->tx_w_round_robin_0);
>+		val64 = 0x0102030400010203ULL;
>+		writeq(val64, &bar0->tx_w_round_robin_1);
>+		val64 = 0x0405060001020001ULL;
>+		writeq(val64, &bar0->tx_w_round_robin_2);
>+		val64 = 0x0304050000010200ULL;
>+		writeq(val64, &bar0->tx_w_round_robin_3);
>+		val64 = 0x0102030000000000ULL;
>+		writeq(val64, &bar0->tx_w_round_robin_4);
>+		break;
>+	case 8:
>+		val64 = 0x0001020300040105ULL;
>+		writeq(val64, &bar0->tx_w_round_robin_0);
>+		val64 = 0x0200030106000204ULL;
>+		writeq(val64, &bar0->tx_w_round_robin_1);
>+		val64 = 0x0103000502010007ULL;
>+		writeq(val64, &bar0->tx_w_round_robin_2);
>+		val64 = 0x0304010002060500ULL;
>+		writeq(val64, &bar0->tx_w_round_robin_3);
>+		val64 = 0x0103020400000000ULL;
>+		writeq(val64, &bar0->tx_w_round_robin_4);
>+		break;
>+	}
>+
>+	/* Filling the Rx round robin registers as per the
>+	 * number of Rings and steering based on QoS.
>+         */
>+	switch (config->rx_ring_num) {
>+	case 1:
> 		val64 = 0x8080808080808080ULL;
> 		writeq(val64, &bar0->rts_qos_steering);
>+		break;
>+	case 2:
>+		val64 = 0x0000010000010000ULL;
>+		writeq(val64, &bar0->rx_w_round_robin_0);
>+		val64 = 0x0100000100000100ULL;
>+		writeq(val64, &bar0->rx_w_round_robin_1);
>+		val64 = 0x0001000001000001ULL;
>+		writeq(val64, &bar0->rx_w_round_robin_2);
>+		val64 = 0x0000010000010000ULL;
>+		writeq(val64, &bar0->rx_w_round_robin_3);
>+		val64 = 0x0100000000000000ULL;
>+		writeq(val64, &bar0->rx_w_round_robin_4);
>+
>+		val64 = 0x8080808040404040ULL;
>+		writeq(val64, &bar0->rts_qos_steering);
>+		break;
>+	case 3:
>+		val64 = 0x0001000102000001ULL;
>+		writeq(val64, &bar0->rx_w_round_robin_0);
>+		val64 = 0x0001020000010001ULL;
>+		writeq(val64, &bar0->rx_w_round_robin_1);
>+		val64 = 0x0200000100010200ULL;
>+		writeq(val64, &bar0->rx_w_round_robin_2);
>+		val64 = 0x0001000102000001ULL;
>+		writeq(val64, &bar0->rx_w_round_robin_3);
>+		val64 = 0x0001020000000000ULL;
>+		writeq(val64, &bar0->rx_w_round_robin_4);
>+
>+		val64 = 0x8080804040402020ULL;
>+		writeq(val64, &bar0->rts_qos_steering);
>+		break;
>+	case 4:
>+		val64 = 0x0001020300010200ULL;
>+		writeq(val64, &bar0->rx_w_round_robin_0);
>+		val64 = 0x0100000102030001ULL;
>+		writeq(val64, &bar0->rx_w_round_robin_1);
>+		val64 = 0x0200010000010203ULL;
>+		writeq(val64, &bar0->rx_w_round_robin_2);
>+		val64 = 0x0001020001000001ULL;	
>+		writeq(val64, &bar0->rx_w_round_robin_3);
>+		val64 = 0x0203000100000000ULL;
>+		writeq(val64, &bar0->rx_w_round_robin_4);
>+
>+		val64 = 0x8080404020201010ULL;
>+		writeq(val64, &bar0->rts_qos_steering);
>+		break;
>+	case 5:
>+		val64 = 0x0001000203000102ULL;
>+		writeq(val64, &bar0->rx_w_round_robin_0);
>+		val64 = 0x0001020001030004ULL;
>+		writeq(val64, &bar0->rx_w_round_robin_1);
>+		val64 = 0x0001000203000102ULL;
>+		writeq(val64, &bar0->rx_w_round_robin_2);
>+		val64 = 0x0001020001030004ULL;
>+		writeq(val64, &bar0->rx_w_round_robin_3);
>+		val64 = 0x0001000000000000ULL;
>+		writeq(val64, &bar0->rx_w_round_robin_4);
>+
>+		val64 = 0x8080404020201008ULL;
>+		writeq(val64, &bar0->rts_qos_steering);
>+		break;
>+	case 6:
>+		val64 = 0x0001020304000102ULL;
>+		writeq(val64, &bar0->rx_w_round_robin_0);
>+		val64 = 0x0304050001020001ULL;
>+		writeq(val64, &bar0->rx_w_round_robin_1);
>+		val64 = 0x0203000100000102ULL;
>+		writeq(val64, &bar0->rx_w_round_robin_2);
>+		val64 = 0x0304000102030405ULL;
>+		writeq(val64, &bar0->rx_w_round_robin_3);
>+		val64 = 0x0001000200000000ULL;
>+		writeq(val64, &bar0->rx_w_round_robin_4);
>+
>+		val64 = 0x8080404020100804ULL;
>+		writeq(val64, &bar0->rts_qos_steering);
>+		break;
>+	case 7:
>+		val64 = 0x0001020001020300ULL;
>+		writeq(val64, &bar0->rx_w_round_robin_0);
>+		val64 = 0x0102030400010203ULL;
>+		writeq(val64, &bar0->rx_w_round_robin_1);
>+		val64 = 0x0405060001020001ULL;
>+		writeq(val64, &bar0->rx_w_round_robin_2);
>+		val64 = 0x0304050000010200ULL;
>+		writeq(val64, &bar0->rx_w_round_robin_3);
>+		val64 = 0x0102030000000000ULL;
>+		writeq(val64, &bar0->rx_w_round_robin_4);
>+
>+		val64 = 0x8080402010080402ULL;
>+		writeq(val64, &bar0->rts_qos_steering);
>+		break;
>+	case 8:
>+		val64 = 0x0001020300040105ULL;
>+		writeq(val64, &bar0->rx_w_round_robin_0);
>+		val64 = 0x0200030106000204ULL;
>+		writeq(val64, &bar0->rx_w_round_robin_1);
>+		val64 = 0x0103000502010007ULL;
>+		writeq(val64, &bar0->rx_w_round_robin_2);
>+		val64 = 0x0304010002060500ULL;
>+		writeq(val64, &bar0->rx_w_round_robin_3);
>+		val64 = 0x0103020400000000ULL;
>+		writeq(val64, &bar0->rx_w_round_robin_4);
>+
>+		val64 = 0x8040201008040201ULL;
>+		writeq(val64, &bar0->rts_qos_steering);
>+		break;
> 	}
> 
> 	/* UDP Fix */
> 	val64 = 0;
>-	for (i = 1; i < 8; i++)
>+	for (i = 0; i < 8; i++)
>+		writeq(val64, &bar0->rts_frm_len_n[i]);
>+
>+	/* Set the default rts frame length for the rings configured */
>+	val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
>+	for (i = 0 ; i < config->rx_ring_num ; i++)
> 		writeq(val64, &bar0->rts_frm_len_n[i]);
> 
>-	/* Set rts_frm_len register for fifo 0 */
>-	writeq(MAC_RTS_FRM_LEN_SET(dev->mtu + 22),
>-	       &bar0->rts_frm_len_n[0]);
>+	/* Set the frame length for the configured rings
>+	 * desired by the user
>+	 */
>+	for (i = 0; i < config->rx_ring_num; i++) {
>+		/* If rts_frm_len[i] == 0 then it is assumed that user not
>+		 * specified frame length steering.
>+		 * If the user provides the frame length then program
>+		 * the rts_frm_len register for those values or else
>+		 * leave it as it is.
>+		 */
>+		if (rts_frm_len[i] != 0) {
>+			writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
>+				&bar0->rts_frm_len_n[i]);
>+		}
>+	}
> 
>-	/* Enable statistics */
>+	/* Program statistics memory */
> 	writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
>-	val64 = SET_UPDT_PERIOD(Stats_refresh_time) |
>-	    STAT_CFG_STAT_RO | STAT_CFG_STAT_EN;
>-	writeq(val64, &bar0->stat_cfg);
> 
>-	/* 
>+	if (nic->device_type == XFRAME_II_DEVICE) {
>+		val64 = STAT_BC(0x320);
>+		writeq(val64, &bar0->stat_byte_cnt);
>+	}
>+
>+	/*
> 	 * Initializing the sampling rate for the device to calculate the
> 	 * bandwidth utilization.
> 	 */
>@@ -966,29 +1295,38 @@ static int init_nic(struct s2io_nic *nic
> 	writeq(val64, &bar0->mac_link_util);
> 
> 
>-	/* 
>-	 * Initializing the Transmit and Receive Traffic Interrupt 
>+	/*
>+	 * Initializing the Transmit and Receive Traffic Interrupt
> 	 * Scheme.
> 	 */
>-	/* TTI Initialization */
>-	val64 = TTI_DATA1_MEM_TX_TIMER_VAL(tx_timer_val) |
>-	    TTI_DATA1_MEM_TX_URNG_A(tx_urange_a) |
>-	    TTI_DATA1_MEM_TX_URNG_B(tx_urange_b) |
>-	    TTI_DATA1_MEM_TX_URNG_C(tx_urange_c);
>-	if (tx_utilz_periodic)
>-		val64 |= TTI_DATA1_MEM_TX_TIMER_AC_EN;
>+	/*
>+	 * TTI Initialization. Default Tx timer gets us about
>+	 * 250 interrupts per sec. Continuous interrupts are enabled
>+	 * by default.
>+	 */
>+	if (nic->device_type == XFRAME_II_DEVICE) {
>+		int count = (nic->config.bus_speed * 125)/2;
>+		val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
>+	} else {
>+
>+		val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
>+	}
>+	val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
>+	    TTI_DATA1_MEM_TX_URNG_B(0x10) |
>+	    TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN;
>+		if (use_continuous_tx_intrs)
>+			val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
> 	writeq(val64, &bar0->tti_data1_mem);
> 
>-	val64 = TTI_DATA2_MEM_TX_UFC_A(tx_ufc_a) |
>-	    TTI_DATA2_MEM_TX_UFC_B(tx_ufc_b) |
>-	    TTI_DATA2_MEM_TX_UFC_C(tx_ufc_c) |
>-	    TTI_DATA2_MEM_TX_UFC_D(tx_ufc_d);
>+	val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
>+	    TTI_DATA2_MEM_TX_UFC_B(0x20) |
>+	    TTI_DATA2_MEM_TX_UFC_C(0x70) | TTI_DATA2_MEM_TX_UFC_D(0x80);
> 	writeq(val64, &bar0->tti_data2_mem);
> 
> 	val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
> 	writeq(val64, &bar0->tti_command_mem);
> 
>-	/* 
>+	/*
> 	 * Once the operation completes, the Strobe bit of the command
> 	 * register will be reset. We poll for this particular condition
> 	 * We wait for a maximum of 500ms for the operation to complete,
>@@ -1005,54 +1343,94 @@ static int init_nic(struct s2io_nic *nic
> 				  dev->name);
> 			return -1;
> 		}
>-		set_current_state(TASK_UNINTERRUPTIBLE);
>-		schedule_timeout(HZ / 20);
>+		msleep(50);
> 		time++;
> 	}
> 
>-	/* RTI Initialization */
>-	val64 = RTI_DATA1_MEM_RX_TIMER_VAL(rx_timer_val) |
>-	    RTI_DATA1_MEM_RX_URNG_A(rx_urange_a) |
>-	    RTI_DATA1_MEM_RX_URNG_B(rx_urange_b) |
>-	    RTI_DATA1_MEM_RX_URNG_C(rx_urange_c);
>-	if (rx_utilz_periodic)
>-		val64 |= RTI_DATA1_MEM_RX_TIMER_AC_EN;
>-
>-	writeq(val64, &bar0->rti_data1_mem);
>-
>-	val64 = RTI_DATA2_MEM_RX_UFC_A(rx_ufc_a) |
>-	    RTI_DATA2_MEM_RX_UFC_B(rx_ufc_b) |
>-	    RTI_DATA2_MEM_RX_UFC_C(rx_ufc_c) |
>-	    RTI_DATA2_MEM_RX_UFC_D(rx_ufc_d);
>-	writeq(val64, &bar0->rti_data2_mem);
>-
>-	val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD;
>-	writeq(val64, &bar0->rti_command_mem);
>+	if (nic->config.bimodal) {
>+		int k = 0;
>+		for (k = 0; k < config->rx_ring_num; k++) {
>+			val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
>+			val64 |= TTI_CMD_MEM_OFFSET(0x38+k);
>+			writeq(val64, &bar0->tti_command_mem);
>+
>+		/*
>+		 * Once the operation completes, the Strobe bit of the command
>+		 * register will be reset. We poll for this particular condition
>+		 * We wait for a maximum of 500ms for the operation to complete,
>+		 * if it's not complete by then we return error.
>+		*/
>+			time = 0;
>+			while (TRUE) {
>+				val64 = readq(&bar0->tti_command_mem);
>+				if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
>+					break;
>+				}
>+				if (time > 10) {
>+					DBG_PRINT(ERR_DBG,
>+						"%s: TTI init Failed\n",
>+					dev->name);
>+					return -1;
>+				}
>+				time++;
>+				msleep(50);
>+			}
>+		}
>+	} else {
> 
>-	/* 
>-	 * Once the operation completes, the Strobe bit of the command
>-	 * register will be reset. We poll for this particular condition
>-	 * We wait for a maximum of 500ms for the operation to complete,
>-	 * if it's not complete by then we return error.
>-	 */
>-	time = 0;
>-	while (TRUE) {
>-		val64 = readq(&bar0->rti_command_mem);
>-		if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
>-			break;
>+		/* RTI Initialization */
>+		if (nic->device_type == XFRAME_II_DEVICE) {
>+			/*
>+			 * Programmed to generate Apprx 500 Intrs per
>+			 * second
>+			 */
>+			int count = (nic->config.bus_speed * 125)/4;
>+			val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
>+		} else {
>+			val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
> 		}
>-		if (time > 10) {
>-			DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
>-				  dev->name);
>-			return -1;
>+		val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
>+		    RTI_DATA1_MEM_RX_URNG_B(0x10) |
>+		    RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
>+
>+		writeq(val64, &bar0->rti_data1_mem);
>+
>+		val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
>+		    RTI_DATA2_MEM_RX_UFC_B(0x2) |
>+		    RTI_DATA2_MEM_RX_UFC_C(0x40) | RTI_DATA2_MEM_RX_UFC_D(0x80);
>+		writeq(val64, &bar0->rti_data2_mem);
>+
>+		for (i = 0; i < config->rx_ring_num; i++) {
>+			val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
>+					| RTI_CMD_MEM_OFFSET(i);
>+			writeq(val64, &bar0->rti_command_mem);
>+
>+			/*
>+			 * Once the operation completes, the Strobe bit of the
>+			 * command register will be reset. We poll for this
>+			 * particular condition. We wait for a maximum of 500ms
>+			 * for the operation to complete, if it's not complete
>+			 * by then we return error.
>+			 */
>+			time = 0;
>+			while (TRUE) {
>+				val64 = readq(&bar0->rti_command_mem);
>+				if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD)) {
>+					break;
>+				}
>+				if (time > 10) {
>+					DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
>+						  dev->name);
>+					return -1;
>+				}
>+				time++;
>+				msleep(50);
>+			}
> 		}
>-		time++;
>-		set_current_state(TASK_UNINTERRUPTIBLE);
>-		schedule_timeout(HZ / 20);
> 	}
> 
>-	/* 
>-	 * Initializing proper values as Pause threshold into all 
>+	/*
>+	 * Initializing proper values as Pause threshold into all
> 	 * the 8 Queues on Rx side.
> 	 */
> 	writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
>@@ -1068,8 +1446,8 @@ static int init_nic(struct s2io_nic *nic
> 	writel((u32) (val64 >> 32), (add + 4));
> 	val64 = readq(&bar0->mac_cfg);
> 
>-	/* 
>-	 * Set the time value to be inserted in the pause frame 
>+	/*
>+	 * Set the time value to be inserted in the pause frame
> 	 * generated by xena.
> 	 */
> 	val64 = readq(&bar0->rmac_pause_cfg);
>@@ -1077,7 +1455,7 @@ static int init_nic(struct s2io_nic *nic
> 	val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
> 	writeq(val64, &bar0->rmac_pause_cfg);
> 
>-	/* 
>+	/*
> 	 * Set the Threshold Limit for Generating the pause frame
> 	 * If the amount of data in any Queue exceeds ratio of
> 	 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
>@@ -1101,31 +1479,60 @@ static int init_nic(struct s2io_nic *nic
> 	}
> 	writeq(val64, &bar0->mc_pause_thresh_q4q7);
> 
>-	/* 
>-	 * TxDMA will stop Read request if the number of read split has 
>+	/*
>+	 * TxDMA will stop Read request if the number of read split has
> 	 * exceeded the limit pointed by shared_splits
> 	 */
> 	val64 = readq(&bar0->pic_control);
> 	val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
> 	writeq(val64, &bar0->pic_control);
> 
>+	/*
>+	 * Programming the Herc to split every write transaction
>+	 * that does not start on an ADB to reduce disconnects.
>+	 */
>+	if (nic->device_type == XFRAME_II_DEVICE) {
>+		val64 = WREQ_SPLIT_MASK_SET_MASK(255);
>+		writeq(val64, &bar0->wreq_split_mask);
>+	}
>+
>+	/* Setting Link stability period to 64 ms */ 
>+	if (nic->device_type == XFRAME_II_DEVICE) {
>+		val64 = MISC_LINK_STABILITY_PRD(3);
>+		writeq(val64, &bar0->misc_control);
>+	}
>+
> 	return SUCCESS;
> }
>+#define LINK_UP_DOWN_INTERRUPT		1
>+#define MAC_RMAC_ERR_TIMER		2
> 
>-/**  
>- *  en_dis_able_nic_intrs - Enable or Disable the interrupts 
>- *  @nic: device private variable,
>+#if defined(CONFIG_MSI_MODE) || defined(CONFIG_MSIX_MODE)
>+#define s2io_link_fault_indication(x) MAC_RMAC_ERR_TIMER
>+#else
>+int s2io_link_fault_indication(nic_t *nic)
>+{
>+	if (nic->device_type == XFRAME_II_DEVICE)
>+		return LINK_UP_DOWN_INTERRUPT;
>+	else
>+		return MAC_RMAC_ERR_TIMER;
>+}
>+#endif
>+
>+/**
>+ *  en_dis_able_nic_intrs - Enable or Disable the interrupts
>+ *  @nic: device private variable,
>  *  @mask: A mask indicating which Intr block must be modified and,
>  *  @flag: A flag indicating whether to enable or disable the Intrs.
>  *  Description: This function will either disable or enable the interrupts
>- *  depending on the flag argument. The mask argument can be used to 
>- *  enable/disable any Intr block. 
>+ *  depending on the flag argument. The mask argument can be used to
>+ *  enable/disable any Intr block.
>  *  Return Value: NONE.
>  */
> 
> static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
> {
>-	XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
>+	XENA_dev_config_t __iomem *bar0 = nic->bar0;
> 	register u64 val64 = 0, temp64 = 0;
> 
> 	/*  Top level interrupt classification */
>@@ -1137,20 +1544,31 @@ static void en_dis_able_nic_intrs(struct
> 			temp64 = readq(&bar0->general_int_mask);
> 			temp64 &= ~((u64) val64);
> 			writeq(temp64, &bar0->general_int_mask);
>-			/*  
>-			 * Disabled all PCIX, Flash, MDIO, IIC and GPIO
>-			 * interrupts for now. 
>-			 * TODO 
>+			/*
>+			 * If Hercules adapter enable GPIO otherwise
>+			 * disabled all PCIX, Flash, MDIO, IIC and GPIO
>+			 * interrupts for now.
>+			 * TODO
> 			 */
>-			writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
>-			/* 
>+			if (s2io_link_fault_indication(nic) ==
>+					LINK_UP_DOWN_INTERRUPT ) {
>+				temp64 = readq(&bar0->pic_int_mask);
>+				temp64 &= ~((u64) PIC_INT_GPIO);
>+				writeq(temp64, &bar0->pic_int_mask);
>+				temp64 = readq(&bar0->gpio_int_mask);
>+				temp64 &= ~((u64) GPIO_INT_MASK_LINK_UP);
>+				writeq(temp64, &bar0->gpio_int_mask);
>+			} else {
>+				writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
>+			}
>+			/*
> 			 * No MSI Support is available presently, so TTI and
> 			 * RTI interrupts are also disabled.
> 			 */
> 		} else if (flag == DISABLE_INTRS) {
>-			/*  
>-			 * Disable PIC Intrs in the general 
>-			 * intr mask register 
>+			/*
>+			 * Disable PIC Intrs in the general
>+			 * intr mask register
> 			 */
> 			writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
> 			temp64 = readq(&bar0->general_int_mask);
>@@ -1168,27 +1586,27 @@ static void en_dis_able_nic_intrs(struct
> 			temp64 = readq(&bar0->general_int_mask);
> 			temp64 &= ~((u64) val64);
> 			writeq(temp64, &bar0->general_int_mask);
>-			/* 
>-			 * Keep all interrupts other than PFC interrupt 
>+			/*
>+			 * Keep all interrupts other than PFC interrupt
> 			 * and PCC interrupt disabled in DMA level.
> 			 */
> 			val64 = DISABLE_ALL_INTRS & ~(TXDMA_PFC_INT_M |
> 						      TXDMA_PCC_INT_M);
> 			writeq(val64, &bar0->txdma_int_mask);
>-			/* 
>-			 * Enable only the MISC error 1 interrupt in PFC block 
>+			/*
>+			 * Enable only the MISC error 1 interrupt in PFC block
> 			 */
> 			val64 = DISABLE_ALL_INTRS & (~PFC_MISC_ERR_1);
> 			writeq(val64, &bar0->pfc_err_mask);
>-			/* 
>-			 * Enable only the FB_ECC error interrupt in PCC block 
>+			/*
>+			 * Enable only the FB_ECC error interrupt in PCC block
> 			 */
> 			val64 = DISABLE_ALL_INTRS & (~PCC_FB_ECC_ERR);
> 			writeq(val64, &bar0->pcc_err_mask);
> 		} else if (flag == DISABLE_INTRS) {
>-			/* 
>-			 * Disable TxDMA Intrs in the general intr mask 
>-			 * register 
>+			/*
>+			 * Disable TxDMA Intrs in the general intr mask
>+			 * register
> 			 */
> 			writeq(DISABLE_ALL_INTRS, &bar0->txdma_int_mask);
> 			writeq(DISABLE_ALL_INTRS, &bar0->pfc_err_mask);
>@@ -1206,15 +1624,15 @@ static void en_dis_able_nic_intrs(struct
> 			temp64 = readq(&bar0->general_int_mask);
> 			temp64 &= ~((u64) val64);
> 			writeq(temp64, &bar0->general_int_mask);
>-			/* 
>-			 * All RxDMA block interrupts are disabled for now 
>-			 * TODO 
>+			/*
>+			 * All RxDMA block interrupts are disabled for now
>+			 * TODO
> 			 */
> 			writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);
> 		} else if (flag == DISABLE_INTRS) {
>-			/*  
>-			 * Disable RxDMA Intrs in the general intr mask 
>-			 * register 
>+			/*
>+			 * Disable RxDMA Intrs in the general intr mask
>+			 * register
> 			 */
> 			writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);
> 			temp64 = readq(&bar0->general_int_mask);
>@@ -1231,22 +1649,13 @@ static void en_dis_able_nic_intrs(struct
> 			temp64 = readq(&bar0->general_int_mask);
> 			temp64 &= ~((u64) val64);
> 			writeq(temp64, &bar0->general_int_mask);
>-			/* 
>-			 * All MAC block error interrupts are disabled for now 
>-			 * except the link status change interrupt.
>+			/*
>+			 * All MAC block error interrupts are disabled for now
> 			 * TODO
> 			 */
>-			val64 = MAC_INT_STATUS_RMAC_INT;
>-			temp64 = readq(&bar0->mac_int_mask);
>-			temp64 &= ~((u64) val64);
>-			writeq(temp64, &bar0->mac_int_mask);
>-
>-			val64 = readq(&bar0->mac_rmac_err_mask);
>-			val64 &= ~((u64) RMAC_LINK_STATE_CHANGE_INT);
>-			writeq(val64, &bar0->mac_rmac_err_mask);
> 		} else if (flag == DISABLE_INTRS) {
>-			/*  
>-			 * Disable MAC Intrs in the general intr mask register 
>+			/*
>+			 * Disable MAC Intrs in the general intr mask register
> 			 */
> 			writeq(DISABLE_ALL_INTRS, &bar0->mac_int_mask);
> 			writeq(DISABLE_ALL_INTRS,
>@@ -1265,14 +1674,14 @@ static void en_dis_able_nic_intrs(struct
> 			temp64 = readq(&bar0->general_int_mask);
> 			temp64 &= ~((u64) val64);
> 			writeq(temp64, &bar0->general_int_mask);
>-			/* 
>+			/*
> 			 * All XGXS block error interrupts are disabled for now
>-			 * TODO 
>+			 * TODO
> 			 */
> 			writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);
> 		} else if (flag == DISABLE_INTRS) {
>-			/*  
>-			 * Disable MC Intrs in the general intr mask register 
>+			/*
>+			 * Disable MC Intrs in the general intr mask register
> 			 */
> 			writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);
> 			temp64 = readq(&bar0->general_int_mask);
>@@ -1288,11 +1697,11 @@ static void en_dis_able_nic_intrs(struct
> 			temp64 = readq(&bar0->general_int_mask);
> 			temp64 &= ~((u64) val64);
> 			writeq(temp64, &bar0->general_int_mask);
>-			/* 
>-			 * All MC block error interrupts are disabled for now
>-			 * TODO 
>+			/*
>+			 * Enable all MC Intrs.
> 			 */
>-			writeq(DISABLE_ALL_INTRS, &bar0->mc_int_mask);
>+			writeq(0x0, &bar0->mc_int_mask);
>+			writeq(0x0, &bar0->mc_err_mask);
> 		} else if (flag == DISABLE_INTRS) {
> 			/*
> 			 * Disable MC Intrs in the general intr mask register
>@@ -1312,14 +1721,14 @@ static void en_dis_able_nic_intrs(struct
> 			temp64 = readq(&bar0->general_int_mask);
> 			temp64 &= ~((u64) val64);
> 			writeq(temp64, &bar0->general_int_mask);
>-			/* 
>+			/*
> 			 * Enable all the Tx side interrupts
>-			 * writing 0 Enables all 64 TX interrupt levels 
>+			 * writing 0 Enables all 64 TX interrupt levels
> 			 */
> 			writeq(0x0, &bar0->tx_traffic_mask);
> 		} else if (flag == DISABLE_INTRS) {
>-			/* 
>-			 * Disable Tx Traffic Intrs in the general intr mask 
>+			/*
>+			 * Disable Tx Traffic Intrs in the general intr mask
> 			 * register.
> 			 */
> 			writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
>@@ -1339,8 +1748,8 @@ static void en_dis_able_nic_intrs(struct
> 			/* writing 0 Enables all 8 RX interrupt levels */
> 			writeq(0x0, &bar0->rx_traffic_mask);
> 		} else if (flag == DISABLE_INTRS) {
>-			/*  
>-			 * Disable Rx Traffic Intrs in the general intr mask 
>+			/*
>+			 * Disable Rx Traffic Intrs in the general intr mask
> 			 * register.
> 			 */
> 			writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
>@@ -1351,24 +1760,66 @@ static void en_dis_able_nic_intrs(struct
> 	}
> }
> 
>-/**  
>- *  verify_xena_quiescence - Checks whether the H/W is ready 
>+static int check_prc_pcc_state(u64 val64, int flag, int rev_id, int herc)
>+{
>+	int ret = 0;
>+
>+	if (flag == FALSE) {
>+		if ((!herc && (rev_id >= 4)) || herc) {
>+			if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) &&
>+			    ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
>+			     ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
>+				ret = 1;
>+			}
>+		}else {
>+			if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) &&
>+			    ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
>+			     ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
>+				ret = 1;
>+			}
>+		}
>+	} else {
>+		if ((!herc && (rev_id >= 4)) || herc) {
>+			if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
>+			     ADAPTER_STATUS_RMAC_PCC_IDLE) &&
>+			    (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ||
>+			     ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
>+			      ADAPTER_STATUS_RC_PRC_QUIESCENT))) {
>+				ret = 1;
>+			}
>+		} else {
>+			if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
>+			     ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) &&
>+			    (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ||
>+			     ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
>+			      ADAPTER_STATUS_RC_PRC_QUIESCENT))) {
>+				ret = 1;
>+			}
>+		}
>+	}
>+
>+	return ret;
>+}
>+/**
>+ *  verify_xena_quiescence - Checks whether the H/W is ready
>  *  @val64 :  Value read from adapter status register.
>  *  @flag : indicates if the adapter enable bit was ever written once
>  *  before.
>  *  Description: Returns whether the H/W is ready to go or not. Depending
>- *  on whether adapter enable bit was written or not the comparison 
>+ *  on whether adapter enable bit was written or not the comparison
>  *  differs and the calling function passes the input argument flag to
>  *  indicate this.
>- *  Return: 1 If xena is quiescence 
>+ *  Return: 1 If xena is quiescence
>  *          0 If Xena is not quiescence
>  */
> 
>-static int verify_xena_quiescence(u64 val64, int flag)
>+static int verify_xena_quiescence(nic_t *sp, u64 val64, int flag)
> {
>-	int ret = 0;
>+	int ret = 0, herc;
> 	u64 tmp64 = ~((u64) val64);
>+	int rev_id = get_xena_rev_id(sp->pdev);
> 
>+	herc = (sp->device_type == XFRAME_II_DEVICE);
> 	if (!
> 	    (tmp64 &
> 	     (ADAPTER_STATUS_TDMA_READY | ADAPTER_STATUS_RDMA_READY |
>@@ -1376,25 +1827,7 @@ static int verify_xena_quiescence(u64 va
> 	      ADAPTER_STATUS_PIC_QUIESCENT | ADAPTER_STATUS_MC_DRAM_READY |
> 	      ADAPTER_STATUS_MC_QUEUES_READY | ADAPTER_STATUS_M_PLL_LOCK |
> 	      ADAPTER_STATUS_P_PLL_LOCK))) {
>-		if (flag == FALSE) {
>-			if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) &&
>-			    ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
>-			     ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
>-
>-				ret = 1;
>-
>-			}
>-		} else {
>-			if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
>-			     ADAPTER_STATUS_RMAC_PCC_IDLE) &&
>-			    (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ||
>-			     ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
>-			      ADAPTER_STATUS_RC_PRC_QUIESCENT))) {
>-
>-				ret = 1;
>-
>-			}
>-		}
>+		ret = check_prc_pcc_state(val64, flag, rev_id, herc);
> 	}
> 
> 	return ret;
>@@ -1403,43 +1836,44 @@ static int verify_xena_quiescence(u64 va
> /**
>  * fix_mac_address -  Fix for Mac addr problem on Alpha platforms
>  * @sp: Pointer to device specifc structure
>- * Description : 
>+ * Description :
>  * New procedure to clear mac address reading  problems on Alpha platforms
>  *
>  */
> 
> void fix_mac_address(nic_t * sp)
> {
>-	XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
>+	XENA_dev_config_t __iomem *bar0 = sp->bar0;
> 	u64 val64;
> 	int i = 0;
> 
> 	while (fix_mac[i] != END_SIGN) {
> 		writeq(fix_mac[i++], &bar0->gpio_control);
>+		udelay(10);
> 		val64 = readq(&bar0->gpio_control);
> 	}
> }
> 
> /**
>- *  start_nic - Turns the device on   
>+ *  start_nic - Turns the device on
>  *  @nic : device private variable.
>- *  Description: 
>- *  This function actually turns the device on. Before this  function is 
>- *  called,all Registers are configured from their reset states 
>- *  and shared memory is allocated but the NIC is still quiescent. On 
>+ *  Description:
>+ *  This function actually turns the device on. Before this  function is
>+ *  called,all Registers are configured from their reset states
>+ *  and shared memory is allocated but the NIC is still quiescent. On
>  *  calling this function, the device interrupts are cleared and the NIC is
>  *  literally switched on by writing into the adapter control register.
>- *  Return Value: 
>+ *  Return Value:
>  *  SUCCESS on success and -1 on failure.
>  */
> 
> static int start_nic(struct s2io_nic *nic)
> {
>-	XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
>+	XENA_dev_config_t __iomem *bar0 = nic->bar0;
> 	struct net_device *dev = nic->dev;
> 	register u64 val64 = 0;
>-	u16 interruptible, i;
>-	u16 subid;
>+	u16 interruptible;
>+	u16 subid, i;
> 	mac_info_t *mac_control;
> 	struct config_param *config;
> 
>@@ -1447,11 +1881,13 @@ static int start_nic(struct s2io_nic *ni
> 	config = &nic->config;
> 
> 	/*  PRC Initialization and configuration */
>-	for (i = 0; i < config->RxRingNum; i++) {
>-		writeq((u64) nic->rx_blocks[i][0].block_dma_addr,
>+	for (i = 0; i < config->rx_ring_num; i++) {
>+		writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,
> 		       &bar0->prc_rxd0_n[i]);
> 
> 		val64 = readq(&bar0->prc_ctrl_n[i]);
>+		if (nic->config.bimodal)
>+			val64 |= PRC_CTRL_BIMODAL_INTERRUPT;
> #ifndef CONFIG_2BUFF_MODE
> 		val64 |= PRC_CTRL_RC_ENABLED;
> #else
>@@ -1467,7 +1903,7 @@ static int start_nic(struct s2io_nic *ni
> 	writeq(val64, &bar0->rx_pa_cfg);
> #endif
> 
>-	/* 
>+	/*
> 	 * Enabling MC-RLDRAM. After enabling the device, we timeout
> 	 * for around 100ms, which is approximately the time required
> 	 * for the device to be ready for operation.
>@@ -1477,28 +1913,27 @@ static int start_nic(struct s2io_nic *ni
> 	SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
> 	val64 = readq(&bar0->mc_rldram_mrs);
> 
>-	set_current_state(TASK_UNINTERRUPTIBLE);
>-	schedule_timeout(HZ / 10);	/* Delay by around 100 ms. */
>+	msleep(100);	/* Delay by around 100 ms. */
> 
> 	/* Enabling ECC Protection. */
> 	val64 = readq(&bar0->adapter_control);
> 	val64 &= ~ADAPTER_ECC_EN;
> 	writeq(val64, &bar0->adapter_control);
> 
>-	/* 
>-	 * Clearing any possible Link state change interrupts that 
>+	/*
>+	 * Clearing any possible Link state change interrupts that
> 	 * could have popped up just before Enabling the card.
> 	 */
> 	val64 = readq(&bar0->mac_rmac_err_reg);
> 	if (val64)
> 		writeq(val64, &bar0->mac_rmac_err_reg);
> 
>-	/* 
>-	 * Verify if the device is ready to be enabled, if so enable 
>+	/*
>+	 * Verify if the device is ready to be enabled, if so enable
> 	 * it.
> 	 */
> 	val64 = readq(&bar0->adapter_status);
>-	if (!verify_xena_quiescence(val64, nic->device_enabled_once)) {
>+	if (!verify_xena_quiescence(nic, val64, nic->device_enabled_once)) {
> 		DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
> 		DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
> 			  (unsigned long long) val64);
>@@ -1506,16 +1941,18 @@ static int start_nic(struct s2io_nic *ni
> 	}
> 
> 	/*  Enable select interrupts */
>-	interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR | TX_MAC_INTR |
>-	    RX_MAC_INTR;
>+	interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
>+	interruptible |= TX_PIC_INTR | RX_PIC_INTR;
>+	interruptible |= TX_MAC_INTR | RX_MAC_INTR;
>+
> 	en_dis_able_nic_intrs(nic, interruptible, ENABLE_INTRS);
> 
>-	/* 
>+	/*
> 	 * With some switches, link might be already up at this point.
>-	 * Because of this weird behavior, when we enable laser, 
>-	 * we may not get link. We need to handle this. We cannot 
>-	 * figure out which switch is misbehaving. So we are forced to 
>-	 * make a global change. 
>+	 * Because of this weird behavior, when we enable laser,
>+	 * we may not get link. We need to handle this. We cannot
>+	 * figure out which switch is misbehaving. So we are forced to
>+	 * make a global change.
> 	 */
> 
> 	/* Enabling Laser. */
>@@ -1525,51 +1962,33 @@ static int start_nic(struct s2io_nic *ni
> 
> 	/* SXE-002: Initialize link and activity LED */
> 	subid = nic->pdev->subsystem_device;
>-	if ((subid & 0xFF) >= 0x07) {
>+	if (((subid & 0xFF) >= 0x07) &&
>+	    (nic->device_type == XFRAME_I_DEVICE)) {
> 		val64 = readq(&bar0->gpio_control);
> 		val64 |= 0x0000800000000000ULL;
> 		writeq(val64, &bar0->gpio_control);
> 		val64 = 0x0411040400000000ULL;
>-		writeq(val64, (void *) ((u8 *) bar0 + 0x2700));
>+		writeq(val64, (void __iomem *) ((u8 *) bar0 + 0x2700));
> 	}
> 
>-	/* 
>+	/*
> 	 * Don't see link state interrupts on certain switches, so
> 	 * directly scheduling a link state task from here.
> 	 */
>-#ifdef INIT_TQUEUE
>-	schedule_task(&nic->set_link_task);
>-#else
> 	schedule_work(&nic->set_link_task);
>-#endif
>-
>-	/* 
>-	 * Here we are performing soft reset on XGXS to 
>-	 * force link down. Since link is already up, we will get
>-	 * link state change interrupt after this reset
>-	 */
>-	SPECIAL_REG_WRITE(0x80010515001E0000ULL, &bar0->dtx_control, UF);
>-	val64 = readq(&bar0->dtx_control);
>-	udelay(50);
>-	SPECIAL_REG_WRITE(0x80010515001E00E0ULL, &bar0->dtx_control, UF);
>-	val64 = readq(&bar0->dtx_control);
>-	udelay(50);
>-	SPECIAL_REG_WRITE(0x80070515001F00E4ULL, &bar0->dtx_control, UF);
>-	val64 = readq(&bar0->dtx_control);
>-	udelay(50);
> 
> 	return SUCCESS;
> }
> 
>-/** 
>- *  free_tx_buffers - Free all queued Tx buffers 
>+/**
>+ *  free_tx_buffers - Free all queued Tx buffers
>  *  @nic : device private variable.
>- *  Description: 
>+ *  Description:
>  *  Free all queued Tx buffers.
>- *  Return Value: void 
>+ *  Return Value: void
> */
> 
>-void free_tx_buffers(struct s2io_nic *nic)
>+static void free_tx_buffers(struct s2io_nic *nic)
> {
> 	struct net_device *dev = nic->dev;
> 	struct sk_buff *skb;
>@@ -1577,39 +1996,61 @@ void free_tx_buffers(struct s2io_nic *ni
> 	int i, j;
> 	mac_info_t *mac_control;
> 	struct config_param *config;
>-	int cnt = 0;
>+	int cnt = 0, frg_cnt;
> 
> 	mac_control = &nic->mac_control;
> 	config = &nic->config;
> 
>-	for (i = 0; i < config->TxFIFONum; i++) {
>-		for (j = 0; j < config->tx_cfg[i].FifoLen - 1; j++) {
>-			txdp = (TxD_t *) nic->list_info[i][j].
>+	for (i = 0; i < config->tx_fifo_num; i++) {
>+		for (j = 0; j < config->tx_cfg[i].fifo_len - 1; j++) {
>+			txdp = (TxD_t *) mac_control->fifos[i].list_info[j].
> 			    list_virt_addr;
> 			skb =
> 			    (struct sk_buff *) ((unsigned long) txdp->
> 						Host_Control);
> 			if (skb == NULL) {
>-				memset(txdp, 0, sizeof(TxD_t));
>+				memset(txdp, 0, sizeof(TxD_t) *
>+				       config->max_txds);
> 				continue;
> 			}
>+			frg_cnt = skb_shinfo(skb)->nr_frags;
>+			pci_unmap_single(nic->pdev, (dma_addr_t)
>+					 txdp->Buffer_Pointer,
>+					 skb->len - skb->data_len,
>+					 PCI_DMA_TODEVICE);
>+			if (frg_cnt) {
>+				TxD_t *temp;
>+				temp = txdp;
>+				txdp++;
>+				for (j = 0; j < frg_cnt; j++, txdp++) {
>+					skb_frag_t *frag =
>+					    &skb_shinfo(skb)->frags[j];
>+					pci_unmap_page(nic->pdev,
>+						       (dma_addr_t)
>+						       txdp->
>+						       Buffer_Pointer,
>+						       frag->size,
>+						       PCI_DMA_TODEVICE);
>+				}
>+				txdp = temp;
>+			}
> 			dev_kfree_skb(skb);
>-			memset(txdp, 0, sizeof(TxD_t));
>+			memset(txdp, 0, sizeof(TxD_t) * config->max_txds);
> 			cnt++;
> 		}
> 		DBG_PRINT(INTR_DBG,
> 			  "%s:forcibly freeing %d skbs on FIFO%d\n",
> 			  dev->name, cnt, i);
>-		mac_control->tx_curr_get_info[i].offset = 0;
>-		mac_control->tx_curr_put_info[i].offset = 0;
>+		mac_control->fifos[i].tx_curr_get_info.offset = 0;
>+		mac_control->fifos[i].tx_curr_put_info.offset = 0;
> 	}
> }
> 
>-/**  
>- *   stop_nic -  To stop the nic  
>+/**
>+ *   stop_nic -  To stop the nic
>  *   @nic ; device private variable.
>- *   Description: 
>- *   This function does exactly the opposite of what the start_nic() 
>+ *   Description:
>+ *   This function does exactly the opposite of what the start_nic()
>  *   function does. This function is called to stop the device.
>  *   Return Value:
>  *   void.
>@@ -1617,7 +2058,7 @@ void free_tx_buffers(struct s2io_nic *ni
> 
> static void stop_nic(struct s2io_nic *nic)
> {
>-	XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
>+	XENA_dev_config_t __iomem *bar0 = nic->bar0;
> 	register u64 val64 = 0;
> 	u16 interruptible, i;
> 	mac_info_t *mac_control;
>@@ -1627,23 +2068,24 @@ static void stop_nic(struct s2io_nic *ni
> 	config = &nic->config;
> 
> 	/*  Disable all interrupts */
>-	interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR | TX_MAC_INTR |
>-	    RX_MAC_INTR;
>+	interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
>+	interruptible |= TX_PIC_INTR | RX_PIC_INTR;
>+	interruptible |= TX_MAC_INTR | RX_MAC_INTR;
> 	en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
> 
> 	/*  Disable PRCs */
>-	for (i = 0; i < config->RxRingNum; i++) {
>+	for (i = 0; i < config->rx_ring_num; i++) {
> 		val64 = readq(&bar0->prc_ctrl_n[i]);
> 		val64 &= ~((u64) PRC_CTRL_RC_ENABLED);
> 		writeq(val64, &bar0->prc_ctrl_n[i]);
> 	}
> }
> 
>-/**  
>- *  fill_rx_buffers - Allocates the Rx side skbs 
>+/**
>+ *  fill_rx_buffers - Allocates the Rx side skbs
>  *  @nic:  device private variable
>- *  @ring_no: ring number 
>- *  Description: 
>+ *  @ring_no: ring number
>+ *  Description:
>  *  The function allocates Rx side skbs and puts the physical
>  *  address of these buffers into the RxD buffer pointers, so that the NIC
>  *  can DMA the received frame into these locations.
>@@ -1651,8 +2093,8 @@ static void stop_nic(struct s2io_nic *ni
>  *  1. single buffer,
>  *  2. three buffer and
>  *  3. Five buffer modes.
>- *  Each mode defines how many fragments the received frame will be split 
>- *  up into by the NIC. The frame is split into L3 header, L4 Header, 
>+ *  Each mode defines how many fragments the received frame will be split
>+ *  up into by the NIC. The frame is split into L3 header, L4 Header,
>  *  L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
>  *  is split into 3 fragments. As of now only single buffer mode is
>  *  supported.
>@@ -1668,8 +2110,7 @@ int fill_rx_buffers(struct s2io_nic *nic
> 	int off, off1, size, block_no, block_no1;
> 	int offset, offset1;
> 	u32 alloc_tab = 0;
>-	u32 alloc_cnt = nic->pkt_cnt[ring_no] -
>-	    atomic_read(&nic->rx_bufs_left[ring_no]);
>+	u32 alloc_cnt;
> 	mac_info_t *mac_control;
> 	struct config_param *config;
> #ifdef CONFIG_2BUFF_MODE
>@@ -1682,27 +2123,22 @@ int fill_rx_buffers(struct s2io_nic *nic
> #ifndef CONFIG_S2IO_NAPI
> 	unsigned long flags;
> #endif
>+	RxD_t *first_rxdp = NULL;
> 
> 	mac_control = &nic->mac_control;
> 	config = &nic->config;
>-
>-	if (frame_len[ring_no]) {
>-		if (frame_len[ring_no] > dev->mtu)
>-			dev->mtu = frame_len[ring_no];
>-		size = frame_len[ring_no] + HEADER_ETHERNET_II_802_3_SIZE +
>-		    HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
>-	} else {
>-		size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
>-		    HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
>-	}
>+	alloc_cnt = mac_control->rings[ring_no].pkt_cnt -
>+	    atomic_read(&nic->rx_bufs_left[ring_no]);
>+	size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
>+	    HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
> 
> 	while (alloc_tab < alloc_cnt) {
>-		block_no = mac_control->rx_curr_put_info[ring_no].
>+		block_no = mac_control->rings[ring_no].rx_curr_put_info.
> 		    block_index;
>-		block_no1 = mac_control->rx_curr_get_info[ring_no].
>+		block_no1 = mac_control->rings[ring_no].rx_curr_get_info.
> 		    block_index;
>-		off = mac_control->rx_curr_put_info[ring_no].offset;
>-		off1 = mac_control->rx_curr_get_info[ring_no].offset;
>+		off = mac_control->rings[ring_no].rx_curr_put_info.offset;
>+		off1 = mac_control->rings[ring_no].rx_curr_get_info.offset;
> #ifndef CONFIG_2BUFF_MODE
> 		offset = block_no * (MAX_RXDS_PER_BLOCK + 1) + off;
> 		offset1 = block_no1 * (MAX_RXDS_PER_BLOCK + 1) + off1;
>@@ -1711,7 +2147,7 @@ int fill_rx_buffers(struct s2io_nic *nic
> 		offset1 = block_no1 * (MAX_RXDS_PER_BLOCK) + off1;
> #endif
> 
>-		rxdp = nic->rx_blocks[ring_no][block_no].
>+		rxdp = mac_control->rings[ring_no].rx_blocks[block_no].
> 		    block_virt_addr + off;
> 		if ((offset == offset1) && (rxdp->Host_Control)) {
> 			DBG_PRINT(INTR_DBG, "%s: Get and Put", dev->name);
>@@ -1720,15 +2156,15 @@ int fill_rx_buffers(struct s2io_nic *nic
> 		}
> #ifndef	CONFIG_2BUFF_MODE
> 		if (rxdp->Control_1 == END_OF_BLOCK) {
>-			mac_control->rx_curr_put_info[ring_no].
>+			mac_control->rings[ring_no].rx_curr_put_info.
> 			    block_index++;
>-			mac_control->rx_curr_put_info[ring_no].
>-			    block_index %= nic->block_count[ring_no];
>-			block_no = mac_control->rx_curr_put_info
>-			    [ring_no].block_index;
>+			mac_control->rings[ring_no].rx_curr_put_info.
>+			    block_index %= mac_control->rings[ring_no].block_count;
>+			block_no = mac_control->rings[ring_no].rx_curr_put_info.
>+				block_index;
> 			off++;
> 			off %= (MAX_RXDS_PER_BLOCK + 1);
>-			mac_control->rx_curr_put_info[ring_no].offset =
>+			mac_control->rings[ring_no].rx_curr_put_info.offset =
> 			    off;
> 			rxdp = (RxD_t *) ((unsigned long) rxdp->Control_2);
> 			DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
>@@ -1736,29 +2172,31 @@ int fill_rx_buffers(struct s2io_nic *nic
> 		}
> #ifndef CONFIG_S2IO_NAPI
> 		spin_lock_irqsave(&nic->put_lock, flags);
>-		nic->put_pos = (block_no * (MAX_RXDS_PER_BLOCK + 1)) + off;
>+		mac_control->rings[ring_no].put_pos =
>+		    (block_no * (MAX_RXDS_PER_BLOCK + 1)) + off;
> 		spin_unlock_irqrestore(&nic->put_lock, flags);
> #endif
> #else
> 		if (rxdp->Host_Control == END_OF_BLOCK) {
>-			mac_control->rx_curr_put_info[ring_no].
>+			mac_control->rings[ring_no].rx_curr_put_info.
> 			    block_index++;
>-			mac_control->rx_curr_put_info[ring_no].
>-			    block_index %= nic->block_count[ring_no];
>-			block_no = mac_control->rx_curr_put_info
>-			    [ring_no].block_index;
>+			mac_control->rings[ring_no].rx_curr_put_info.block_index
>+			    %= mac_control->rings[ring_no].block_count;
>+			block_no = mac_control->rings[ring_no].rx_curr_put_info
>+			    .block_index;
> 			off = 0;
> 			DBG_PRINT(INTR_DBG, "%s: block%d at: 0x%llx\n",
> 				  dev->name, block_no,
> 				  (unsigned long long) rxdp->Control_1);
>-			mac_control->rx_curr_put_info[ring_no].offset =
>+			mac_control->rings[ring_no].rx_curr_put_info.offset =
> 			    off;
>-			rxdp = nic->rx_blocks[ring_no][block_no].
>+			rxdp = mac_control->rings[ring_no].rx_blocks[block_no].
> 			    block_virt_addr;
> 		}
> #ifndef CONFIG_S2IO_NAPI
> 		spin_lock_irqsave(&nic->put_lock, flags);
>-		nic->put_pos = (block_no * (MAX_RXDS_PER_BLOCK + 1)) + off;
>+		mac_control->rings[ring_no].put_pos = (block_no *
>+					 (MAX_RXDS_PER_BLOCK + 1)) + off;
> 		spin_unlock_irqrestore(&nic->put_lock, flags);
> #endif
> #endif
>@@ -1769,27 +2207,27 @@ int fill_rx_buffers(struct s2io_nic *nic
> 		if (rxdp->Control_2 & BIT(0))
> #endif
> 		{
>-			mac_control->rx_curr_put_info[ring_no].
>+			mac_control->rings[ring_no].rx_curr_put_info.
> 			    offset = off;
> 			goto end;
> 		}
> #ifdef	CONFIG_2BUFF_MODE
>-		/* 
>-		 * RxDs Spanning cache lines will be replenished only 
>-		 * if the succeeding RxD is also owned by Host. It 
>-		 * will always be the ((8*i)+3) and ((8*i)+6) 
>-		 * descriptors for the 48 byte descriptor. The offending 
>+		/*
>+		 * RxDs Spanning cache lines will be replenished only
>+		 * if the succeeding RxD is also owned by Host. It
>+		 * will always be the ((8*i)+3) and ((8*i)+6)
>+		 * descriptors for the 48 byte descriptor. The offending
> 		 * decsriptor is of-course the 3rd descriptor.
> 		 */
>-		rxdpphys = nic->rx_blocks[ring_no][block_no].
>+		rxdpphys = mac_control->rings[ring_no].rx_blocks[block_no].
> 		    block_dma_addr + (off * sizeof(RxD_t));
> 		if (((u64) (rxdpphys)) % 128 > 80) {
>-			rxdpnext = nic->rx_blocks[ring_no][block_no].
>+			rxdpnext = mac_control->rings[ring_no].rx_blocks[block_no].
> 			    block_virt_addr + (off + 1);
> 			if (rxdpnext->Host_Control == END_OF_BLOCK) {
> 				nextblk = (block_no + 1) %
>-				    (nic->block_count[ring_no]);
>-				rxdpnext = nic->rx_blocks[ring_no]
>+				    (mac_control->rings[ring_no].block_count);
>+				rxdpnext = mac_control->rings[ring_no].rx_blocks
> 				    [nextblk].block_virt_addr;
> 			}
> 			if (rxdpnext->Control_2 & BIT(0))
>@@ -1798,38 +2236,42 @@ int fill_rx_buffers(struct s2io_nic *nic
> #endif
> 
> #ifndef	CONFIG_2BUFF_MODE
>-		skb = dev_alloc_skb(size + HEADER_ALIGN_LAYER_3);
>+		skb = dev_alloc_skb(size + NET_IP_ALIGN);
> #else
>-		skb = dev_alloc_skb(dev->mtu + ALIGN_SIZE +
>-				    /*BUF0_LEN + */ 22);
>+		skb = dev_alloc_skb(dev->mtu + ALIGN_SIZE + BUF0_LEN + 4);
> #endif
> 		if (!skb) {
> 			DBG_PRINT(ERR_DBG, "%s: Out of ", dev->name);
> 			DBG_PRINT(ERR_DBG, "memory to allocate SKBs\n");
>+			if (first_rxdp) {
>+				wmb();
>+				first_rxdp->Control_1 |= RXD_OWN_XENA;
>+			}
> 			return -ENOMEM;
> 		}
> #ifndef	CONFIG_2BUFF_MODE
>-		skb_reserve(skb, HEADER_ALIGN_LAYER_3);
>+		skb_reserve(skb, NET_IP_ALIGN);
> 		memset(rxdp, 0, sizeof(RxD_t));
> 		rxdp->Buffer0_ptr = pci_map_single
> 		    (nic->pdev, skb->data, size, PCI_DMA_FROMDEVICE);
> 		rxdp->Control_2 &= (~MASK_BUFFER0_SIZE);
> 		rxdp->Control_2 |= SET_BUFFER0_SIZE(size);
> 		rxdp->Host_Control = (unsigned long) (skb);
>-		rxdp->Control_1 |= RXD_OWN_XENA;
>+		if (alloc_tab & ((1 << rxsync_frequency) - 1))
>+			rxdp->Control_1 |= RXD_OWN_XENA;
> 		off++;
> 		off %= (MAX_RXDS_PER_BLOCK + 1);
>-		mac_control->rx_curr_put_info[ring_no].offset = off;
>+		mac_control->rings[ring_no].rx_curr_put_info.offset = off;
> #else
>-		ba = &nic->ba[ring_no][block_no][off];
>-		tmp = (u64) skb->data;
>-		tmp += ALIGN_SIZE;
>-		tmp &= ~ALIGN_SIZE;
>-		skb->data = (void *) tmp;
>+		ba = &mac_control->rings[ring_no].ba[block_no][off];
>+		skb_reserve(skb, BUF0_LEN);
>+		tmp = ((unsigned long) skb->data & ALIGN_SIZE);
>+		if (tmp)
>+			skb_reserve(skb, (ALIGN_SIZE + 1) - tmp);
> 
> 		memset(rxdp, 0, sizeof(RxD_t));
> 		rxdp->Buffer2_ptr = pci_map_single
>-		    (nic->pdev, skb->data, dev->mtu + 22,
>+		    (nic->pdev, skb->data, dev->mtu + BUF0_LEN + 4,
> 		     PCI_DMA_FROMDEVICE);
> 		rxdp->Buffer0_ptr =
> 		    pci_map_single(nic->pdev, ba->ba_0, BUF0_LEN,
>@@ -1838,27 +2280,46 @@ int fill_rx_buffers(struct s2io_nic *nic
> 		    pci_map_single(nic->pdev, ba->ba_1, BUF1_LEN,
> 				   PCI_DMA_FROMDEVICE);
> 
>-		rxdp->Control_2 = SET_BUFFER2_SIZE(dev->mtu + 22);
>+		rxdp->Control_2 = SET_BUFFER2_SIZE(dev->mtu + 4);
> 		rxdp->Control_2 |= SET_BUFFER0_SIZE(BUF0_LEN);
> 		rxdp->Control_2 |= SET_BUFFER1_SIZE(1);	/* dummy. */
> 		rxdp->Control_2 |= BIT(0);	/* Set Buffer_Empty bit. */
> 		rxdp->Host_Control = (u64) ((unsigned long) (skb));
>-		rxdp->Control_1 |= RXD_OWN_XENA;
>+		if (alloc_tab & ((1 << rxsync_frequency) - 1))
>+			rxdp->Control_1 |= RXD_OWN_XENA;
> 		off++;
>-		mac_control->rx_curr_put_info[ring_no].offset = off;
>+		mac_control->rings[ring_no].rx_curr_put_info.offset = off;
> #endif
>+		rxdp->Control_2 |= SET_RXD_MARKER;
>+
>+		if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
>+			if (first_rxdp) {
>+				wmb();
>+				first_rxdp->Control_1 |= RXD_OWN_XENA;
>+			}
>+			first_rxdp = rxdp;
>+		}
> 		atomic_inc(&nic->rx_bufs_left[ring_no]);
> 		alloc_tab++;
> 	}
> 
>       end:
>+	/* Transfer ownership of first descriptor to adapter just before
>+	 * exiting. Before that, use memory barrier so that ownership
>+	 * and other fields are seen by adapter correctly.
>+	 */
>+	if (first_rxdp) {
>+		wmb();
>+		first_rxdp->Control_1 |= RXD_OWN_XENA;
>+	}
>+
> 	return SUCCESS;
> }
> 
> /**
>- *  free_rx_buffers - Frees all Rx buffers   
>+ *  free_rx_buffers - Frees all Rx buffers
>  *  @sp: device private variable.
>- *  Description: 
>+ *  Description:
>  *  This function will free all Rx buffers allocated by host.
>  *  Return Value:
>  *  NONE.
>@@ -1879,10 +2340,11 @@ static void free_rx_buffers(struct s2io_
> 	mac_control = &sp->mac_control;
> 	config = &sp->config;
> 
>-	for (i = 0; i < config->RxRingNum; i++) {
>-		for (j = 0, blk = 0; j < config->rx_cfg[i].NumRxd; j++) {
>+	for (i = 0; i < config->rx_ring_num; i++) {
>+		for (j = 0, blk = 0; j < config->rx_cfg[i].num_rxd; j++) {
> 			off = j % (MAX_RXDS_PER_BLOCK + 1);
>-			rxdp = sp->rx_blocks[i][blk].block_virt_addr + off;
>+			rxdp = mac_control->rings[i].rx_blocks[blk].
>+				block_virt_addr + off;
> 
> #ifndef CONFIG_2BUFF_MODE
> 			if (rxdp->Control_1 == END_OF_BLOCK) {
>@@ -1917,7 +2379,7 @@ static void free_rx_buffers(struct s2io_
> 						 HEADER_SNAP_SIZE,
> 						 PCI_DMA_FROMDEVICE);
> #else
>-				ba = &sp->ba[i][blk][off];
>+				ba = &mac_control->rings[i].ba[blk][off];
> 				pci_unmap_single(sp->pdev, (dma_addr_t)
> 						 rxdp->Buffer0_ptr,
> 						 BUF0_LEN,
>@@ -1928,7 +2390,7 @@ static void free_rx_buffers(struct s2io_
> 						 PCI_DMA_FROMDEVICE);
> 				pci_unmap_single(sp->pdev, (dma_addr_t)
> 						 rxdp->Buffer2_ptr,
>-						 dev->mtu + 22,
>+						 dev->mtu + BUF0_LEN + 4,
> 						 PCI_DMA_FROMDEVICE);
> #endif
> 				dev_kfree_skb(skb);
>@@ -1937,10 +2399,10 @@ static void free_rx_buffers(struct s2io_
> 			}
> 			memset(rxdp, 0, sizeof(RxD_t));
> 		}
>-		mac_control->rx_curr_put_info[i].block_index = 0;
>-		mac_control->rx_curr_get_info[i].block_index = 0;
>-		mac_control->rx_curr_put_info[i].offset = 0;
>-		mac_control->rx_curr_get_info[i].offset = 0;
>+		mac_control->rings[i].rx_curr_put_info.block_index = 0;
>+		mac_control->rings[i].rx_curr_get_info.block_index = 0;
>+		mac_control->rings[i].rx_curr_put_info.offset = 0;
>+		mac_control->rings[i].rx_curr_get_info.offset = 0;
> 		atomic_set(&sp->rx_bufs_left[i], 0);
> 		DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
> 			  dev->name, buf_cnt, i);
>@@ -1950,7 +2412,7 @@ static void free_rx_buffers(struct s2io_
> /**
>  * s2io_poll - Rx interrupt handler for NAPI support
>  * @dev : pointer to the device structure.
>- * @budget : The number of packets that were budgeted to be processed 
>+ * @budget : The number of packets that were budgeted to be processed
>  * during  one pass through the 'Poll" function.
>  * Description:
>  * Comes into picture only if NAPI support has been incorporated. It does
>@@ -1960,172 +2422,36 @@ static void free_rx_buffers(struct s2io_
>  * 0 on success and 1 if there are No Rx packets to be processed.
>  */
> 
>-#ifdef CONFIG_S2IO_NAPI
>+#if defined(CONFIG_S2IO_NAPI)
> static int s2io_poll(struct net_device *dev, int *budget)
> {
> 	nic_t *nic = dev->priv;
>-	XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
>-	int pkts_to_process = *budget, pkt_cnt = 0;
>-	register u64 val64 = 0;
>-	rx_curr_get_info_t get_info, put_info;
>-	int i, get_block, put_block, get_offset, put_offset, ring_bufs;
>-#ifndef CONFIG_2BUFF_MODE
>-	u16 val16, cksum;
>-#endif
>-	struct sk_buff *skb;
>-	RxD_t *rxdp;
>+	int pkt_cnt = 0, org_pkts_to_process;
> 	mac_info_t *mac_control;
> 	struct config_param *config;
>-#ifdef CONFIG_2BUFF_MODE
>-	buffAdd_t *ba;
>-#endif
>+	XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
>+	u64 val64;
>+	int i;
> 
>+	atomic_inc(&nic->isr_cnt);
> 	mac_control = &nic->mac_control;
> 	config = &nic->config;
> 
>-	if (pkts_to_process > dev->quota)
>-		pkts_to_process = dev->quota;
>+	nic->pkts_to_process = *budget;
>+	if (nic->pkts_to_process > dev->quota)
>+		nic->pkts_to_process = dev->quota;
>+	org_pkts_to_process = nic->pkts_to_process;
> 
> 	val64 = readq(&bar0->rx_traffic_int);
> 	writeq(val64, &bar0->rx_traffic_int);
> 
>-	for (i = 0; i < config->RxRingNum; i++) {
>-		get_info = mac_control->rx_curr_get_info[i];
>-		get_block = get_info.block_index;
>-		put_info = mac_control->rx_curr_put_info[i];
>-		put_block = put_info.block_index;
>-		ring_bufs = config->rx_cfg[i].NumRxd;
>-		rxdp = nic->rx_blocks[i][get_block].block_virt_addr +
>-		    get_info.offset;
>-#ifndef	CONFIG_2BUFF_MODE
>-		get_offset = (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
>-		    get_info.offset;
>-#ifndef CONFIG_S2IO_NAPI
>-		spin_lock(&nic->put_lock);
>-		put_offset = nic->put_pos;
>-		spin_unlock(&nic->put_lock);
>-#else
>-		put_offset = (put_block * (MAX_RXDS_PER_BLOCK + 1)) +
>-		    put_info.offset;
>-#endif
>-		while ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
>-		       (((get_offset + 1) % ring_bufs) != put_offset)) {
>-			if (--pkts_to_process < 0) {
>-				goto no_rx;
>-			}
>-			if (rxdp->Control_1 == END_OF_BLOCK) {
>-				rxdp =
>-				    (RxD_t *) ((unsigned long) rxdp->
>-					       Control_2);
>-				get_info.offset++;
>-				get_info.offset %=
>-				    (MAX_RXDS_PER_BLOCK + 1);
>-				get_block++;
>-				get_block %= nic->block_count[i];
>-				mac_control->rx_curr_get_info[i].
>-				    offset = get_info.offset;
>-				mac_control->rx_curr_get_info[i].
>-				    block_index = get_block;
>-				continue;
>-			}
>-			get_offset =
>-			    (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
>-			    get_info.offset;
>-			skb =
>-			    (struct sk_buff *) ((unsigned long) rxdp->
>-						Host_Control);
>-			if (skb == NULL) {
>-				DBG_PRINT(ERR_DBG, "%s: The skb is ",
>-					  dev->name);
>-				DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
>-				goto no_rx;
>-			}
>-			val64 = RXD_GET_BUFFER0_SIZE(rxdp->Control_2);
>-			val16 = (u16) (val64 >> 48);
>-			cksum = RXD_GET_L4_CKSUM(rxdp->Control_1);
>-			pci_unmap_single(nic->pdev, (dma_addr_t)
>-					 rxdp->Buffer0_ptr,
>-					 dev->mtu +
>-					 HEADER_ETHERNET_II_802_3_SIZE +
>-					 HEADER_802_2_SIZE +
>-					 HEADER_SNAP_SIZE,
>-					 PCI_DMA_FROMDEVICE);
>-			rx_osm_handler(nic, val16, rxdp, i);
>-			pkt_cnt++;
>-			get_info.offset++;
>-			get_info.offset %= (MAX_RXDS_PER_BLOCK + 1);
>-			rxdp =
>-			    nic->rx_blocks[i][get_block].block_virt_addr +
>-			    get_info.offset;
>-			mac_control->rx_curr_get_info[i].offset =
>-			    get_info.offset;
>-		}
>-#else
>-		get_offset = (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
>-		    get_info.offset;
>-#ifndef CONFIG_S2IO_NAPI
>-		spin_lock(&nic->put_lock);
>-		put_offset = nic->put_pos;
>-		spin_unlock(&nic->put_lock);
>-#else
>-		put_offset = (put_block * (MAX_RXDS_PER_BLOCK + 1)) +
>-		    put_info.offset;
>-#endif
>-		while (((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
>-			!(rxdp->Control_2 & BIT(0))) &&
>-		       (((get_offset + 1) % ring_bufs) != put_offset)) {
>-			if (--pkts_to_process < 0) {
>-				goto no_rx;
>-			}
>-			skb = (struct sk_buff *) ((unsigned long)
>-						  rxdp->Host_Control);
>-			if (skb == NULL) {
>-				DBG_PRINT(ERR_DBG, "%s: The skb is ",
>-					  dev->name);
>-				DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
>-				goto no_rx;
>-			}
>-
>-			pci_unmap_single(nic->pdev, (dma_addr_t)
>-					 rxdp->Buffer0_ptr,
>-					 BUF0_LEN, PCI_DMA_FROMDEVICE);
>-			pci_unmap_single(nic->pdev, (dma_addr_t)
>-					 rxdp->Buffer1_ptr,
>-					 BUF1_LEN, PCI_DMA_FROMDEVICE);
>-			pci_unmap_single(nic->pdev, (dma_addr_t)
>-					 rxdp->Buffer2_ptr,
>-					 dev->mtu + 22,
>-					 PCI_DMA_FROMDEVICE);
>-			ba = &nic->ba[i][get_block][get_info.offset];
>-
>-			rx_osm_handler(nic, rxdp, i, ba);
>-
>-			get_info.offset++;
>-			mac_control->rx_curr_get_info[i].offset =
>-			    get_info.offset;
>-			rxdp =
>-			    nic->rx_blocks[i][get_block].block_virt_addr +
>-			    get_info.offset;
>-
>-			if (get_info.offset &&
>-			    (!(get_info.offset % MAX_RXDS_PER_BLOCK))) {
>-				get_info.offset = 0;
>-				mac_control->rx_curr_get_info[i].
>-				    offset = get_info.offset;
>-				get_block++;
>-				get_block %= nic->block_count[i];
>-				mac_control->rx_curr_get_info[i].
>-				    block_index = get_block;
>-				rxdp =
>-				    nic->rx_blocks[i][get_block].
>-				    block_virt_addr;
>-			}
>-			get_offset =
>-			    (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
>-			    get_info.offset;
>-			pkt_cnt++;
>+	for (i = 0; i < config->rx_ring_num; i++) {
>+		rx_intr_handler(&mac_control->rings[i]);
>+		pkt_cnt = org_pkts_to_process - nic->pkts_to_process;
>+		if (!nic->pkts_to_process) {
>+			/* Quota for the current iteration has been met */
>+			goto no_rx;
> 		}
>-#endif
> 	}
> 	if (!pkt_cnt)
> 		pkt_cnt = 1;
>@@ -2134,7 +2460,7 @@ static int s2io_poll(struct net_device *
> 	*budget -= pkt_cnt;
> 	netif_rx_complete(dev);
> 
>-	for (i = 0; i < config->RxRingNum; i++) {
>+	for (i = 0; i < config->rx_ring_num; i++) {
> 		if (fill_rx_buffers(nic, i) == -ENOMEM) {
> 			DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
> 			DBG_PRINT(ERR_DBG, " in Rx Poll!!\n");
>@@ -2143,296 +2469,225 @@ static int s2io_poll(struct net_device *
> 	}
> 	/* Re enable the Rx interrupts. */
> 	en_dis_able_nic_intrs(nic, RX_TRAFFIC_INTR, ENABLE_INTRS);
>+	atomic_dec(&nic->isr_cnt);
> 	return 0;
> 
>-      no_rx:
>+no_rx:
> 	dev->quota -= pkt_cnt;
> 	*budget -= pkt_cnt;
> 
>-	for (i = 0; i < config->RxRingNum; i++) {
>+	for (i = 0; i < config->rx_ring_num; i++) {
> 		if (fill_rx_buffers(nic, i) == -ENOMEM) {
> 			DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
> 			DBG_PRINT(ERR_DBG, " in Rx Poll!!\n");
> 			break;
> 		}
> 	}
>+	atomic_dec(&nic->isr_cnt);
> 	return 1;
> }
>-#else
>-/**  
>+#endif
>+
>+/**
>  *  rx_intr_handler - Rx interrupt handler
>  *  @nic: device private variable.
>- *  Description: 
>- *  If the interrupt is because of a received frame or if the 
>+ *  Description:
>+ *  If the interrupt is because of a received frame or if the
>  *  receive ring contains fresh as yet un-processed frames,this function is
>- *  called. It picks out the RxD at which place the last Rx processing had 
>- *  stopped and sends the skb to the OSM's Rx handler and then increments 
>+ *  called. It picks out the RxD at which place the last Rx processing had
>+ *  stopped and sends the skb to the OSM's Rx handler and then increments
>  *  the offset.
>  *  Return Value:
>  *  NONE.
>  */
>-
>-static void rx_intr_handler(struct s2io_nic *nic)
>+static void rx_intr_handler(ring_info_t *ring_data)
> {
>+	nic_t *nic = ring_data->nic;
> 	struct net_device *dev = (struct net_device *) nic->dev;
>-	XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
>+	int get_block, get_offset, put_block, put_offset, ring_bufs;
> 	rx_curr_get_info_t get_info, put_info;
> 	RxD_t *rxdp;
> 	struct sk_buff *skb;
>-#ifndef CONFIG_2BUFF_MODE
>-	u16 val16, cksum;
>-#endif
>-	register u64 val64 = 0;
>-	int get_block, get_offset, put_block, put_offset, ring_bufs;
>-	int i, pkt_cnt = 0;
>-	mac_info_t *mac_control;
>-	struct config_param *config;
>-#ifdef CONFIG_2BUFF_MODE
>-	buffAdd_t *ba;
>+#ifndef CONFIG_S2IO_NAPI
>+	int pkt_cnt = 0;
> #endif
>+	spin_lock(&nic->rx_lock);
>+	if (atomic_read(&nic->card_state) == CARD_DOWN) {
>+		DBG_PRINT(INTR_DBG, "%s: %s going down for reset\n",
>+			  __FUNCTION__, dev->name);
>+		spin_unlock(&nic->rx_lock);
>+		return;
>+	}
> 
>-	mac_control = &nic->mac_control;
>-	config = &nic->config;
>-
>-	/* 
>-	 * rx_traffic_int reg is an R1 register, hence we read and write back 
>-	 * the samevalue in the register to clear it.
>-	 */
>-	val64 = readq(&bar0->rx_traffic_int);
>-	writeq(val64, &bar0->rx_traffic_int);
>-
>-	for (i = 0; i < config->RxRingNum; i++) {
>-		get_info = mac_control->rx_curr_get_info[i];
>-		get_block = get_info.block_index;
>-		put_info = mac_control->rx_curr_put_info[i];
>-		put_block = put_info.block_index;
>-		ring_bufs = config->rx_cfg[i].NumRxd;
>-		rxdp = nic->rx_blocks[i][get_block].block_virt_addr +
>-		    get_info.offset;
>-#ifndef	CONFIG_2BUFF_MODE
>-		get_offset = (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
>+	get_info = ring_data->rx_curr_get_info;
>+	get_block = get_info.block_index;
>+	put_info = ring_data->rx_curr_put_info;
>+	put_block = put_info.block_index;
>+	ring_bufs = get_info.ring_len+1;
>+	rxdp = ring_data->rx_blocks[get_block].block_virt_addr +
> 		    get_info.offset;
>+	get_offset = (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
>+		get_info.offset;
> #ifndef CONFIG_S2IO_NAPI
>-		spin_lock(&nic->put_lock);
>-		put_offset = nic->put_pos;
>-		spin_unlock(&nic->put_lock);
>+	spin_lock(&nic->put_lock);
>+	put_offset = ring_data->put_pos;
>+	spin_unlock(&nic->put_lock);
>+#else
>+	put_offset = (put_block * (MAX_RXDS_PER_BLOCK + 1)) +
>+		put_info.offset;
> #endif
>-		while ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
>-		       (((get_offset + 1) % ring_bufs) != put_offset)) {
>-			if (rxdp->Control_1 == END_OF_BLOCK) {
>-				rxdp = (RxD_t *) ((unsigned long)
>-						  rxdp->Control_2);
>-				get_info.offset++;
>-				get_info.offset %=
>-				    (MAX_RXDS_PER_BLOCK + 1);
>-				get_block++;
>-				get_block %= nic->block_count[i];
>-				mac_control->rx_curr_get_info[i].
>-				    offset = get_info.offset;
>-				mac_control->rx_curr_get_info[i].
>-				    block_index = get_block;
>-				continue;
>-			}
>-			get_offset =
>-			    (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
>-			    get_info.offset;
>-			skb = (struct sk_buff *) ((unsigned long)
>-						  rxdp->Host_Control);
>-			if (skb == NULL) {
>-				DBG_PRINT(ERR_DBG, "%s: The skb is ",
>-					  dev->name);
>-				DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
>-				return;
>-			}
>-			val64 = RXD_GET_BUFFER0_SIZE(rxdp->Control_2);
>-			val16 = (u16) (val64 >> 48);
>-			cksum = RXD_GET_L4_CKSUM(rxdp->Control_1);
>-			pci_unmap_single(nic->pdev, (dma_addr_t)
>-					 rxdp->Buffer0_ptr,
>-					 dev->mtu +
>-					 HEADER_ETHERNET_II_802_3_SIZE +
>-					 HEADER_802_2_SIZE +
>-					 HEADER_SNAP_SIZE,
>-					 PCI_DMA_FROMDEVICE);
>-			rx_osm_handler(nic, val16, rxdp, i);
>-			get_info.offset++;
>-			get_info.offset %= (MAX_RXDS_PER_BLOCK + 1);
>-			rxdp =
>-			    nic->rx_blocks[i][get_block].block_virt_addr +
>-			    get_info.offset;
>-			mac_control->rx_curr_get_info[i].offset =
>-			    get_info.offset;
>-			pkt_cnt++;
>-			if ((indicate_max_pkts)
>-			    && (pkt_cnt > indicate_max_pkts))
>-				break;
>+	while (RXD_IS_UP2DT(rxdp) &&
>+	       (((get_offset + 1) % ring_bufs) != put_offset)) {
>+		skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
>+		if (skb == NULL) {
>+			DBG_PRINT(ERR_DBG, "%s: The skb is ",
>+				  dev->name);
>+			DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
>+			spin_unlock(&nic->rx_lock);
>+			return;
> 		}
>+#ifndef CONFIG_2BUFF_MODE
>+		pci_unmap_single(nic->pdev, (dma_addr_t)
>+				 rxdp->Buffer0_ptr,
>+				 dev->mtu +
>+				 HEADER_ETHERNET_II_802_3_SIZE +
>+				 HEADER_802_2_SIZE +
>+				 HEADER_SNAP_SIZE,
>+				 PCI_DMA_FROMDEVICE);
> #else
>-		get_offset = (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
>+		pci_unmap_single(nic->pdev, (dma_addr_t)
>+				 rxdp->Buffer0_ptr,
>+				 BUF0_LEN, PCI_DMA_FROMDEVICE);
>+		pci_unmap_single(nic->pdev, (dma_addr_t)
>+				 rxdp->Buffer1_ptr,
>+				 BUF1_LEN, PCI_DMA_FROMDEVICE);
>+		pci_unmap_single(nic->pdev, (dma_addr_t)
>+				 rxdp->Buffer2_ptr,
>+				 dev->mtu + BUF0_LEN + 4,
>+				 PCI_DMA_FROMDEVICE);
>+#endif
>+		rx_osm_handler(ring_data, rxdp);
>+		get_info.offset++;
>+		ring_data->rx_curr_get_info.offset =
> 		    get_info.offset;
>-#ifndef CONFIG_S2IO_NAPI
>-		spin_lock(&nic->put_lock);
>-		put_offset = nic->put_pos;
>-		spin_unlock(&nic->put_lock);
>-#endif
>-		while (((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
>-			!(rxdp->Control_2 & BIT(0))) &&
>-		       (((get_offset + 1) % ring_bufs) != put_offset)) {
>-			skb = (struct sk_buff *) ((unsigned long)
>-						  rxdp->Host_Control);
>-			if (skb == NULL) {
>-				DBG_PRINT(ERR_DBG, "%s: The skb is ",
>-					  dev->name);
>-				DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
>-				return;
>-			}
>-
>-			pci_unmap_single(nic->pdev, (dma_addr_t)
>-					 rxdp->Buffer0_ptr,
>-					 BUF0_LEN, PCI_DMA_FROMDEVICE);
>-			pci_unmap_single(nic->pdev, (dma_addr_t)
>-					 rxdp->Buffer1_ptr,
>-					 BUF1_LEN, PCI_DMA_FROMDEVICE);
>-			pci_unmap_single(nic->pdev, (dma_addr_t)
>-					 rxdp->Buffer2_ptr,
>-					 dev->mtu + 22,
>-					 PCI_DMA_FROMDEVICE);
>-			ba = &nic->ba[i][get_block][get_info.offset];
>+		rxdp = ring_data->rx_blocks[get_block].block_virt_addr +
>+		    get_info.offset;
>+		if (get_info.offset &&
>+		    (!(get_info.offset % MAX_RXDS_PER_BLOCK))) {
>+			get_info.offset = 0;
>+			ring_data->rx_curr_get_info.offset
>+			    = get_info.offset;
>+			get_block++;
>+			get_block %= ring_data->block_count;
>+			ring_data->rx_curr_get_info.block_index
>+			    = get_block;
>+			rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
>+		}
> 
>-			rx_osm_handler(nic, rxdp, i, ba);
>-
>-			get_info.offset++;
>-			mac_control->rx_curr_get_info[i].offset =
>-			    get_info.offset;
>-			rxdp =
>-			    nic->rx_blocks[i][get_block].block_virt_addr +
>-			    get_info.offset;
>-
>-			if (get_info.offset &&
>-			    (!(get_info.offset % MAX_RXDS_PER_BLOCK))) {
>-				get_info.offset = 0;
>-				mac_control->rx_curr_get_info[i].
>-				    offset = get_info.offset;
>-				get_block++;
>-				get_block %= nic->block_count[i];
>-				mac_control->rx_curr_get_info[i].
>-				    block_index = get_block;
>-				rxdp =
>-				    nic->rx_blocks[i][get_block].
>-				    block_virt_addr;
>-			}
>-			get_offset =
>-			    (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
>+		get_offset = (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
> 			    get_info.offset;
>-			pkt_cnt++;
>-			if ((indicate_max_pkts)
>-			    && (pkt_cnt > indicate_max_pkts))
>-				break;
>-		}
>-#endif
>+#ifdef CONFIG_S2IO_NAPI
>+		nic->pkts_to_process -= 1;
>+		if (!nic->pkts_to_process)
>+			break;
>+#else
>+		pkt_cnt++;
> 		if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
> 			break;
>+#endif
> 	}
>+	spin_unlock(&nic->rx_lock);
> }
>-#endif
>-/**  
>+
>+/**
>  *  tx_intr_handler - Transmit interrupt handler
>  *  @nic : device private variable
>- *  Description: 
>- *  If an interrupt was raised to indicate DMA complete of the 
>- *  Tx packet, this function is called. It identifies the last TxD 
>- *  whose buffer was freed and frees all skbs whose data have already 
>+ *  Description:
>+ *  If an interrupt was raised to indicate DMA complete of the
>+ *  Tx packet, this function is called. It identifies the last TxD
>+ *  whose buffer was freed and frees all skbs whose data have already
>  *  DMA'ed into the NICs internal memory.
>  *  Return Value:
>  *  NONE
>  */
> 
>-static void tx_intr_handler(struct s2io_nic *nic)
>+static void tx_intr_handler(fifo_info_t *fifo_data)
> {
>-	XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
>+	nic_t *nic = fifo_data->nic;
> 	struct net_device *dev = (struct net_device *) nic->dev;
> 	tx_curr_get_info_t get_info, put_info;
> 	struct sk_buff *skb;
> 	TxD_t *txdlp;
>-	register u64 val64 = 0;
>-	int i;
> 	u16 j, frg_cnt;
>-	mac_info_t *mac_control;
>-	struct config_param *config;
>-
>-	mac_control = &nic->mac_control;
>-	config = &nic->config;
> 
>-	/* 
>-	 * tx_traffic_int reg is an R1 register, hence we read and write 
>-	 * back the samevalue in the register to clear it.
>-	 */
>-	val64 = readq(&bar0->tx_traffic_int);
>-	writeq(val64, &bar0->tx_traffic_int);
>-
>-	for (i = 0; i < config->TxFIFONum; i++) {
>-		get_info = mac_control->tx_curr_get_info[i];
>-		put_info = mac_control->tx_curr_put_info[i];
>-		txdlp = (TxD_t *) nic->list_info[i][get_info.offset].
>-		    list_virt_addr;
>-		while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
>-		       (get_info.offset != put_info.offset) &&
>-		       (txdlp->Host_Control)) {
>-			/* Check for TxD errors */
>-			if (txdlp->Control_1 & TXD_T_CODE) {
>-				unsigned long long err;
>-				err = txdlp->Control_1 & TXD_T_CODE;
>-				DBG_PRINT(ERR_DBG, "***TxD error %llx\n",
>-					  err);
>+	get_info = fifo_data->tx_curr_get_info;
>+	put_info = fifo_data->tx_curr_put_info;
>+	txdlp = (TxD_t *) fifo_data->list_info[get_info.offset].
>+	    list_virt_addr;
>+	while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
>+	       (get_info.offset != put_info.offset) &&
>+	       (txdlp->Host_Control)) {
>+		/* Check for TxD errors */
>+		if (txdlp->Control_1 & TXD_T_CODE) {
>+			unsigned long long err;
>+			err = txdlp->Control_1 & TXD_T_CODE;
>+			if ((err >> 48) == 0xA) {
>+				DBG_PRINT(TX_DBG, "TxD returned due \
>+						to loss of link\n");
> 			}
>-
>-			skb = (struct sk_buff *) ((unsigned long)
>-						  txdlp->Host_Control);
>-			if (skb == NULL) {
>-				DBG_PRINT(ERR_DBG, "%s: Null skb ",
>-					  dev->name);
>-				DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
>-				return;
>+			else {
>+				DBG_PRINT(ERR_DBG, "***TxD error \
>+						%llx\n", err);
> 			}
>-			nic->tx_pkt_count++;
>+		}
> 
>-			frg_cnt = skb_shinfo(skb)->nr_frags;
>+		skb = (struct sk_buff *) ((unsigned long)
>+				txdlp->Host_Control);
>+		if (skb == NULL) {
>+			DBG_PRINT(ERR_DBG, "%s: Null skb ",
>+			__FUNCTION__);
>+			DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
>+			return;
>+		}
> 
>-			/*  For unfragmented skb */
>-			pci_unmap_single(nic->pdev, (dma_addr_t)
>-					 txdlp->Buffer_Pointer,
>-					 skb->len - skb->data_len,
>-					 PCI_DMA_TODEVICE);
>-			if (frg_cnt) {
>-				TxD_t *temp = txdlp;
>-				txdlp++;
>-				for (j = 0; j < frg_cnt; j++, txdlp++) {
>-					skb_frag_t *frag =
>-					    &skb_shinfo(skb)->frags[j];
>-					pci_unmap_page(nic->pdev,
>-						       (dma_addr_t)
>-						       txdlp->
>-						       Buffer_Pointer,
>-						       frag->size,
>-						       PCI_DMA_TODEVICE);
>-				}
>-				txdlp = temp;
>-			}
>-			memset(txdlp, 0,
>-			       (sizeof(TxD_t) * config->MaxTxDs));
>+		frg_cnt = skb_shinfo(skb)->nr_frags;
>+		nic->tx_pkt_count++;
> 
>-			/* Updating the statistics block */
>-			nic->stats.tx_packets++;
>-			nic->stats.tx_bytes += skb->len;
>-			dev_kfree_skb_irq(skb);
>-
>-			get_info.offset++;
>-			get_info.offset %= get_info.fifo_len + 1;
>-			txdlp = (TxD_t *) nic->list_info[i]
>-			    [get_info.offset].list_virt_addr;
>-			mac_control->tx_curr_get_info[i].offset =
>-			    get_info.offset;
>+		pci_unmap_single(nic->pdev, (dma_addr_t)
>+				 txdlp->Buffer_Pointer,
>+				 skb->len - skb->data_len,
>+				 PCI_DMA_TODEVICE);
>+		if (frg_cnt) {
>+			TxD_t *temp;
>+			temp = txdlp;
>+			txdlp++;
>+			for (j = 0; j < frg_cnt; j++, txdlp++) {
>+				skb_frag_t *frag =
>+				    &skb_shinfo(skb)->frags[j];
>+				if (!txdlp->Buffer_Pointer)
>+					break;
>+				pci_unmap_page(nic->pdev,
>+					       (dma_addr_t)
>+					       txdlp->
>+					       Buffer_Pointer,
>+					       frag->size,
>+					       PCI_DMA_TODEVICE);
>+			}
>+			txdlp = temp;
> 		}
>+		memset(txdlp, 0,
>+		       (sizeof(TxD_t) * fifo_data->max_txds));
>+
>+		/* Updating the statistics block */
>+		nic->stats.tx_bytes += skb->len;
>+		dev_kfree_skb_irq(skb);
>+
>+		get_info.offset++;
>+		get_info.offset %= get_info.fifo_len + 1;
>+		txdlp = (TxD_t *) fifo_data->list_info
>+		    [get_info.offset].list_virt_addr;
>+		fifo_data->tx_curr_get_info.offset =
>+		    get_info.offset;
> 	}
> 
> 	spin_lock(&nic->tx_lock);
>@@ -2441,13 +2696,13 @@ static void tx_intr_handler(struct s2io_
> 	spin_unlock(&nic->tx_lock);
> }
> 
>-/**  
>+/**
>  *  alarm_intr_handler - Alarm Interrrupt handler
>  *  @nic: device private variable
>- *  Description: If the interrupt was neither because of Rx packet or Tx 
>+ *  Description: If the interrupt was neither because of Rx packet or Tx
>  *  complete, this function is called. If the interrupt was to indicate
>- *  a loss of link, the OSM link status handler is invoked for any other 
>- *  alarm interrupt the block that raised the interrupt is displayed 
>+ *  a loss of link, the OSM link status handler is invoked for any other
>+ *  alarm interrupt the block that raised the interrupt is displayed
>  *  and a H/W reset is issued.
>  *  Return Value:
>  *  NONE
>@@ -2456,28 +2711,56 @@ static void tx_intr_handler(struct s2io_
> static void alarm_intr_handler(struct s2io_nic *nic)
> {
> 	struct net_device *dev = (struct net_device *) nic->dev;
>-	XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
>+	XENA_dev_config_t __iomem *bar0 = nic->bar0;
> 	register u64 val64 = 0, err_reg = 0;
> 
> 	/* Handling link status change error Intr */
>-	err_reg = readq(&bar0->mac_rmac_err_reg);
>-	writeq(err_reg, &bar0->mac_rmac_err_reg);
>-	if (err_reg & RMAC_LINK_STATE_CHANGE_INT) {
>-		schedule_work(&nic->set_link_task);
>+	if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
>+		err_reg = readq(&bar0->mac_rmac_err_reg);
>+		writeq(err_reg, &bar0->mac_rmac_err_reg);
>+		if (err_reg & RMAC_LINK_STATE_CHANGE_INT) {
>+			schedule_work(&nic->set_link_task);
>+		}
>+	}
>+
>+	/* Handling Ecc errors */
>+	val64 = readq(&bar0->mc_err_reg);
>+	writeq(val64, &bar0->mc_err_reg);
>+	if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
>+		if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
>+			nic->mac_control.stats_info->sw_stat.
>+				double_ecc_errs++;
>+			DBG_PRINT(INIT_DBG, "%s: Device indicates ",
>+				  dev->name);
>+			DBG_PRINT(INIT_DBG, "double ECC error!!\n");
>+			if (nic->device_type != XFRAME_II_DEVICE) {
>+				/* Reset XframeI only if critical error */
>+				if (val64 & (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
>+					     MC_ERR_REG_MIRI_ECC_DB_ERR_1)) {
>+					netif_stop_queue(dev);
>+					schedule_work(&nic->rst_timer_task);
>+				}
>+			}
>+		} else {
>+			nic->mac_control.stats_info->sw_stat.
>+				single_ecc_errs++;
>+		}
> 	}
> 
> 	/* In case of a serious error, the device will be Reset. */
> 	val64 = readq(&bar0->serr_source);
> 	if (val64 & SERR_SOURCE_ANY) {
> 		DBG_PRINT(ERR_DBG, "%s: Device indicates ", dev->name);
>-		DBG_PRINT(ERR_DBG, "serious error!!\n");
>+		DBG_PRINT(ERR_DBG, "serious error %llx!!\n", 
>+			  (unsigned long long)val64);
>+		netif_stop_queue(dev);
> 		schedule_work(&nic->rst_timer_task);
> 	}
> 
> 	/*
> 	 * Also as mentioned in the latest Errata sheets if the PCC_FB_ECC
> 	 * Error occurs, the adapter will be recycled by disabling the
>-	 * adapter enable bit and enabling it again after the device 
>+	 * adapter enable bit and enabling it again after the device
> 	 * becomes Quiescent.
> 	 */
> 	val64 = readq(&bar0->pcc_err_reg);
>@@ -2493,20 +2776,20 @@ static void alarm_intr_handler(struct s2
> 	/* Other type of interrupts are not being handled now,  TODO */
> }
> 
>-/** 
>+/**
>  *  wait_for_cmd_complete - waits for a command to complete.
>- *  @sp : private member of the device structure, which is a pointer to the 
>+ *  @sp : private member of the device structure, which is a pointer to the
>  *  s2io_nic structure.
>- *  Description: Function that waits for a command to Write into RMAC 
>- *  ADDR DATA registers to be completed and returns either success or 
>- *  error depending on whether the command was complete or not. 
>+ *  Description: Function that waits for a command to Write into RMAC
>+ *  ADDR DATA registers to be completed and returns either success or
>+ *  error depending on whether the command was complete or not.
>  *  Return value:
>  *   SUCCESS on success and FAILURE on failure.
>  */
> 
> int wait_for_cmd_complete(nic_t * sp)
> {
>-	XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
>+	XENA_dev_config_t __iomem *bar0 = sp->bar0;
> 	int ret = FAILURE, cnt = 0;
> 	u64 val64;
> 
>@@ -2516,8 +2799,7 @@ int wait_for_cmd_complete(nic_t * sp)
> 			ret = SUCCESS;
> 			break;
> 		}
>-		set_current_state(TASK_UNINTERRUPTIBLE);
>-		schedule_timeout(HZ / 20);
>+		msleep(50);
> 		if (cnt++ > 10)
> 			break;
> 	}
>@@ -2525,63 +2807,96 @@ int wait_for_cmd_complete(nic_t * sp)
> 	return ret;
> }
> 
>-/** 
>- *  s2io_reset - Resets the card. 
>+/**
>+ *  s2io_reset - Resets the card.
>  *  @sp : private member of the device structure.
>  *  Description: Function to Reset the card. This function then also
>- *  restores the previously saved PCI configuration space registers as 
>- *  the card reset also resets the Configration space.
>+ *  restores the previously saved PCI configuration space registers as
>+ *  the card reset also resets the configuration space.
>  *  Return value:
>  *  void.
>  */
> 
> void s2io_reset(nic_t * sp)
> {
>-	XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
>+	XENA_dev_config_t __iomem *bar0 = sp->bar0;
> 	u64 val64;
>-	u16 subid;
>+	u16 subid, pci_cmd;
>+
>+	/* Back up  the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
>+	pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
> 
> 	val64 = SW_RESET_ALL;
> 	writeq(val64, &bar0->sw_reset);
> 
>-	/* 
>-	 * At this stage, if the PCI write is indeed completed, the 
>-	 * card is reset and so is the PCI Config space of the device. 
>-	 * So a read cannot be issued at this stage on any of the 
>+	/*
>+	 * At this stage, if the PCI write is indeed completed, the
>+	 * card is reset and so is the PCI Config space of the device.
>+	 * So a read cannot be issued at this stage on any of the
> 	 * registers to ensure the write into "sw_reset" register
> 	 * has gone through.
> 	 * Question: Is there any system call that will explicitly force
> 	 * all the write commands still pending on the bus to be pushed
> 	 * through?
>-	 * As of now I'am just giving a 100ms delay and hoping that the
>+	 * As of now I'am just giving a 250ms delay and hoping that the
> 	 * PCI write to sw_reset register is done by this time.
> 	 */
>-	mdelay(100);
>+	msleep(250);
> 
>-	/* Restore the PCI state saved during initializarion. */
>+	/* Restore the PCI state saved during initialization. */
> 	pci_restore_state(sp->pdev, sp->config_space);
>+	pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
>+				     pci_cmd);
> 	s2io_init_pci(sp);
> 
>-	mdelay(100);
>+	msleep(250);
>+
>+	/* Set swapper to enable I/O register access */
>+	s2io_set_swapper(sp);
>+
>+	/* Clear certain PCI/PCI-X fields after reset */
>+	if (sp->device_type == XFRAME_II_DEVICE) {
>+		/* Clear parity err detect bit */
>+		pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
>+
>+		/* Clearing PCIX Ecc status register */
>+		pci_write_config_dword(sp->pdev, 0x68, 0x7C);
>+
>+		/* Clearing PCI_STATUS error reflected here */
>+		writeq(BIT(62), &bar0->txpic_int_reg);
>+	}
>+
>+	/* Reset device statistics maintained by OS */
>+	memset(&sp->stats, 0, sizeof (struct net_device_stats));
> 
> 	/* SXE-002: Configure link and activity LED to turn it off */
> 	subid = sp->pdev->subsystem_device;
>-	if ((subid & 0xFF) >= 0x07) {
>+	if (((subid & 0xFF) >= 0x07) &&
>+	    (sp->device_type == XFRAME_I_DEVICE)) {
> 		val64 = readq(&bar0->gpio_control);
> 		val64 |= 0x0000800000000000ULL;
> 		writeq(val64, &bar0->gpio_control);
> 		val64 = 0x0411040400000000ULL;
>-		writeq(val64, (void *) ((u8 *) bar0 + 0x2700));
>+		writeq(val64, (void __iomem *) ((u8 *) bar0 + 0x2700));
>+	}
>+
>+	/*
>+	 * Clear spurious ECC interrupts that would have occured on
>+	 * XFRAME II cards after reset.
>+	 */
>+	if (sp->device_type == XFRAME_II_DEVICE) {
>+		val64 = readq(&bar0->pcc_err_reg);
>+		writeq(val64, &bar0->pcc_err_reg);
> 	}
> 
> 	sp->device_enabled_once = FALSE;
> }
> 
> /**
>- *  s2io_set_swapper - to set the swapper controle on the card 
>- *  @sp : private member of the device structure, 
>+ *  s2io_set_swapper - to set the swapper controle on the card
>+ *  @sp : private member of the device structure,
>  *  pointer to the s2io_nic structure.
>- *  Description: Function to set the swapper control on the card 
>+ *  Description: Function to set the swapper control on the card
>  *  correctly depending on the 'endianness' of the system.
>  *  Return value:
>  *  SUCCESS on success and FAILURE on failure.
>@@ -2590,24 +2905,76 @@ void s2io_reset(nic_t * sp)
> int s2io_set_swapper(nic_t * sp)
> {
> 	struct net_device *dev = sp->dev;
>-	XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
>-	u64 val64;
>+	XENA_dev_config_t __iomem *bar0 = sp->bar0;
>+	u64 val64, valt, valr;
> 
>-	/* 
>+	/*
> 	 * Set proper endian settings and verify the same by reading
> 	 * the PIF Feed-back register.
> 	 */
>+
>+	val64 = readq(&bar0->pif_rd_swapper_fb);
>+	if (val64 != 0x0123456789ABCDEFULL) {
>+		int i = 0;
>+		u64 value[] = { 0xC30000C3C30000C3ULL,   /* FE=1, SE=1 */
>+				0x8100008181000081ULL,  /* FE=1, SE=0 */
>+				0x4200004242000042ULL,  /* FE=0, SE=1 */
>+				0};                     /* FE=0, SE=0 */
>+
>+		while(i<4) {
>+			writeq(value[i], &bar0->swapper_ctrl);
>+			val64 = readq(&bar0->pif_rd_swapper_fb);
>+			if (val64 == 0x0123456789ABCDEFULL)
>+				break;
>+			i++;
>+		}
>+		if (i == 4) {
>+			DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
>+				dev->name);
>+			DBG_PRINT(ERR_DBG, "feedback read %llx\n",
>+				(unsigned long long) val64);
>+			return FAILURE;
>+		}
>+		valr = value[i];
>+	} else {
>+		valr = readq(&bar0->swapper_ctrl);
>+	}
>+
>+	valt = 0x0123456789ABCDEFULL;
>+	writeq(valt, &bar0->xmsi_address);
>+	val64 = readq(&bar0->xmsi_address);
>+
>+	if(val64 != valt) {
>+		int i = 0;
>+		u64 value[] = { 0x00C3C30000C3C300ULL,  /* FE=1, SE=1 */
>+				0x0081810000818100ULL,  /* FE=1, SE=0 */
>+				0x0042420000424200ULL,  /* FE=0, SE=1 */
>+				0};                     /* FE=0, SE=0 */
>+
>+		while(i<4) {
>+			writeq((value[i] | valr), &bar0->swapper_ctrl);
>+			writeq(valt, &bar0->xmsi_address);
>+			val64 = readq(&bar0->xmsi_address);
>+			if(val64 == valt)
>+				break;
>+			i++;
>+		}
>+		if(i == 4) {
>+			unsigned long long x = val64;
>+			DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
>+			DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
>+			return FAILURE;
>+		}
>+	}
>+	val64 = readq(&bar0->swapper_ctrl);
>+	val64 &= 0xFFFF000000000000ULL;
>+
> #ifdef  __BIG_ENDIAN
>-	/* 
>-	 * The device by default set to a big endian format, so a 
>+	/*
>+	 * The device by default set to a big endian format, so a
> 	 * big endian driver need not set anything.
> 	 */
>-	writeq(0xffffffffffffffffULL, &bar0->swapper_ctrl);
>-	val64 = (SWAPPER_CTRL_PIF_R_FE |
>-		 SWAPPER_CTRL_PIF_R_SE |
>-		 SWAPPER_CTRL_PIF_W_FE |
>-		 SWAPPER_CTRL_PIF_W_SE |
>-		 SWAPPER_CTRL_TXP_FE |
>+	val64 |= (SWAPPER_CTRL_TXP_FE |
> 		 SWAPPER_CTRL_TXP_SE |
> 		 SWAPPER_CTRL_TXD_R_FE |
> 		 SWAPPER_CTRL_TXD_W_FE |
>@@ -2620,17 +2987,12 @@ int s2io_set_swapper(nic_t * sp)
> 		 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
> 	writeq(val64, &bar0->swapper_ctrl);
> #else
>-	/* 
>+	/*
> 	 * Initially we enable all bits to make it accessible by the
>-	 * driver, then we selectively enable only those bits that 
>+	 * driver, then we selectively enable only those bits that
> 	 * we want to set.
> 	 */
>-	writeq(0xffffffffffffffffULL, &bar0->swapper_ctrl);
>-	val64 = (SWAPPER_CTRL_PIF_R_FE |
>-		 SWAPPER_CTRL_PIF_R_SE |
>-		 SWAPPER_CTRL_PIF_W_FE |
>-		 SWAPPER_CTRL_PIF_W_SE |
>-		 SWAPPER_CTRL_TXP_FE |
>+	val64 |= (SWAPPER_CTRL_TXP_FE |
> 		 SWAPPER_CTRL_TXP_SE |
> 		 SWAPPER_CTRL_TXD_R_FE |
> 		 SWAPPER_CTRL_TXD_R_SE |
>@@ -2647,9 +3009,10 @@ int s2io_set_swapper(nic_t * sp)
> 		 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
> 	writeq(val64, &bar0->swapper_ctrl);
> #endif
>+	val64 = readq(&bar0->swapper_ctrl);
> 
>-	/* 
>-	 * Verifying if endian settings are accurate by reading a 
>+	/*
>+	 * Verifying if endian settings are accurate by reading a
> 	 * feedback register.
> 	 */
> 	val64 = readq(&bar0->pif_rd_swapper_fb);
>@@ -2669,13 +3032,13 @@ int s2io_set_swapper(nic_t * sp)
>  * Functions defined below concern the OS part of the driver *
>  * ********************************************************* */
> 
>-/**  
>- *  s2io-open - open entry point of the driver
>+/**
>+ *  s2io_open - open entry point of the driver
>  *  @dev : pointer to the device structure.
>  *  Description:
>  *  This function is the open entry point of the driver. It mainly calls a
>  *  function to allocate Rx buffers and inserts them into the buffer
>- *  descriptors and then enables the Rx part of the NIC. 
>+ *  descriptors and then enables the Rx part of the NIC.
>  *  Return value:
>  *  0 on success and an appropriate (-)ve integer as defined in errno.h
>  *   file on failure.
>@@ -2684,81 +3047,48 @@ int s2io_set_swapper(nic_t * sp)
> int s2io_open(struct net_device *dev)
> {
> 	nic_t *sp = dev->priv;
>-	int i, ret = 0, err = 0;
>-	mac_info_t *mac_control;
>-	struct config_param *config;
>+	int err = 0;
> 
>-
>-	/* 
>-	 * Make sure you have link off by default every time 
>+	/*
>+	 * Make sure you have link off by default every time
> 	 * Nic is initialized
> 	 */
> 	netif_carrier_off(dev);
>-	sp->last_link_state = LINK_DOWN;
>+	sp->last_link_state = 0;
> 
>-	/* Initialize the H/W I/O registers */
>-	if (init_nic(sp) != 0) {
>+	/* Initialize H/W and enable interrupts */
>+	if (s2io_card_up(sp)) {
> 		DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
> 			  dev->name);
>-		return -ENODEV;
>+		err = -ENODEV;
>+		goto hw_init_failed;
> 	}
> 
> 	/* After proper initialization of H/W, register ISR */
>-	err =
>-	    request_irq((int) sp->irq, s2io_isr, SA_SHIRQ, sp->name, dev);
>+	err = request_irq((int) sp->pdev->irq, s2io_isr, SA_SHIRQ,
>+			  sp->name, dev);
> 	if (err) {
>-		s2io_reset(sp);
> 		DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
> 			  dev->name);
>-		return err;
>+		goto isr_registration_failed;
> 	}
>+
> 	if (s2io_set_mac_addr(dev, dev->dev_addr) == FAILURE) {
> 		DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
>-		s2io_reset(sp);
>-		return -ENODEV;
>-	}
>-
>-
>-	/* Setting its receive mode */
>-	s2io_set_multicast(dev);
>-
>-	/* 
>-	 * Initializing the Rx buffers. For now we are considering only 1 
>-	 * Rx ring and initializing buffers into 1016 RxDs or 8 Rx blocks
>-	 */
>-	mac_control = &sp->mac_control;
>-	config = &sp->config;
>-
>-	for (i = 0; i < config->RxRingNum; i++) {
>-		if ((ret = fill_rx_buffers(sp, i))) {
>-			DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
>-				  dev->name);
>-			s2io_reset(sp);
>-			free_irq(dev->irq, dev);
>-			free_rx_buffers(sp);
>-			return -ENOMEM;
>-		}
>-		DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
>-			  atomic_read(&sp->rx_bufs_left[i]));
>-	}
>-
>-	/* Enable tasklet for the device */
>-	tasklet_init(&sp->task, s2io_tasklet, (unsigned long) dev);
>-
>-	/* Enable Rx Traffic and interrupts on the NIC */
>-	if (start_nic(sp)) {
>-		DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
>-		tasklet_kill(&sp->task);
>-		s2io_reset(sp);
>-		free_irq(dev->irq, dev);
>-		free_rx_buffers(sp);
>-		return -ENODEV;
>+		err = -ENODEV;
>+		goto setting_mac_address_failed;
> 	}
> 
>-	sp->device_close_flag = FALSE;	/* Device is up and running. */
> 	netif_start_queue(dev);
>-
> 	return 0;
>+
>+setting_mac_address_failed:
>+	free_irq(sp->pdev->irq, dev);
>+isr_registration_failed:
>+	del_timer_sync(&sp->alarm_timer);
>+	s2io_reset(sp);
>+hw_init_failed:
>+	return err;
> }
> 
> /**
>@@ -2777,67 +3107,13 @@ int s2io_open(struct net_device *dev)
> int s2io_close(struct net_device *dev)
> {
> 	nic_t *sp = dev->priv;
>-	XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
>-	register u64 val64 = 0;
>-	u16 cnt = 0;
>-	unsigned long flags;
>-
>-	spin_lock_irqsave(&sp->tx_lock, flags);
>+	flush_scheduled_work();
> 	netif_stop_queue(dev);
>+	/* Reset card, kill tasklet and free Tx and Rx buffers. */
>+	s2io_card_down(sp);
> 
>-	/* disable Tx and Rx traffic on the NIC */
>-	stop_nic(sp);
>-
>-	/* 
>-	 * If the device tasklet is running, wait till its done 
>-	 * before killing it 
>-	 */
>-	while (atomic_read(&(sp->tasklet_status))) {
>-		set_current_state(TASK_UNINTERRUPTIBLE);
>-		schedule_timeout(HZ / 10);
>-	}
>-	tasklet_kill(&sp->task);
>-
>-	/*  Free the Registered IRQ */
>-	free_irq(dev->irq, dev);
>-
>-	/* Flush all scheduled tasks */
>-	if (sp->task_flag == 1) {
>-		DBG_PRINT(INFO_DBG, "%s: Calling close from a task\n",
>-			  dev->name);
>-	} else {
>-		flush_scheduled_work();
>-	}
>-
>-	/* Check if the device is Quiescent and then Reset the NIC */
>-	do {
>-		val64 = readq(&bar0->adapter_status);
>-		if (verify_xena_quiescence(val64, sp->device_enabled_once)) {
>-			break;
>-		}
>-
>-		set_current_state(TASK_UNINTERRUPTIBLE);
>-		schedule_timeout(HZ / 20);
>-		cnt++;
>-		if (cnt == 10) {
>-			DBG_PRINT(ERR_DBG,
>-				  "s2io_close:Device not Quiescent ");
>-			DBG_PRINT(ERR_DBG, "adaper status reads 0x%llx\n",
>-				  (unsigned long long) val64);
>-			break;
>-		}
>-	} while (1);
>-	s2io_reset(sp);
>-
>-	/* Free all Tx Buffers waiting for transmission */
>-	free_tx_buffers(sp);
>-
>-	/*  Free all Rx buffers allocated by host */
>-	free_rx_buffers(sp);
>-
>+	free_irq(sp->pdev->irq, dev);
> 	sp->device_close_flag = TRUE;	/* Device is shut down. */
>-	spin_unlock_irqrestore(&sp->tx_lock, flags);
>-
> 	return 0;
> }
> 
>@@ -2860,50 +3136,61 @@ int s2io_xmit(struct sk_buff *skb, struc
> 	u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
> 	register u64 val64;
> 	TxD_t *txdp;
>-	TxFIFO_element_t *tx_fifo;
>+	TxFIFO_element_t __iomem *tx_fifo;
> 	unsigned long flags;
> #ifdef NETIF_F_TSO
> 	int mss;
> #endif
>+	u16 vlan_tag = 0;
>+	int vlan_priority = 0;
> 	mac_info_t *mac_control;
> 	struct config_param *config;
>-	XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
> 
> 	mac_control = &sp->mac_control;
> 	config = &sp->config;
> 
>-	DBG_PRINT(TX_DBG, "%s: In S2IO Tx routine\n", dev->name);
>-
>+	DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
> 	spin_lock_irqsave(&sp->tx_lock, flags);
>-	if ((netif_queue_stopped(dev)) || (!netif_carrier_ok(dev))) {
>-		DBG_PRINT(ERR_DBG, "%s:s2io_xmit: Tx Queue stopped\n",
>+	if (atomic_read(&sp->card_state) == CARD_DOWN) {
>+		DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
> 			  dev->name);
>-		dev_kfree_skb(skb);
> 		spin_unlock_irqrestore(&sp->tx_lock, flags);
>+		dev_kfree_skb(skb);
> 		return 0;
> 	}
> 
> 	queue = 0;
>-	/* Multi FIFO Tx is disabled for now. */
>-	if (!queue && tx_prio) {
>-		u8 x = (skb->data)[5];
>-		queue = x % config->TxFIFONum;
>-	}
> 
>+	/* Get Fifo number to Transmit based on vlan priority */
>+	if (sp->vlgrp && vlan_tx_tag_present(skb)) {
>+		vlan_tag = vlan_tx_tag_get(skb);
>+		vlan_priority = vlan_tag >> 13;
>+		queue = config->fifo_mapping[vlan_priority];
>+	}
> 
>-	put_off = (u16) mac_control->tx_curr_put_info[queue].offset;
>-	get_off = (u16) mac_control->tx_curr_get_info[queue].offset;
>-	txdp = (TxD_t *) sp->list_info[queue][put_off].list_virt_addr;
>+	put_off = (u16) mac_control->fifos[queue].tx_curr_put_info.offset;
>+	get_off = (u16) mac_control->fifos[queue].tx_curr_get_info.offset;
>+	txdp = (TxD_t *) mac_control->fifos[queue].list_info[put_off].
>+		list_virt_addr;
> 
>-	queue_len = mac_control->tx_curr_put_info[queue].fifo_len + 1;
>+	queue_len = mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1;
> 	/* Avoid "put" pointer going beyond "get" pointer */
> 	if (txdp->Host_Control || (((put_off + 1) % queue_len) == get_off)) {
>-		DBG_PRINT(ERR_DBG, "Error in xmit, No free TXDs.\n");
>+		DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
> 		netif_stop_queue(dev);
> 		dev_kfree_skb(skb);
> 		spin_unlock_irqrestore(&sp->tx_lock, flags);
> 		return 0;
> 	}
>+
>+	/* A buffer with no data will be dropped */
>+	if (!skb->len) {
>+		DBG_PRINT(TX_DBG, "%s:Buffer has no data..\n", dev->name);
>+		dev_kfree_skb(skb);
>+		spin_unlock_irqrestore(&sp->tx_lock, flags);
>+		return 0;
>+	}
>+
> #ifdef NETIF_F_TSO
> 	mss = skb_shinfo(skb)->tso_size;
> 	if (mss) {
>@@ -2915,16 +3202,21 @@ int s2io_xmit(struct sk_buff *skb, struc
> 	frg_cnt = skb_shinfo(skb)->nr_frags;
> 	frg_len = skb->len - skb->data_len;
> 
>-	txdp->Host_Control = (unsigned long) skb;
> 	txdp->Buffer_Pointer = pci_map_single
> 	    (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE);
>+	txdp->Host_Control = (unsigned long) skb;
> 	if (skb->ip_summed == CHECKSUM_HW) {
> 		txdp->Control_2 |=
> 		    (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN |
> 		     TXD_TX_CKO_UDP_EN);
> 	}
> 
>-	txdp->Control_2 |= config->TxIntrType;
>+	txdp->Control_2 |= config->tx_intr_type;
>+
>+	if (sp->vlgrp && vlan_tx_tag_present(skb)) {
>+		txdp->Control_2 |= TXD_VLAN_ENABLE;
>+		txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
>+	}
> 
> 	txdp->Control_1 |= (TXD_BUFFER0_SIZE(frg_len) |
> 			    TXD_GATHER_CODE_FIRST);
>@@ -2933,6 +3225,9 @@ int s2io_xmit(struct sk_buff *skb, struc
> 	/* For fragmented SKB. */
> 	for (i = 0; i < frg_cnt; i++) {
> 		skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
>+		/* A '0' length fragment will be ignored */
>+		if (!frag->size)
>+			continue;
> 		txdp++;
> 		txdp->Buffer_Pointer = (u64) pci_map_page
> 		    (sp->pdev, frag->page, frag->page_offset,
>@@ -2942,23 +3237,23 @@ int s2io_xmit(struct sk_buff *skb, struc
> 	txdp->Control_1 |= TXD_GATHER_CODE_LAST;
> 
> 	tx_fifo = mac_control->tx_FIFO_start[queue];
>-	val64 = sp->list_info[queue][put_off].list_phy_addr;
>+	val64 = mac_control->fifos[queue].list_info[put_off].list_phy_addr;
> 	writeq(val64, &tx_fifo->TxDL_Pointer);
> 
> 	val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
> 		 TX_FIFO_LAST_LIST);
>+
> #ifdef NETIF_F_TSO
> 	if (mss)
> 		val64 |= TX_FIFO_SPECIAL_FUNC;
> #endif
> 	writeq(val64, &tx_fifo->List_Control);
> 
>-	/* Perform a PCI read to flush previous writes */
>-	val64 = readq(&bar0->general_int_status);
>+	mmiowb();
> 
> 	put_off++;
>-	put_off %= mac_control->tx_curr_put_info[queue].fifo_len + 1;
>-	mac_control->tx_curr_put_info[queue].offset = put_off;
>+	put_off %= mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1;
>+	mac_control->fifos[queue].tx_curr_put_info.offset = put_off;
> 
> 	/* Avoid "put" pointer going beyond "get" pointer */
> 	if (((put_off + 1) % queue_len) == get_off) {
>@@ -2974,59 +3269,106 @@ int s2io_xmit(struct sk_buff *skb, struc
> 	return 0;
> }
> 
>+static void
>+s2io_alarm_handle(unsigned long data)
>+{
>+	nic_t *sp = (nic_t *)data;
>+
>+	alarm_intr_handler(sp);
>+	mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
>+}
>+
>+static void s2io_txpic_intr_handle(nic_t *sp)
>+{
>+	XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
>+	u64 val64;
>+
>+	val64 = readq(&bar0->pic_int_status);
>+	if (val64 & PIC_INT_GPIO) {
>+		val64 = readq(&bar0->gpio_int_reg);
>+		if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
>+		    (val64 & GPIO_INT_REG_LINK_UP)) {
>+			val64 |=  GPIO_INT_REG_LINK_DOWN;
>+			val64 |= GPIO_INT_REG_LINK_UP;
>+			writeq(val64, &bar0->gpio_int_reg);
>+			goto masking;
>+		}
>+
>+		if (((sp->last_link_state == LINK_UP) &&
>+			(val64 & GPIO_INT_REG_LINK_DOWN)) ||
>+		((sp->last_link_state == LINK_DOWN) &&
>+		(val64 & GPIO_INT_REG_LINK_UP))) {
>+			val64 = readq(&bar0->gpio_int_mask);
>+			val64 |=  GPIO_INT_MASK_LINK_DOWN;
>+			val64 |= GPIO_INT_MASK_LINK_UP;
>+			writeq(val64, &bar0->gpio_int_mask);
>+			s2io_set_link((unsigned long)sp);
>+		}
>+masking:
>+		if (sp->last_link_state == LINK_UP) {
>+			/*enable down interrupt */
>+			val64 = readq(&bar0->gpio_int_mask);
>+			/* unmasks link down intr */
>+			val64 &=  ~GPIO_INT_MASK_LINK_DOWN;
>+			/* masks link up intr */
>+			val64 |= GPIO_INT_MASK_LINK_UP;
>+			writeq(val64, &bar0->gpio_int_mask);
>+		} else {
>+			/*enable UP Interrupt */
>+			val64 = readq(&bar0->gpio_int_mask);
>+			/* unmasks link up interrupt */
>+			val64 &= ~GPIO_INT_MASK_LINK_UP;
>+			/* masks link down interrupt */
>+			val64 |=  GPIO_INT_MASK_LINK_DOWN;
>+			writeq(val64, &bar0->gpio_int_mask);
>+		}
>+	}
>+}
>+
> /**
>  *  s2io_isr - ISR handler of the device .
>  *  @irq: the irq of the device.
>  *  @dev_id: a void pointer to the dev structure of the NIC.
>  *  @pt_regs: pointer to the registers pushed on the stack.
>- *  Description:  This function is the ISR handler of the device. It 
>- *  identifies the reason for the interrupt and calls the relevant 
>- *  service routines. As a contongency measure, this ISR allocates the 
>+ *  Description:  This function is the ISR handler of the device. It
>+ *  identifies the reason for the interrupt and calls the relevant
>+ *  service routines. As a contongency measure, this ISR allocates the
>  *  recv buffers, if their numbers are below the panic value which is
>  *  presently set to 25% of the original number of rcv buffers allocated.
>  *  Return value:
>- *   IRQ_HANDLED: will be returned if IRQ was handled by this routine 
>+ *   IRQ_HANDLED: will be returned if IRQ was handled by this routine
>  *   IRQ_NONE: will be returned if interrupt is not from our device
>  */
> static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs)
> {
> 	struct net_device *dev = (struct net_device *) dev_id;
> 	nic_t *sp = dev->priv;
>-	XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
>-#ifndef CONFIG_S2IO_NAPI
>-	int i, ret;
>-#endif
>-	u64 reason = 0;
>+	XENA_dev_config_t __iomem *bar0 = sp->bar0;
>+	int i;
>+	u64 reason = 0, val64;
> 	mac_info_t *mac_control;
> 	struct config_param *config;
> 
>+	atomic_inc(&sp->isr_cnt);
> 	mac_control = &sp->mac_control;
> 	config = &sp->config;
> 
>-	/* 
>+	/*
> 	 * Identify the cause for interrupt and call the appropriate
> 	 * interrupt handler. Causes for the interrupt could be;
> 	 * 1. Rx of packet.
> 	 * 2. Tx complete.
> 	 * 3. Link down.
>-	 * 4. Error in any functional blocks of the NIC. 
>+	 * 4. Error in any functional blocks of the NIC.
> 	 */
> 	reason = readq(&bar0->general_int_status);
> 
> 	if (!reason) {
> 		/* The interrupt was not raised by Xena. */
>+		atomic_dec(&sp->isr_cnt);
> 		return IRQ_NONE;
> 	}
> 
>-	/* If Intr is because of Tx Traffic */
>-	if (reason & GEN_INTR_TXTRAFFIC) {
>-		tx_intr_handler(sp);
>-	}
>-
>-	/* If Intr is because of an error */
>-	if (reason & (GEN_ERROR_INTR))
>-		alarm_intr_handler(sp);
>-
> #ifdef CONFIG_S2IO_NAPI
> 	if (reason & GEN_INTR_RXTRAFFIC) {
> 		if (netif_rx_schedule_prep(dev)) {
>@@ -3038,17 +3380,43 @@ static irqreturn_t s2io_isr(int irq, voi
> #else
> 	/* If Intr is because of Rx Traffic */
> 	if (reason & GEN_INTR_RXTRAFFIC) {
>-		rx_intr_handler(sp);
>+		/*
>+		 * rx_traffic_int reg is an R1 register, writing all 1's
>+		 * will ensure that the actual interrupt causing bit get's
>+		 * cleared and hence a read can be avoided.
>+		 */
>+		val64 = 0xFFFFFFFFFFFFFFFFULL;
>+		writeq(val64, &bar0->rx_traffic_int);
>+		for (i = 0; i < config->rx_ring_num; i++) {
>+			rx_intr_handler(&mac_control->rings[i]);
>+		}
> 	}
> #endif
> 
>-	/* 
>-	 * If the Rx buffer count is below the panic threshold then 
>-	 * reallocate the buffers from the interrupt handler itself, 
>+	/* If Intr is because of Tx Traffic */
>+	if (reason & GEN_INTR_TXTRAFFIC) {
>+		/*
>+		 * tx_traffic_int reg is an R1 register, writing all 1's
>+		 * will ensure that the actual interrupt causing bit get's
>+		 * cleared and hence a read can be avoided.
>+		 */
>+		val64 = 0xFFFFFFFFFFFFFFFFULL;
>+		writeq(val64, &bar0->tx_traffic_int);
>+
>+		for (i = 0; i < config->tx_fifo_num; i++)
>+			tx_intr_handler(&mac_control->fifos[i]);
>+	}
>+
>+	if (reason & GEN_INTR_TXPIC)
>+		s2io_txpic_intr_handle(sp);
>+	/*
>+	 * If the Rx buffer count is below the panic threshold then
>+	 * reallocate the buffers from the interrupt handler itself,
> 	 * else schedule a tasklet to reallocate the buffers.
> 	 */
> #ifndef CONFIG_S2IO_NAPI
>-	for (i = 0; i < config->RxRingNum; i++) {
>+	for (i = 0; i < config->rx_ring_num; i++) {
>+		int ret;
> 		int rxb_size = atomic_read(&sp->rx_bufs_left[i]);
> 		int level = rx_buffer_level(sp, rxb_size, i);
> 
>@@ -3059,29 +3427,52 @@ static irqreturn_t s2io_isr(int irq, voi
> 				DBG_PRINT(ERR_DBG, "%s:Out of memory",
> 					  dev->name);
> 				DBG_PRINT(ERR_DBG, " in ISR!!\n");
>-				clear_bit(0,
>-					  (unsigned long *) (&sp->
>-							     tasklet_status));
>+				clear_bit(0, (&sp->tasklet_status));
>+				atomic_dec(&sp->isr_cnt);
> 				return IRQ_HANDLED;
> 			}
>-			clear_bit(0,
>-				  (unsigned long *) (&sp->tasklet_status));
>-		} else if ((level == LOW)
>-			   && (!atomic_read(&sp->tasklet_status))) {
>+			clear_bit(0, (&sp->tasklet_status));
>+		} else if (level == LOW) {
> 			tasklet_schedule(&sp->task);
> 		}
>-
> 	}
> #endif
> 
>+	atomic_dec(&sp->isr_cnt);
> 	return IRQ_HANDLED;
> }
> 
> /**
>- *  s2io_get_stats - Updates the device statistics structure. 
>+ * s2io_updt_stats -
>+ */
>+static void s2io_updt_stats(nic_t *sp)
>+{
>+	XENA_dev_config_t __iomem *bar0 = sp->bar0;
>+	u64 val64;
>+	int cnt = 0;
>+
>+	if (atomic_read(&sp->card_state) == CARD_UP) {
>+		/* Apprx 30us on a 133 MHz bus */
>+		val64 = SET_UPDT_CLICKS(10) |
>+			STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
>+		writeq(val64, &bar0->stat_cfg);
>+		do {
>+			udelay(100);
>+			val64 = readq(&bar0->stat_cfg);
>+			if (!(val64 & BIT(0)))
>+				break;
>+			cnt++;
>+			if (cnt == 5)
>+				break; /* Updt failed */
>+		} while(1);
>+	}
>+}
>+
>+/**
>+ *  s2io_get_stats - Updates the device statistics structure.
>  *  @dev : pointer to the device structure.
>  *  Description:
>- *  This function updates the device statistics structure in the s2io_nic 
>+ *  This function updates the device statistics structure in the s2io_nic
>  *  structure and returns a pointer to the same.
>  *  Return value:
>  *  pointer to the updated net_device_stats structure.
>@@ -3093,14 +3484,23 @@ struct net_device_stats *s2io_get_stats(
> 	mac_info_t *mac_control;
> 	struct config_param *config;
> 
>+
> 	mac_control = &sp->mac_control;
> 	config = &sp->config;
> 
>-	sp->stats.tx_errors = mac_control->stats_info->tmac_any_err_frms;
>-	sp->stats.rx_errors = mac_control->stats_info->rmac_drop_frms;
>-	sp->stats.multicast = mac_control->stats_info->rmac_vld_mcst_frms;
>+	/* Configure Stats for immediate updt */
>+	s2io_updt_stats(sp);
>+
>+	sp->stats.tx_packets =
>+		le32_to_cpu(mac_control->stats_info->tmac_frms);
>+	sp->stats.tx_errors =
>+		le32_to_cpu(mac_control->stats_info->tmac_any_err_frms);
>+	sp->stats.rx_errors =
>+		le32_to_cpu(mac_control->stats_info->rmac_drop_frms);
>+	sp->stats.multicast =
>+		le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms);
> 	sp->stats.rx_length_errors =
>-	    mac_control->stats_info->rmac_long_frms;
>+		le32_to_cpu(mac_control->stats_info->rmac_long_frms);
> 
> 	return (&sp->stats);
> }
>@@ -3109,8 +3509,8 @@ struct net_device_stats *s2io_get_stats(
>  *  s2io_set_multicast - entry point for multicast address enable/disable.
>  *  @dev : pointer to the device structure
>  *  Description:
>- *  This function is a driver entry point which gets called by the kernel 
>- *  whenever multicast addresses must be enabled/disabled. This also gets 
>+ *  This function is a driver entry point which gets called by the kernel
>+ *  whenever multicast addresses must be enabled/disabled. This also gets
>  *  called to set/reset promiscuous mode. Depending on the deivce flag, we
>  *  determine, if multicast address must be enabled or if promiscuous mode
>  *  is to be disabled etc.
>@@ -3123,11 +3523,11 @@ static void s2io_set_multicast(struct ne
> 	int i, j, prev_cnt;
> 	struct dev_mc_list *mclist;
> 	nic_t *sp = dev->priv;
>-	XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
>+	XENA_dev_config_t __iomem *bar0 = sp->bar0;
> 	u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
> 	    0xfeffffffffffULL;
> 	u64 dis_addr = 0xffffffffffffULL, mac_addr = 0;
>-	void *add;
>+	void __iomem *add;
> 
> 	if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
> 		/*  Enable all Multicast addresses */
>@@ -3148,6 +3548,8 @@ static void s2io_set_multicast(struct ne
> 		/*  Disable all Multicast addresses */
> 		writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
> 		       &bar0->rmac_addr_data0_mem);
>+		writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
>+		       &bar0->rmac_addr_data1_mem);
> 		val64 = RMAC_ADDR_CMD_MEM_WE |
> 		    RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
> 		    RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
>@@ -3161,7 +3563,7 @@ static void s2io_set_multicast(struct ne
> 
> 	if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
> 		/*  Put the NIC into promiscuous mode */
>-		add = (void *) &bar0->mac_cfg;
>+		add = &bar0->mac_cfg;
> 		val64 = readq(&bar0->mac_cfg);
> 		val64 |= MAC_CFG_RMAC_PROM_ENABLE;
> 
>@@ -3172,11 +3574,11 @@ static void s2io_set_multicast(struct ne
> 
> 		val64 = readq(&bar0->mac_cfg);
> 		sp->promisc_flg = 1;
>-		DBG_PRINT(ERR_DBG, "%s: entered promiscuous mode\n",
>+		DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
> 			  dev->name);
> 	} else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
> 		/*  Remove the NIC from promiscuous mode */
>-		add = (void *) &bar0->mac_cfg;
>+		add = &bar0->mac_cfg;
> 		val64 = readq(&bar0->mac_cfg);
> 		val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
> 
>@@ -3187,7 +3589,7 @@ static void s2io_set_multicast(struct ne
> 
> 		val64 = readq(&bar0->mac_cfg);
> 		sp->promisc_flg = 0;
>-		DBG_PRINT(ERR_DBG, "%s: left promiscuous mode\n",
>+		DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n",
> 			  dev->name);
> 	}
> 
>@@ -3209,6 +3611,8 @@ static void s2io_set_multicast(struct ne
> 		for (i = 0; i < prev_cnt; i++) {
> 			writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
> 			       &bar0->rmac_addr_data0_mem);
>+			writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
>+				&bar0->rmac_addr_data1_mem);
> 			val64 = RMAC_ADDR_CMD_MEM_WE |
> 			    RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
> 			    RMAC_ADDR_CMD_MEM_OFFSET
>@@ -3233,9 +3637,11 @@ static void s2io_set_multicast(struct ne
> 				mac_addr |= mclist->dmi_addr[j];
> 				mac_addr <<= 8;
> 			}
>+			mac_addr >>= 8;
> 			writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
> 			       &bar0->rmac_addr_data0_mem);
>-
>+			writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
>+				&bar0->rmac_addr_data1_mem);
> 			val64 = RMAC_ADDR_CMD_MEM_WE |
> 			    RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
> 			    RMAC_ADDR_CMD_MEM_OFFSET
>@@ -3254,26 +3660,26 @@ static void s2io_set_multicast(struct ne
> }
> 
> /**
>- *  s2io_set_mac_addr - Programs the Xframe mac address 
>+ *  s2io_set_mac_addr - Programs the Xframe mac address
>  *  @dev : pointer to the device structure.
>  *  @addr: a uchar pointer to the new mac address which is to be set.
>- *  Description : This procedure will program the Xframe to receive 
>+ *  Description : This procedure will program the Xframe to receive
>  *  frames with new Mac Address
>- *  Return value: SUCCESS on success and an appropriate (-)ve integer 
>+ *  Return value: SUCCESS on success and an appropriate (-)ve integer
>  *  as defined in errno.h file on failure.
>  */
> 
> int s2io_set_mac_addr(struct net_device *dev, u8 * addr)
> {
> 	nic_t *sp = dev->priv;
>-	XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
>+	XENA_dev_config_t __iomem *bar0 = sp->bar0;
> 	register u64 val64, mac_addr = 0;
> 	int i;
> 
>-	/* 
>+	/*
> 	 * Set the new MAC address as the new unicast filter and reflect this
> 	 * change on the device address registered with the OS. It will be
>-	 * at offset 0. 
>+	 * at offset 0.
> 	 */
> 	for (i = 0; i < ETH_ALEN; i++) {
> 		mac_addr <<= 8;
>@@ -3297,12 +3703,12 @@ int s2io_set_mac_addr(struct net_device 
> }
> 
> /**
>- * s2io_ethtool_sset - Sets different link parameters. 
>+ * s2io_ethtool_sset - Sets different link parameters.
>  * @sp : private member of the device structure, which is a pointer to the  * s2io_nic structure.
>  * @info: pointer to the structure with parameters given by ethtool to set
>  * link information.
>  * Description:
>- * The function sets different link parameters provided by the user onto 
>+ * The function sets different link parameters provided by the user onto
>  * the NIC.
>  * Return value:
>  * 0 on success.
>@@ -3324,18 +3730,18 @@ static int s2io_ethtool_sset(struct net_
> }
> 
> /**
>- * s2io_ethtol_gset - Return link specific information. 
>+ * s2io_ethtol_gset - Return link specific information.
>  * @sp : private member of the device structure, pointer to the
>  *      s2io_nic structure.
>  * @info : pointer to the structure with parameters given by ethtool
>  * to return link information.
>  * Description:
>- * Returns link specefic information like speed, duplex etc.. to ethtool.
>+ * Returns link specific information like speed, duplex etc.. to ethtool.
>  * Return value :
>  * return 0 on success.
>  */
> 
>-int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
>+static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
> {
> 	nic_t *sp = dev->priv;
> 	info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
>@@ -3356,8 +3762,8 @@ int s2io_ethtool_gset(struct net_device 
> }
> 
> /**
>- * s2io_ethtool_gdrvinfo - Returns driver specific information. 
>- * @sp : private member of the device structure, which is a pointer to the 
>+ * s2io_ethtool_gdrvinfo - Returns driver specific information.
>+ * @sp : private member of the device structure, which is a pointer to the
>  * s2io_nic structure.
>  * @info : pointer to the structure with parameters given by ethtool to
>  * return driver information.
>@@ -3376,7 +3782,7 @@ static void s2io_ethtool_gdrvinfo(struct
> 	strncpy(info->version, s2io_driver_version,
> 		sizeof(s2io_driver_version));
> 	strncpy(info->fw_version, "", 32);
>-	strncpy(info->bus_info, sp->pdev->slot_name, 32);
>+	strncpy(info->bus_info, pci_name(sp->pdev), 32);
> 	info->regdump_len = XENA_REG_SPACE;
> 	info->eedump_len = XENA_EEPROM_SPACE;
> 	info->testinfo_len = S2IO_TEST_LEN;
>@@ -3384,10 +3790,10 @@ static void s2io_ethtool_gdrvinfo(struct
> }
> 
> /**
>- *  s2io_ethtool_gregs - dumps the entire space of Xfame into te buffer.
>- *  @sp: private member of the device structure, which is a pointer to the 
>+ *  s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
>+ *  @sp: private member of the device structure, which is a pointer to the
>  *  s2io_nic structure.
>- *  @regs : pointer to the structure with parameters given by ethtool for 
>+ *  @regs : pointer to the structure with parameters given by ethtool for
>  *  dumping the registers.
>  *  @reg_space: The input argumnet into which all the registers are dumped.
>  *  Description:
>@@ -3409,29 +3815,30 @@ static void s2io_ethtool_gregs(struct ne
> 	regs->version = sp->pdev->subsystem_device;
> 
> 	for (i = 0; i < regs->len; i += 8) {
>-		reg = readq((void *) (sp->bar0 + i));
>+		reg = readq(sp->bar0 + i);
> 		memcpy((reg_space + i), &reg, 8);
> 	}
> }
> 
> /**
>  *  s2io_phy_id  - timer function that alternates adapter LED.
>- *  @data : address of the private member of the device structure, which 
>+ *  @data : address of the private member of the device structure, which
>  *  is a pointer to the s2io_nic structure, provided as an u32.
>- * Description: This is actually the timer function that alternates the 
>- * adapter LED bit of the adapter control bit to set/reset every time on 
>- * invocation. The timer is set for 1/2 a second, hence tha NIC blinks 
>+ * Description: This is actually the timer function that alternates the
>+ * adapter LED bit of the adapter control bit to set/reset every time on
>+ * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
>  *  once every second.
> */
> static void s2io_phy_id(unsigned long data)
> {
> 	nic_t *sp = (nic_t *) data;
>-	XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
>+	XENA_dev_config_t __iomem *bar0 = sp->bar0;
> 	u64 val64 = 0;
> 	u16 subid;
> 
> 	subid = sp->pdev->subsystem_device;
>-	if ((subid & 0xFF) >= 0x07) {
>+	if ((sp->device_type == XFRAME_II_DEVICE) ||
>+		   ((subid & 0xFF) >= 0x07)) {
> 		val64 = readq(&bar0->gpio_control);
> 		val64 ^= GPIO_CTRL_GPIO_0;
> 		writeq(val64, &bar0->gpio_control);
>@@ -3445,15 +3852,15 @@ static void s2io_phy_id(unsigned long da
> }
> 
> /**
>- * s2io_ethtool_idnic - To physically ientify the nic on the system.
>+ * s2io_ethtool_idnic - To physically identify the nic on the system.
>  * @sp : private member of the device structure, which is a pointer to the
>  * s2io_nic structure.
>- * @id : pointer to the structure with identification parameters given by 
>+ * @id : pointer to the structure with identification parameters given by
>  * ethtool.
>  * Description: Used to physically identify the NIC on the system.
>- * The Link LED will blink for a time specified by the user for 
>+ * The Link LED will blink for a time specified by the user for
>  * identification.
>- * NOTE: The Link has to be Up to be able to blink the LED. Hence 
>+ * NOTE: The Link has to be Up to be able to blink the LED. Hence
>  * identification is possible only if it's link is up.
>  * Return value:
>  * int , returns 0 on success
>@@ -3463,12 +3870,13 @@ static int s2io_ethtool_idnic(struct net
> {
> 	u64 val64 = 0, last_gpio_ctrl_val;
> 	nic_t *sp = dev->priv;
>-	XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
>+	XENA_dev_config_t __iomem *bar0 = sp->bar0;
> 	u16 subid;
> 
> 	subid = sp->pdev->subsystem_device;
> 	last_gpio_ctrl_val = readq(&bar0->gpio_control);
>-	if ((subid & 0xFF) < 0x07) {
>+	if ((sp->device_type == XFRAME_I_DEVICE) &&
>+		((subid & 0xFF) < 0x07)) {
> 		val64 = readq(&bar0->adapter_control);
> 		if (!(val64 & ADAPTER_CNTL_EN)) {
> 			printk(KERN_ERR
>@@ -3482,14 +3890,13 @@ static int s2io_ethtool_idnic(struct net
> 		sp->id_timer.data = (unsigned long) sp;
> 	}
> 	mod_timer(&sp->id_timer, jiffies);
>-	set_current_state(TASK_INTERRUPTIBLE);
> 	if (data)
>-		schedule_timeout(data * HZ);
>+		msleep_interruptible(data * HZ);
> 	else
>-		schedule_timeout(MAX_SCHEDULE_TIMEOUT);
>+		msleep_interruptible(MAX_FLICKER_TIME);
> 	del_timer_sync(&sp->id_timer);
> 
>-	if (CARDS_WITH_FAULTY_LINK_INDICATORS(subid)) {
>+	if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
> 		writeq(last_gpio_ctrl_val, &bar0->gpio_control);
> 		last_gpio_ctrl_val = readq(&bar0->gpio_control);
> 	}
>@@ -3499,7 +3906,8 @@ static int s2io_ethtool_idnic(struct net
> 
> /**
>  * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
>- * @sp : private member of the device structure, which is a pointer to the  * s2io_nic structure.
>+ * @sp : private member of the device structure, which is a pointer to the
>+ *	s2io_nic structure.
>  * @ep : pointer to the structure with pause parameters given by ethtool.
>  * Description:
>  * Returns the Pause frame generation and reception capability of the NIC.
>@@ -3511,7 +3919,7 @@ static void s2io_ethtool_getpause_data(s
> {
> 	u64 val64;
> 	nic_t *sp = dev->priv;
>-	XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
>+	XENA_dev_config_t __iomem *bar0 = sp->bar0;
> 
> 	val64 = readq(&bar0->rmac_pause_cfg);
> 	if (val64 & RMAC_PAUSE_GEN_ENABLE)
>@@ -3522,8 +3930,8 @@ static void s2io_ethtool_getpause_data(s
> }
> 
> /**
>- * s2io_ethtool-setpause_data -  set/reset pause frame generation.
>- * @sp : private member of the device structure, which is a pointer to the 
>+ * s2io_ethtool_setpause_data -  set/reset pause frame generation.
>+ * @sp : private member of the device structure, which is a pointer to the
>  *      s2io_nic structure.
>  * @ep : pointer to the structure with pause parameters given by ethtool.
>  * Description:
>@@ -3533,12 +3941,12 @@ static void s2io_ethtool_getpause_data(s
>  * int, returns 0 on Success
>  */
> 
>-int s2io_ethtool_setpause_data(struct net_device *dev,
>+static int s2io_ethtool_setpause_data(struct net_device *dev,
> 			       struct ethtool_pauseparam *ep)
> {
> 	u64 val64;
> 	nic_t *sp = dev->priv;
>-	XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
>+	XENA_dev_config_t __iomem *bar0 = sp->bar0;
> 
> 	val64 = readq(&bar0->rmac_pause_cfg);
> 	if (ep->tx_pause)
>@@ -3555,13 +3963,13 @@ int s2io_ethtool_setpause_data(struct ne
> 
> /**
>  * read_eeprom - reads 4 bytes of data from user given offset.
>- * @sp : private member of the device structure, which is a pointer to the 
>+ * @sp : private member of the device structure, which is a pointer to the
>  *      s2io_nic structure.
>  * @off : offset at which the data must be written
>  * @data : Its an output parameter where the data read at the given
>- * 	offset is stored.
>+ *	offset is stored.
>  * Description:
>- * Will read 4 bytes of data from the user given offset and return the 
>+ * Will read 4 bytes of data from the user given offset and return the
>  * read data.
>  * NOTE: Will allow to read only part of the EEPROM visible through the
>  *   I2C bus.
>@@ -3575,7 +3983,7 @@ static int read_eeprom(nic_t * sp, int o
> 	int ret = -1;
> 	u32 exit_cnt = 0;
> 	u64 val64;
>-	XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
>+	XENA_dev_config_t __iomem *bar0 = sp->bar0;
> 
> 	val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
> 	    I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ |
>@@ -3589,8 +3997,7 @@ static int read_eeprom(nic_t * sp, int o
> 			ret = 0;
> 			break;
> 		}
>-		set_current_state(TASK_UNINTERRUPTIBLE);
>-		schedule_timeout(HZ / 20);
>+		msleep(50);
> 		exit_cnt++;
> 	}
> 
>@@ -3603,7 +4010,7 @@ static int read_eeprom(nic_t * sp, int o
>  *       s2io_nic structure.
>  *  @off : offset at which the data must be written
>  *  @data : The data that is to be written
>- *  @cnt : Number of bytes of the data that are actually to be written into 
>+ *  @cnt : Number of bytes of the data that are actually to be written into
>  *  the Eeprom. (max of 3)
>  * Description:
>  *  Actually writes the relevant part of the data value into the Eeprom
>@@ -3616,7 +4023,7 @@ static int write_eeprom(nic_t * sp, int 
> {
> 	int exit_cnt = 0, ret = -1;
> 	u64 val64;
>-	XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
>+	XENA_dev_config_t __iomem *bar0 = sp->bar0;
> 
> 	val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
> 	    I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA(data) |
>@@ -3630,8 +4037,7 @@ static int write_eeprom(nic_t * sp, int 
> 				ret = 0;
> 			break;
> 		}
>-		set_current_state(TASK_UNINTERRUPTIBLE);
>-		schedule_timeout(HZ / 20);
>+		msleep(50);
> 		exit_cnt++;
> 	}
> 
>@@ -3641,7 +4047,7 @@ static int write_eeprom(nic_t * sp, int 
> /**
>  *  s2io_ethtool_geeprom  - reads the value stored in the Eeprom.
>  *  @sp : private member of the device structure, which is a pointer to the *       s2io_nic structure.
>- *  @eeprom : pointer to the user level structure provided by ethtool, 
>+ *  @eeprom : pointer to the user level structure provided by ethtool,
>  *  containing all relevant information.
>  *  @data_buf : user defined value to be written into Eeprom.
>  *  Description: Reads the values stored in the Eeprom at given offset
>@@ -3651,7 +4057,7 @@ static int write_eeprom(nic_t * sp, int 
>  *  int  0 on success
>  */
> 
>-int s2io_ethtool_geeprom(struct net_device *dev,
>+static int s2io_ethtool_geeprom(struct net_device *dev,
> 			 struct ethtool_eeprom *eeprom, u8 * data_buf)
> {
> 	u32 data, i, valid;
>@@ -3677,7 +4083,7 @@ int s2io_ethtool_geeprom(struct net_devi
>  *  s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
>  *  @sp : private member of the device structure, which is a pointer to the
>  *  s2io_nic structure.
>- *  @eeprom : pointer to the user level structure provided by ethtool, 
>+ *  @eeprom : pointer to the user level structure provided by ethtool,
>  *  containing all relevant information.
>  *  @data_buf ; user defined value to be written into Eeprom.
>  *  Description:
>@@ -3725,8 +4131,8 @@ static int s2io_ethtool_seeprom(struct n
> }
> 
> /**
>- * s2io_register_test - reads and writes into all clock domains. 
>- * @sp : private member of the device structure, which is a pointer to the 
>+ * s2io_register_test - reads and writes into all clock domains.
>+ * @sp : private member of the device structure, which is a pointer to the
>  * s2io_nic structure.
>  * @data : variable that returns the result of each of the test conducted b
>  * by the driver.
>@@ -3739,12 +4145,12 @@ static int s2io_ethtool_seeprom(struct n
> 
> static int s2io_register_test(nic_t * sp, uint64_t * data)
> {
>-	XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
>+	XENA_dev_config_t __iomem *bar0 = sp->bar0;
> 	u64 val64 = 0;
> 	int fail = 0;
> 
>-	val64 = readq(&bar0->pcc_enable);
>-	if (val64 != 0xff00000000000000ULL) {
>+	val64 = readq(&bar0->pif_rd_swapper_fb);
>+	if (val64 != 0x123456789abcdefULL) {
> 		fail = 1;
> 		DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n");
> 	}
>@@ -3788,13 +4194,13 @@ static int s2io_register_test(nic_t * sp
> }
> 
> /**
>- * s2io_eeprom_test - to verify that EEprom in the xena can be programmed. 
>+ * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
>  * @sp : private member of the device structure, which is a pointer to the
>  * s2io_nic structure.
>  * @data:variable that returns the result of each of the test conducted by
>  * the driver.
>  * Description:
>- * Verify that EEPROM in the xena can be programmed using I2C_CONTROL 
>+ * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
>  * register.
>  * Return value:
>  * 0 on success.
>@@ -3859,14 +4265,14 @@ static int s2io_eeprom_test(nic_t * sp, 
> 
> /**
>  * s2io_bist_test - invokes the MemBist test of the card .
>- * @sp : private member of the device structure, which is a pointer to the 
>+ * @sp : private member of the device structure, which is a pointer to the
>  * s2io_nic structure.
>- * @data:variable that returns the result of each of the test conducted by 
>+ * @data:variable that returns the result of each of the test conducted by
>  * the driver.
>  * Description:
>  * This invokes the MemBist test of the card. We give around
>  * 2 secs time for the Test to complete. If it's still not complete
>- * within this peiod, we consider that the test failed. 
>+ * within this peiod, we consider that the test failed.
>  * Return value:
>  * 0 on success and -1 on failure.
>  */
>@@ -3887,8 +4293,7 @@ static int s2io_bist_test(nic_t * sp, ui
> 			ret = 0;
> 			break;
> 		}
>-		set_current_state(TASK_UNINTERRUPTIBLE);
>-		schedule_timeout(HZ / 10);
>+		msleep(100);
> 		cnt++;
> 	}
> 
>@@ -3896,13 +4301,13 @@ static int s2io_bist_test(nic_t * sp, ui
> }
> 
> /**
>- * s2io-link_test - verifies the link state of the nic  
>- * @sp ; private member of the device structure, which is a pointer to the 
>+ * s2io-link_test - verifies the link state of the nic
>+ * @sp ; private member of the device structure, which is a pointer to the
>  * s2io_nic structure.
>  * @data: variable that returns the result of each of the test conducted by
>  * the driver.
>  * Description:
>- * The function verifies the link state of the NIC and updates the input 
>+ * The function verifies the link state of the NIC and updates the input
>  * argument 'data' appropriately.
>  * Return value:
>  * 0 on success.
>@@ -3910,7 +4315,7 @@ static int s2io_bist_test(nic_t * sp, ui
> 
> static int s2io_link_test(nic_t * sp, uint64_t * data)
> {
>-	XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
>+	XENA_dev_config_t __iomem *bar0 = sp->bar0;
> 	u64 val64;
> 
> 	val64 = readq(&bar0->adapter_status);
>@@ -3921,13 +4326,13 @@ static int s2io_link_test(nic_t * sp, ui
> }
> 
> /**
>- * s2io_rldram_test - offline test for access to the RldRam chip on the NIC 
>- * @sp - private member of the device structure, which is a pointer to the  
>+ * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
>+ * @sp - private member of the device structure, which is a pointer to the
>  * s2io_nic structure.
>- * @data - variable that returns the result of each of the test 
>+ * @data - variable that returns the result of each of the test
>  * conducted by the driver.
>  * Description:
>- *  This is one of the offline test that tests the read and write 
>+ *  This is one of the offline test that tests the read and write
>  *  access to the RldRam chip on the NIC.
>  * Return value:
>  *  0 on success.
>@@ -3935,7 +4340,7 @@ static int s2io_link_test(nic_t * sp, ui
> 
> static int s2io_rldram_test(nic_t * sp, uint64_t * data)
> {
>-	XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
>+	XENA_dev_config_t __iomem *bar0 = sp->bar0;
> 	u64 val64;
> 	int cnt, iteration = 0, test_pass = 0;
> 
>@@ -3989,8 +4394,7 @@ static int s2io_rldram_test(nic_t * sp, 
> 			val64 = readq(&bar0->mc_rldram_test_ctrl);
> 			if (val64 & MC_RLDRAM_TEST_DONE)
> 				break;
>-			set_current_state(TASK_UNINTERRUPTIBLE);
>-			schedule_timeout(HZ / 5);
>+			msleep(200);
> 		}
> 
> 		if (cnt == 5)
>@@ -4006,8 +4410,7 @@ static int s2io_rldram_test(nic_t * sp, 
> 			val64 = readq(&bar0->mc_rldram_test_ctrl);
> 			if (val64 & MC_RLDRAM_TEST_DONE)
> 				break;
>-			set_current_state(TASK_UNINTERRUPTIBLE);
>-			schedule_timeout(HZ / 2);
>+			msleep(500);
> 		}
> 
> 		if (cnt == 5)
>@@ -4034,7 +4437,7 @@ static int s2io_rldram_test(nic_t * sp, 
>  *  s2io_nic structure.
>  *  @ethtest : pointer to a ethtool command specific structure that will be
>  *  returned to the user.
>- *  @data : variable that returns the result of each of the test 
>+ *  @data : variable that returns the result of each of the test
>  * conducted by the driver.
>  * Description:
>  *  This function conducts 6 tests ( 4 offline and 2 online) to determine
>@@ -4052,23 +4455,18 @@ static void s2io_ethtool_test(struct net
> 
> 	if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
> 		/* Offline Tests. */
>-		if (orig_state) {
>+		if (orig_state)
> 			s2io_close(sp->dev);
>-			s2io_set_swapper(sp);
>-		} else
>-			s2io_set_swapper(sp);
> 
> 		if (s2io_register_test(sp, &data[0]))
> 			ethtest->flags |= ETH_TEST_FL_FAILED;
> 
> 		s2io_reset(sp);
>-		s2io_set_swapper(sp);
> 
> 		if (s2io_rldram_test(sp, &data[3]))
> 			ethtest->flags |= ETH_TEST_FL_FAILED;
> 
> 		s2io_reset(sp);
>-		s2io_set_swapper(sp);
> 
> 		if (s2io_eeprom_test(sp, &data[1]))
> 			ethtest->flags |= ETH_TEST_FL_FAILED;
>@@ -4111,45 +4509,96 @@ static void s2io_get_ethtool_stats(struc
> 	nic_t *sp = dev->priv;
> 	StatInfo_t *stat_info = sp->mac_control.stats_info;
> 
>-	tmp_stats[i++] = stat_info->tmac_frms;
>-	tmp_stats[i++] = stat_info->tmac_data_octets;
>-	tmp_stats[i++] = stat_info->tmac_drop_frms;
>-	tmp_stats[i++] = stat_info->tmac_mcst_frms;
>-	tmp_stats[i++] = stat_info->tmac_bcst_frms;
>-	tmp_stats[i++] = stat_info->tmac_pause_ctrl_frms;
>-	tmp_stats[i++] = stat_info->tmac_any_err_frms;
>-	tmp_stats[i++] = stat_info->tmac_vld_ip_octets;
>-	tmp_stats[i++] = stat_info->tmac_vld_ip;
>-	tmp_stats[i++] = stat_info->tmac_drop_ip;
>-	tmp_stats[i++] = stat_info->tmac_icmp;
>-	tmp_stats[i++] = stat_info->tmac_rst_tcp;
>-	tmp_stats[i++] = stat_info->tmac_tcp;
>-	tmp_stats[i++] = stat_info->tmac_udp;
>-	tmp_stats[i++] = stat_info->rmac_vld_frms;
>-	tmp_stats[i++] = stat_info->rmac_data_octets;
>-	tmp_stats[i++] = stat_info->rmac_fcs_err_frms;
>-	tmp_stats[i++] = stat_info->rmac_drop_frms;
>-	tmp_stats[i++] = stat_info->rmac_vld_mcst_frms;
>-	tmp_stats[i++] = stat_info->rmac_vld_bcst_frms;
>-	tmp_stats[i++] = stat_info->rmac_in_rng_len_err_frms;
>-	tmp_stats[i++] = stat_info->rmac_long_frms;
>-	tmp_stats[i++] = stat_info->rmac_pause_ctrl_frms;
>-	tmp_stats[i++] = stat_info->rmac_discarded_frms;
>-	tmp_stats[i++] = stat_info->rmac_usized_frms;
>-	tmp_stats[i++] = stat_info->rmac_osized_frms;
>-	tmp_stats[i++] = stat_info->rmac_frag_frms;
>-	tmp_stats[i++] = stat_info->rmac_jabber_frms;
>-	tmp_stats[i++] = stat_info->rmac_ip;
>-	tmp_stats[i++] = stat_info->rmac_ip_octets;
>-	tmp_stats[i++] = stat_info->rmac_hdr_err_ip;
>-	tmp_stats[i++] = stat_info->rmac_drop_ip;
>-	tmp_stats[i++] = stat_info->rmac_icmp;
>-	tmp_stats[i++] = stat_info->rmac_tcp;
>-	tmp_stats[i++] = stat_info->rmac_udp;
>-	tmp_stats[i++] = stat_info->rmac_err_drp_udp;
>-	tmp_stats[i++] = stat_info->rmac_pause_cnt;
>-	tmp_stats[i++] = stat_info->rmac_accepted_ip;
>-	tmp_stats[i++] = stat_info->rmac_err_tcp;
>+	s2io_updt_stats(sp);
>+	tmp_stats[i++] =
>+		(u64)le32_to_cpu(stat_info->tmac_frms_oflow) << 32  |
>+		le32_to_cpu(stat_info->tmac_frms);
>+	tmp_stats[i++] =
>+		(u64)le32_to_cpu(stat_info->tmac_data_octets_oflow) << 32 |
>+		le32_to_cpu(stat_info->tmac_data_octets);
>+	tmp_stats[i++] = le64_to_cpu(stat_info->tmac_drop_frms);
>+	tmp_stats[i++] =
>+		(u64)le32_to_cpu(stat_info->tmac_mcst_frms_oflow) << 32 |
>+		le32_to_cpu(stat_info->tmac_mcst_frms);
>+	tmp_stats[i++] =
>+		(u64)le32_to_cpu(stat_info->tmac_bcst_frms_oflow) << 32 |
>+		le32_to_cpu(stat_info->tmac_bcst_frms);
>+	tmp_stats[i++] = le64_to_cpu(stat_info->tmac_pause_ctrl_frms);
>+	tmp_stats[i++] =
>+		(u64)le32_to_cpu(stat_info->tmac_any_err_frms_oflow) << 32 |
>+		le32_to_cpu(stat_info->tmac_any_err_frms);
>+	tmp_stats[i++] = le64_to_cpu(stat_info->tmac_vld_ip_octets);
>+	tmp_stats[i++] =
>+		(u64)le32_to_cpu(stat_info->tmac_vld_ip_oflow) << 32 |
>+		le32_to_cpu(stat_info->tmac_vld_ip);
>+	tmp_stats[i++] =
>+		(u64)le32_to_cpu(stat_info->tmac_drop_ip_oflow) << 32 |
>+		le32_to_cpu(stat_info->tmac_drop_ip);
>+	tmp_stats[i++] =
>+		(u64)le32_to_cpu(stat_info->tmac_icmp_oflow) << 32 |
>+		le32_to_cpu(stat_info->tmac_icmp);
>+	tmp_stats[i++] =
>+		(u64)le32_to_cpu(stat_info->tmac_rst_tcp_oflow) << 32 |
>+		le32_to_cpu(stat_info->tmac_rst_tcp);
>+	tmp_stats[i++] = le64_to_cpu(stat_info->tmac_tcp);
>+	tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_udp_oflow) << 32 |
>+		le32_to_cpu(stat_info->tmac_udp);
>+	tmp_stats[i++] =
>+		(u64)le32_to_cpu(stat_info->rmac_vld_frms_oflow) << 32 |
>+		le32_to_cpu(stat_info->rmac_vld_frms);
>+	tmp_stats[i++] =
>+		(u64)le32_to_cpu(stat_info->rmac_data_octets_oflow) << 32 |
>+		le32_to_cpu(stat_info->rmac_data_octets);
>+	tmp_stats[i++] = le64_to_cpu(stat_info->rmac_fcs_err_frms);
>+	tmp_stats[i++] = le64_to_cpu(stat_info->rmac_drop_frms);
>+	tmp_stats[i++] =
>+		(u64)le32_to_cpu(stat_info->rmac_vld_mcst_frms_oflow) << 32 |
>+		le32_to_cpu(stat_info->rmac_vld_mcst_frms);
>+	tmp_stats[i++] =
>+		(u64)le32_to_cpu(stat_info->rmac_vld_bcst_frms_oflow) << 32 |
>+		le32_to_cpu(stat_info->rmac_vld_bcst_frms);
>+	tmp_stats[i++] = le32_to_cpu(stat_info->rmac_in_rng_len_err_frms);
>+	tmp_stats[i++] = le64_to_cpu(stat_info->rmac_long_frms);
>+	tmp_stats[i++] = le64_to_cpu(stat_info->rmac_pause_ctrl_frms);
>+	tmp_stats[i++] =
>+		(u64)le32_to_cpu(stat_info->rmac_discarded_frms_oflow) << 32 |
>+		le32_to_cpu(stat_info->rmac_discarded_frms);
>+	tmp_stats[i++] =
>+		(u64)le32_to_cpu(stat_info->rmac_usized_frms_oflow) << 32 |
>+		le32_to_cpu(stat_info->rmac_usized_frms);
>+	tmp_stats[i++] =
>+		(u64)le32_to_cpu(stat_info->rmac_osized_frms_oflow) << 32 |
>+		le32_to_cpu(stat_info->rmac_osized_frms);
>+	tmp_stats[i++] =
>+		(u64)le32_to_cpu(stat_info->rmac_frag_frms_oflow) << 32 |
>+		le32_to_cpu(stat_info->rmac_frag_frms);
>+	tmp_stats[i++] =
>+		(u64)le32_to_cpu(stat_info->rmac_jabber_frms_oflow) << 32 |
>+		le32_to_cpu(stat_info->rmac_jabber_frms);
>+	tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_ip_oflow) << 32 |
>+		le32_to_cpu(stat_info->rmac_ip);
>+	tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ip_octets);
>+	tmp_stats[i++] = le32_to_cpu(stat_info->rmac_hdr_err_ip);
>+	tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_drop_ip_oflow) << 32 |
>+		le32_to_cpu(stat_info->rmac_drop_ip);
>+	tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_icmp_oflow) << 32 |
>+		le32_to_cpu(stat_info->rmac_icmp);
>+	tmp_stats[i++] = le64_to_cpu(stat_info->rmac_tcp);
>+	tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_udp_oflow) << 32 |
>+		le32_to_cpu(stat_info->rmac_udp);
>+	tmp_stats[i++] =
>+		(u64)le32_to_cpu(stat_info->rmac_err_drp_udp_oflow) << 32 |
>+		le32_to_cpu(stat_info->rmac_err_drp_udp);
>+	tmp_stats[i++] =
>+		(u64)le32_to_cpu(stat_info->rmac_pause_cnt_oflow) << 32 |
>+		le32_to_cpu(stat_info->rmac_pause_cnt);
>+	tmp_stats[i++] =
>+		(u64)le32_to_cpu(stat_info->rmac_accepted_ip_oflow) << 32 |
>+		le32_to_cpu(stat_info->rmac_accepted_ip);
>+	tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_tcp);
>+	tmp_stats[i++] = 0;
>+	tmp_stats[i++] = stat_info->sw_stat.single_ecc_errs;
>+	tmp_stats[i++] = stat_info->sw_stat.double_ecc_errs;
> }
> 
> int s2io_ethtool_get_regs_len(struct net_device *dev)
>@@ -4243,18 +4692,15 @@ static struct ethtool_ops netdev_ethtool
> };
> 
> /**
>- *  s2io_ioctl - Entry point for the Ioctl 
>+ *  s2io_ioctl - Entry point for the Ioctl
>  *  @dev :  Device pointer.
>  *  @ifr :  An IOCTL specefic structure, that can contain a pointer to
>  *  a proprietary structure used to pass information to the driver.
>  *  @cmd :  This is used to distinguish between the different commands that
>  *  can be passed to the IOCTL functions.
>  *  Description:
>- *  This function has support for ethtool, adding multiple MAC addresses on 
>- *  the NIC and some DBG commands for the util tool.
>- *  Return value:
>- *  Currently the IOCTL supports no operations, hence by default this
>- *  function returns OP NOT SUPPORTED value.
>+ *  Currently there are no special functionality supported in IOCTL, hence
>+ *  function always return EOPNOTSUPPORTED
>  */
> 
> int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
>@@ -4276,14 +4722,6 @@ int s2io_ioctl(struct net_device *dev, s
> int s2io_change_mtu(struct net_device *dev, int new_mtu)
> {
> 	nic_t *sp = dev->priv;
>-	XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
>-	register u64 val64;
>-
>-	if (netif_running(dev)) {
>-		DBG_PRINT(ERR_DBG, "%s: Must be stopped to ", dev->name);
>-		DBG_PRINT(ERR_DBG, "change its MTU \n");
>-		return -EBUSY;
>-	}
> 
> 	if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
> 		DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n",
>@@ -4291,11 +4729,22 @@ int s2io_change_mtu(struct net_device *d
> 		return -EPERM;
> 	}
> 
>-	/* Set the new MTU into the PYLD register of the NIC */
>-	val64 = new_mtu;
>-	writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
>-
> 	dev->mtu = new_mtu;
>+	if (netif_running(dev)) {
>+		s2io_card_down(sp);
>+		netif_stop_queue(dev);
>+		if (s2io_card_up(sp)) {
>+			DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
>+				  __FUNCTION__);
>+		}
>+		if (netif_queue_stopped(dev))
>+			netif_wake_queue(dev);
>+	} else { /* Device is down */
>+		XENA_dev_config_t __iomem *bar0 = sp->bar0;
>+		u64 val64 = new_mtu;
>+
>+		writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
>+	}
> 
> 	return 0;
> }
>@@ -4305,9 +4754,9 @@ int s2io_change_mtu(struct net_device *d
>  *  @dev_adr : address of the device structure in dma_addr_t format.
>  *  Description:
>  *  This is the tasklet or the bottom half of the ISR. This is
>- *  an extension of the ISR which is scheduled by the scheduler to be run 
>+ *  an extension of the ISR which is scheduled by the scheduler to be run
>  *  when the load on the CPU is low. All low priority tasks of the ISR can
>- *  be pushed into the tasklet. For now the tasklet is used only to 
>+ *  be pushed into the tasklet. For now the tasklet is used only to
>  *  replenish the Rx buffers in the Rx buffer descriptors.
>  *  Return value:
>  *  void.
>@@ -4325,7 +4774,7 @@ static void s2io_tasklet(unsigned long d
> 	config = &sp->config;
> 
> 	if (!TASKLET_IN_USE) {
>-		for (i = 0; i < config->RxRingNum; i++) {
>+		for (i = 0; i < config->rx_ring_num; i++) {
> 			ret = fill_rx_buffers(sp, i);
> 			if (ret == -ENOMEM) {
> 				DBG_PRINT(ERR_DBG, "%s: Out of ",
>@@ -4339,7 +4788,7 @@ static void s2io_tasklet(unsigned long d
> 				break;
> 			}
> 		}
>-		clear_bit(0, (unsigned long *) (&sp->tasklet_status));
>+		clear_bit(0, (&sp->tasklet_status));
> 	}
> }
> 
>@@ -4353,25 +4802,32 @@ static void s2io_set_link(unsigned long 
> {
> 	nic_t *nic = (nic_t *) data;
> 	struct net_device *dev = nic->dev;
>-	XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
>+	XENA_dev_config_t __iomem *bar0 = nic->bar0;
> 	register u64 val64;
> 	u16 subid;
> 
>+	if (test_and_set_bit(0, &(nic->link_state))) {
>+		/* The card is being reset, no point doing anything */
>+		return;
>+	}
>+
> 	subid = nic->pdev->subsystem_device;
>-	/* 
>-	 * Allow a small delay for the NICs self initiated 
>-	 * cleanup to complete.
>-	 */
>-	set_current_state(TASK_UNINTERRUPTIBLE);
>-	schedule_timeout(HZ / 10);
>+	if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
>+		/*
>+		 * Allow a small delay for the NICs self initiated
>+		 * cleanup to complete.
>+		 */
>+		msleep(100);
>+	}
> 
> 	val64 = readq(&bar0->adapter_status);
>-	if (verify_xena_quiescence(val64, nic->device_enabled_once)) {
>+	if (verify_xena_quiescence(nic, val64, nic->device_enabled_once)) {
> 		if (LINK_IS_UP(val64)) {
> 			val64 = readq(&bar0->adapter_control);
> 			val64 |= ADAPTER_CNTL_EN;
> 			writeq(val64, &bar0->adapter_control);
>-			if (CARDS_WITH_FAULTY_LINK_INDICATORS(subid)) {
>+			if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
>+							     subid)) {
> 				val64 = readq(&bar0->gpio_control);
> 				val64 |= GPIO_CTRL_GPIO_0;
> 				writeq(val64, &bar0->gpio_control);
>@@ -4380,20 +4836,24 @@ static void s2io_set_link(unsigned long 
> 				val64 |= ADAPTER_LED_ON;
> 				writeq(val64, &bar0->adapter_control);
> 			}
>-			val64 = readq(&bar0->adapter_status);
>-			if (!LINK_IS_UP(val64)) {
>-				DBG_PRINT(ERR_DBG, "%s:", dev->name);
>-				DBG_PRINT(ERR_DBG, " Link down");
>-				DBG_PRINT(ERR_DBG, "after ");
>-				DBG_PRINT(ERR_DBG, "enabling ");
>-				DBG_PRINT(ERR_DBG, "device \n");
>+			if (s2io_link_fault_indication(nic) ==
>+						MAC_RMAC_ERR_TIMER) {
>+				val64 = readq(&bar0->adapter_status);
>+				if (!LINK_IS_UP(val64)) {
>+					DBG_PRINT(ERR_DBG, "%s:", dev->name);
>+					DBG_PRINT(ERR_DBG, " Link down");
>+					DBG_PRINT(ERR_DBG, "after ");
>+					DBG_PRINT(ERR_DBG, "enabling ");
>+					DBG_PRINT(ERR_DBG, "device \n");
>+				}
> 			}
> 			if (nic->device_enabled_once == FALSE) {
> 				nic->device_enabled_once = TRUE;
> 			}
> 			s2io_link(nic, LINK_UP);
> 		} else {
>-			if (CARDS_WITH_FAULTY_LINK_INDICATORS(subid)) {
>+			if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
>+							      subid)) {
> 				val64 = readq(&bar0->gpio_control);
> 				val64 &= ~GPIO_CTRL_GPIO_0;
> 				writeq(val64, &bar0->gpio_control);
>@@ -4406,14 +4866,131 @@ static void s2io_set_link(unsigned long 
> 		DBG_PRINT(ERR_DBG, "device is not Quiescent\n");
> 		netif_stop_queue(dev);
> 	}
>+	clear_bit(0, &(nic->link_state));
>+}
>+
>+static void s2io_card_down(nic_t * sp)
>+{
>+	int cnt = 0;
>+	XENA_dev_config_t __iomem *bar0 = sp->bar0;
>+	unsigned long flags;
>+	register u64 val64 = 0;
>+
>+	del_timer_sync(&sp->alarm_timer);
>+	/* If s2io_set_link task is executing, wait till it completes. */
>+	while (test_and_set_bit(0, &(sp->link_state))) {
>+		msleep(50);
>+	}
>+	atomic_set(&sp->card_state, CARD_DOWN);
>+
>+	/* disable Tx and Rx traffic on the NIC */
>+	stop_nic(sp);
>+
>+	/* Kill tasklet. */
>+	tasklet_kill(&sp->task);
>+
>+	/* Check if the device is Quiescent and then Reset the NIC */
>+	do {
>+		val64 = readq(&bar0->adapter_status);
>+		if (verify_xena_quiescence(sp, val64, sp->device_enabled_once)) {
>+			break;
>+		}
>+
>+		msleep(50);
>+		cnt++;
>+		if (cnt == 10) {
>+			DBG_PRINT(ERR_DBG,
>+				  "s2io_close:Device not Quiescent ");
>+			DBG_PRINT(ERR_DBG, "adaper status reads 0x%llx\n",
>+				  (unsigned long long) val64);
>+			break;
>+		}
>+	} while (1);
>+	s2io_reset(sp);
>+
>+	/* Waiting till all Interrupt handlers are complete */
>+	cnt = 0;
>+	do {
>+		msleep(10);
>+		if (!atomic_read(&sp->isr_cnt))
>+			break;
>+		cnt++;
>+	} while(cnt < 5);
>+
>+	spin_lock_irqsave(&sp->tx_lock, flags);
>+	/* Free all Tx buffers */
>+	free_tx_buffers(sp);
>+	spin_unlock_irqrestore(&sp->tx_lock, flags);
>+
>+	/* Free all Rx buffers */
>+	spin_lock_irqsave(&sp->rx_lock, flags);
>+	free_rx_buffers(sp);
>+	spin_unlock_irqrestore(&sp->rx_lock, flags);
>+
>+	clear_bit(0, &(sp->link_state));
> }
> 
>-/** 
>+static int s2io_card_up(nic_t * sp)
>+{
>+	int i, ret;
>+	mac_info_t *mac_control;
>+	struct config_param *config;
>+	struct net_device *dev = (struct net_device *) sp->dev;
>+
>+	/* Initialize the H/W I/O registers */
>+	if (init_nic(sp) != 0) {
>+		DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
>+			  dev->name);
>+		return -ENODEV;
>+	}
>+
>+	/*
>+	 * Initializing the Rx buffers. For now we are considering only 1
>+	 * Rx ring and initializing buffers into 30 Rx blocks
>+	 */
>+	mac_control = &sp->mac_control;
>+	config = &sp->config;
>+
>+	for (i = 0; i < config->rx_ring_num; i++) {
>+		if ((ret = fill_rx_buffers(sp, i))) {
>+			DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
>+				  dev->name);
>+			s2io_reset(sp);
>+			free_rx_buffers(sp);
>+			return -ENOMEM;
>+		}
>+		DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
>+			  atomic_read(&sp->rx_bufs_left[i]));
>+	}
>+
>+	/* Setting its receive mode */
>+	s2io_set_multicast(dev);
>+
>+	/* Enable tasklet for the device */
>+	tasklet_init(&sp->task, s2io_tasklet, (unsigned long) dev);
>+
>+	/* Enable Rx Traffic and interrupts on the NIC */
>+	if (start_nic(sp)) {
>+		DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
>+		tasklet_kill(&sp->task);
>+		s2io_reset(sp);
>+		free_irq(dev->irq, dev);
>+		free_rx_buffers(sp);
>+		return -ENODEV;
>+	}
>+
>+	S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
>+
>+	atomic_set(&sp->card_state, CARD_UP);
>+	return 0;
>+}
>+
>+/**
>  * s2io_restart_nic - Resets the NIC.
>  * @data : long pointer to the device private structure
>  * Description:
>  * This function is scheduled to be run by the s2io_tx_watchdog
>- * function after 0.5 secs to reset the NIC. The idea is to reduce 
>+ * function after 0.5 secs to reset the NIC. The idea is to reduce
>  * the run time of the watch dog routine which is run holding a
>  * spin lock.
>  */
>@@ -4423,17 +5000,19 @@ static void s2io_restart_nic(unsigned lo
> 	struct net_device *dev = (struct net_device *) data;
> 	nic_t *sp = dev->priv;
> 
>-	sp->task_flag = 1;
>-	s2io_close(dev);
>-	sp->task_flag = 0;
>-	sp->device_close_flag = TRUE;
>-	s2io_open(dev);
>-	DBG_PRINT(ERR_DBG,
>-		  "%s: was reset by Tx watchdog timer.\n", dev->name);
>+	s2io_card_down(sp);
>+	if (s2io_card_up(sp)) {
>+		DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
>+			  dev->name);
>+	}
>+	netif_wake_queue(dev);
>+	DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n",
>+		  dev->name);
>+
> }
> 
>-/** 
>- *  s2io_tx_watchdog - Watchdog for transmit side. 
>+/**
>+ *  s2io_tx_watchdog - Watchdog for transmit side.
>  *  @dev : Pointer to net device structure
>  *  Description:
>  *  This function is triggered if the Tx Queue is stopped
>@@ -4461,7 +5040,7 @@ static void s2io_tx_watchdog(struct net_
>  *   @len : length of the packet
>  *   @cksum : FCS checksum of the frame.
>  *   @ring_no : the ring from which this RxD was extracted.
>- *   Description: 
>+ *   Description:
>  *   This function is called by the Tx interrupt serivce routine to perform
>  *   some OS related operations on the SKB before passing it to the upper
>  *   layers. It mainly checks if the checksum is OK, if so adds it to the
>@@ -4471,35 +5050,68 @@ static void s2io_tx_watchdog(struct net_
>  *   Return value:
>  *   SUCCESS on success and -1 on failure.
>  */
>-#ifndef CONFIG_2BUFF_MODE
>-static int rx_osm_handler(nic_t * sp, u16 len, RxD_t * rxdp, int ring_no)
>-#else
>-static int rx_osm_handler(nic_t * sp, RxD_t * rxdp, int ring_no,
>-			  buffAdd_t * ba)
>-#endif
>+static int rx_osm_handler(ring_info_t *ring_data, RxD_t * rxdp)
> {
>+	nic_t *sp = ring_data->nic;
> 	struct net_device *dev = (struct net_device *) sp->dev;
>-	struct sk_buff *skb =
>-	    (struct sk_buff *) ((unsigned long) rxdp->Host_Control);
>+	struct sk_buff *skb = (struct sk_buff *)
>+		((unsigned long) rxdp->Host_Control);
>+	int ring_no = ring_data->ring_no;
> 	u16 l3_csum, l4_csum;
> #ifdef CONFIG_2BUFF_MODE
>-	int buf0_len, buf2_len;
>-	struct ethhdr *eth = (struct ethhdr *) ba->ba_0;
>+	int buf0_len = RXD_GET_BUFFER0_SIZE(rxdp->Control_2);
>+	int buf2_len = RXD_GET_BUFFER2_SIZE(rxdp->Control_2);
>+	int get_block = ring_data->rx_curr_get_info.block_index;
>+	int get_off = ring_data->rx_curr_get_info.offset;
>+	buffAdd_t *ba = &ring_data->ba[get_block][get_off];
>+	unsigned char *buff;
>+#else
>+	u16 len = (u16) ((RXD_GET_BUFFER0_SIZE(rxdp->Control_2)) >> 48);;
> #endif
>+	skb->dev = dev;
>+	if (rxdp->Control_1 & RXD_T_CODE) {
>+		unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
>+		DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%llx\n",
>+			  dev->name, err);
>+		dev_kfree_skb(skb);
>+		sp->stats.rx_crc_errors++;
>+		atomic_dec(&sp->rx_bufs_left[ring_no]);
>+		rxdp->Host_Control = 0;
>+		return 0;
>+	}
> 
>-	l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
>-	if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) && (sp->rx_csum)) {
>+	/* Updating statistics */
>+	rxdp->Host_Control = 0;
>+	sp->rx_pkt_count++;
>+	sp->stats.rx_packets++;
>+#ifndef CONFIG_2BUFF_MODE
>+	sp->stats.rx_bytes += len;
>+#else
>+	sp->stats.rx_bytes += buf0_len + buf2_len;
>+#endif
>+
>+#ifndef CONFIG_2BUFF_MODE
>+	skb_put(skb, len);
>+#else
>+	buff = skb_push(skb, buf0_len);
>+	memcpy(buff, ba->ba_0, buf0_len);
>+	skb_put(skb, buf2_len);
>+#endif
>+
>+	if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) &&
>+	    (sp->rx_csum)) {
>+		l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
> 		l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
> 		if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
>-			/* 
>+			/*
> 			 * NIC verifies if the Checksum of the received
> 			 * frame is Ok or not and accordingly returns
> 			 * a flag in the RxD.
> 			 */
> 			skb->ip_summed = CHECKSUM_UNNECESSARY;
> 		} else {
>-			/* 
>-			 * Packet with erroneous checksum, let the 
>+			/*
>+			 * Packet with erroneous checksum, let the
> 			 * upper layers deal with it.
> 			 */
> 			skb->ip_summed = CHECKSUM_NONE;
>@@ -4508,77 +5120,29 @@ static int rx_osm_handler(nic_t * sp, Rx
> 		skb->ip_summed = CHECKSUM_NONE;
> 	}
> 
>-	if (rxdp->Control_1 & RXD_T_CODE) {
>-		unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
>-		DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%llx\n",
>-			  dev->name, err);
>-	}
>-#ifdef CONFIG_2BUFF_MODE
>-	buf0_len = RXD_GET_BUFFER0_SIZE(rxdp->Control_2);
>-	buf2_len = RXD_GET_BUFFER2_SIZE(rxdp->Control_2);
>-#endif
>-
>-	skb->dev = dev;
>-#ifndef CONFIG_2BUFF_MODE
>-	skb_put(skb, len);
> 	skb->protocol = eth_type_trans(skb, dev);
>-#else
>-	skb_put(skb, buf2_len);
>-	/* 
>-	 * Reproducing eth_type_trans functionality and running
>-	 * on the ethernet header 'eth' stripped and given to us
>-	 * by the hardware in 2Buff mode.
>-	 */
>-	if (*eth->h_dest & 1) {
>-		if (!memcmp(eth->h_dest, dev->broadcast, ETH_ALEN))
>-			skb->pkt_type = PACKET_BROADCAST;
>-		else
>-			skb->pkt_type = PACKET_MULTICAST;
>-	} else if (memcmp(eth->h_dest, dev->dev_addr, ETH_ALEN)) {
>-		skb->pkt_type = PACKET_OTHERHOST;
>-	}
>-	skb->protocol = eth->h_proto;
>-#endif
>-
> #ifdef CONFIG_S2IO_NAPI
>-	netif_receive_skb(skb);
>+	if (sp->vlgrp && RXD_GET_VLAN_TAG(rxdp->Control_2)) {
>+		/* Queueing the vlan frame to the upper layer */
>+		vlan_hwaccel_receive_skb(skb, sp->vlgrp,
>+			RXD_GET_VLAN_TAG(rxdp->Control_2));
>+	} else {
>+		netif_receive_skb(skb);
>+	}
> #else
>-	netif_rx(skb);
>+	if (sp->vlgrp && RXD_GET_VLAN_TAG(rxdp->Control_2)) {
>+		/* Queueing the vlan frame to the upper layer */
>+		vlan_hwaccel_rx(skb, sp->vlgrp,
>+			RXD_GET_VLAN_TAG(rxdp->Control_2));
>+	} else {
>+		netif_rx(skb);
>+	}
> #endif
>-
> 	dev->last_rx = jiffies;
>-	sp->rx_pkt_count++;
>-	sp->stats.rx_packets++;
>-#ifndef CONFIG_2BUFF_MODE
>-	sp->stats.rx_bytes += len;
>-#else
>-	sp->stats.rx_bytes += buf0_len + buf2_len;
>-#endif
>-
> 	atomic_dec(&sp->rx_bufs_left[ring_no]);
>-	rxdp->Host_Control = 0;
> 	return SUCCESS;
> }
> 
>-int check_for_tx_space(nic_t * sp)
>-{
>-	u32 put_off, get_off, queue_len;
>-	int ret = TRUE, i;
>-
>-	for (i = 0; i < sp->config.TxFIFONum; i++) {
>-		queue_len = sp->mac_control.tx_curr_put_info[i].fifo_len
>-		    + 1;
>-		put_off = sp->mac_control.tx_curr_put_info[i].offset;
>-		get_off = sp->mac_control.tx_curr_get_info[i].offset;
>-		if (((put_off + 1) % queue_len) == get_off) {
>-			ret = FALSE;
>-			break;
>-		}
>-	}
>-
>-	return ret;
>-}
>-
> /**
>  *  s2io_link - stops/starts the Tx queue.
>  *  @sp : private member of the device structure, which is a pointer to the
>@@ -4586,8 +5150,8 @@ int check_for_tx_space(nic_t * sp)
>  *  @link : inidicates whether link is UP/DOWN.
>  *  Description:
>  *  This function stops/starts the Tx queue depending on whether the link
>- *  status of the NIC is is down or up. This is called by the Alarm 
>- *  interrupt handler whenever a link change interrupt comes up. 
>+ *  status of the NIC is is down or up. This is called by the Alarm
>+ *  interrupt handler whenever a link change interrupt comes up.
>  *  Return value:
>  *  void.
>  */
>@@ -4609,7 +5173,7 @@ void s2io_link(nic_t * sp, int link)
> }
> 
> /**
>- *  get_xena_rev_id - to identify revision ID of xena. 
>+ *  get_xena_rev_id - to identify revision ID of xena.
>  *  @pdev : PCI Dev structure
>  *  Description:
>  *  Function to identify the Revision ID of xena.
>@@ -4626,8 +5190,8 @@ int get_xena_rev_id(struct pci_dev *pdev
> }
> 
> /**
>- *  s2io_init_pci -Initialization of PCI and PCI-X configuration registers . 
>- *  @sp : private member of the device structure, which is a pointer to the 
>+ *  s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
>+ *  @sp : private member of the device structure, which is a pointer to the
>  *  s2io_nic structure.
>  *  Description:
>  *  This function initializes a few of the PCI and PCI-X configuration registers
>@@ -4638,15 +5202,15 @@ int get_xena_rev_id(struct pci_dev *pdev
> 
> static void s2io_init_pci(nic_t * sp)
> {
>-	u16 pci_cmd = 0;
>+	u16 pci_cmd = 0, pcix_cmd = 0;
> 
> 	/* Enable Data Parity Error Recovery in PCI-X command register. */
> 	pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
>-			     &(sp->pcix_cmd));
>+			     &(pcix_cmd));
> 	pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
>-			      (sp->pcix_cmd | 1));
>+			      (pcix_cmd | 1));
> 	pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
>-			     &(sp->pcix_cmd));
>+			     &(pcix_cmd));
> 
> 	/* Set the PErr Response bit in PCI command register. */
> 	pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
>@@ -4654,100 +5218,43 @@ static void s2io_init_pci(nic_t * sp)
> 			      (pci_cmd | PCI_COMMAND_PARITY));
> 	pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
> 
>-	/* Set user specified value in Latency Timer */
>-	if (latency_timer) {
>-		pci_write_config_byte(sp->pdev, PCI_LATENCY_TIMER,
>-				      latency_timer);
>-		pci_read_config_byte(sp->pdev, PCI_LATENCY_TIMER,
>-				     &latency_timer);
>-	}
>-
>-	/* Set MMRB count to 4096 in PCI-X Command register. */
>-	sp->pcix_cmd &= 0xFFF3;
>-	pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
>-			      (sp->pcix_cmd | (max_read_byte_cnt << 2)));
>-	pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
>-			     &(sp->pcix_cmd));
>-
>-	/*  Setting Maximum outstanding splits based on system type. */
>-	sp->pcix_cmd &= 0xFF8F;
>-
>-	sp->pcix_cmd |= XENA_MAX_OUTSTANDING_SPLITS(max_splits_trans);
>-	pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
>-			      sp->pcix_cmd);
>-	pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
>-			     &(sp->pcix_cmd));
> 	/* Forcibly disabling relaxed ordering capability of the card. */
>-	sp->pcix_cmd &= 0xfffd;
>+	pcix_cmd &= 0xfffd;
> 	pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
>-			      sp->pcix_cmd);
>+			      pcix_cmd);
> 	pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
>-			     &(sp->pcix_cmd));
>+			     &(pcix_cmd));
> }
> 
>-MODULE_AUTHOR("Raghavendra Koushik <raghavendra.koushik@s2io.com>");
>+MODULE_AUTHOR("Raghavendra Koushik <raghavendra.koushik@neterion.com>");
> MODULE_LICENSE("GPL");
>-MODULE_PARM(lso_enable, "i");
>+module_param(tx_fifo_num, int, 0);
>+module_param(rx_ring_num, int, 0);
>+module_param_array(tx_fifo_len, int, tx_fifo_num, 0);
>+module_param_array(rx_ring_sz, int, rx_ring_num, 0);
>+module_param_array(rts_frm_len, int, rx_ring_num, 0);
>+module_param(use_continuous_tx_intrs, int, 1);
>+module_param(rmac_pause_time, int, 0);
>+module_param(mc_pause_threshold_q0q3, int, 0);
>+module_param(mc_pause_threshold_q4q7, int, 0);
>+module_param(shared_splits, int, 0);
>+module_param(tmac_util_period, int, 0);
>+module_param(rmac_util_period, int, 0);
>+module_param(bimodal, bool, 0);
> #ifndef CONFIG_S2IO_NAPI
>-MODULE_PARM(indicate_max_pkts, "i");
>+module_param(indicate_max_pkts, int, 0);
> #endif
>-MODULE_PARM(cksum_offload_enable, "i");
>-MODULE_PARM(TxFifoNum, "i");
>-MODULE_PARM(TxFIFOLen_0, "i");
>-MODULE_PARM(TxFIFOLen_1, "i");
>-MODULE_PARM(TxFIFOLen_2, "i");
>-MODULE_PARM(TxFIFOLen_3, "i");
>-MODULE_PARM(TxFIFOLen_4, "i");
>-MODULE_PARM(TxFIFOLen_5, "i");
>-MODULE_PARM(TxFIFOLen_6, "i");
>-MODULE_PARM(TxFIFOLen_7, "i");
>-MODULE_PARM(MaxTxDs, "i");
>-MODULE_PARM(RxRingNum, "i");
>-MODULE_PARM(RxRingSz_0, "i");
>-MODULE_PARM(RxRingSz_1, "i");
>-MODULE_PARM(RxRingSz_2, "i");
>-MODULE_PARM(RxRingSz_3, "i");
>-MODULE_PARM(RxRingSz_4, "i");
>-MODULE_PARM(RxRingSz_5, "i");
>-MODULE_PARM(RxRingSz_6, "i");
>-MODULE_PARM(RxRingSz_7, "i");
>-MODULE_PARM(Stats_refresh_time, "i");
>-MODULE_PARM(rmac_pause_time, "i");
>-MODULE_PARM(mc_pause_threshold_q0q3, "i");
>-MODULE_PARM(mc_pause_threshold_q4q7, "i");
>-MODULE_PARM(shared_splits, "i");
>-MODULE_PARM(max_splits_trans, "i");
>-MODULE_PARM(tmac_util_period, "i");
>-MODULE_PARM(rmac_util_period, "i");
>-MODULE_PARM(tx_timer_val, "i");
>-MODULE_PARM(tx_utilz_periodic, "i");
>-MODULE_PARM(rx_timer_val, "i");
>-MODULE_PARM(rx_utilz_periodic, "i");
>-MODULE_PARM(tx_urange_a, "i");
>-MODULE_PARM(tx_ufc_a, "i");
>-MODULE_PARM(tx_urange_b, "i");
>-MODULE_PARM(tx_ufc_b, "i");
>-MODULE_PARM(tx_urange_c, "i");
>-MODULE_PARM(tx_ufc_c, "i");
>-MODULE_PARM(tx_ufc_d, "i");
>-MODULE_PARM(rx_urange_a, "i");
>-MODULE_PARM(rx_ufc_a, "i");
>-MODULE_PARM(rx_urange_b, "i");
>-MODULE_PARM(rx_ufc_b, "i");
>-MODULE_PARM(rx_urange_c, "i");
>-MODULE_PARM(rx_ufc_c, "i");
>-MODULE_PARM(rx_ufc_d, "i");
>-MODULE_PARM(latency_timer, "i");
>-MODULE_PARM(max_read_byte_cnt, "i");
>+module_param(rxsync_frequency, int, 0);
>+
> /**
>- *  s2io_init_nic - Initialization of the adapter . 
>+ *  s2io_init_nic - Initialization of the adapter .
>  *  @pdev : structure containing the PCI related information of the device.
>  *  @pre: List of PCI devices supported by the driver listed in s2io_tbl.
>  *  Description:
>  *  The function initializes an adapter identified by the pci_dec structure.
>- *  All OS related initialization including memory and device structure and 
>- *  initlaization of the device private variable is done. Also the swapper 
>- *  control register is initialized to enable read and write into the I/O 
>+ *  All OS related initialization including memory and device structure and
>+ *  initlaization of the device private variable is done. Also the swapper
>+ *  control register is initialized to enable read and write into the I/O
>  *  registers of the device.
>  *  Return value:
>  *  returns 0 on success and negative on failure.
>@@ -4758,16 +5265,19 @@ s2io_init_nic(struct pci_dev *pdev, cons
> {
> 	nic_t *sp;
> 	struct net_device *dev;
>-	char *dev_name = "S2IO 10GE NIC";
> 	int i, j, ret;
> 	int dma_flag = FALSE;
> 	u32 mac_up, mac_down;
> 	u64 val64 = 0, tmp64 = 0;
>-	XENA_dev_config_t *bar0 = NULL;
>+	XENA_dev_config_t __iomem *bar0 = NULL;
> 	u16 subid;
> 	mac_info_t *mac_control;
> 	struct config_param *config;
>+	int mode;
> 
>+#ifdef CONFIG_S2IO_NAPI
>+	DBG_PRINT(ERR_DBG, "NAPI support has been enabled\n");
>+#endif
> 
> 	if ((ret = pci_enable_device(pdev))) {
> 		DBG_PRINT(ERR_DBG,
>@@ -4775,19 +5285,18 @@ s2io_init_nic(struct pci_dev *pdev, cons
> 		return ret;
> 	}
> 
>-	if (!pci_set_dma_mask(pdev, 0xffffffffffffffffULL)) {
>+	if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
> 		DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n");
> 		dma_flag = TRUE;
>-
> 		if (pci_set_consistent_dma_mask
>-		    (pdev, 0xffffffffffffffffULL)) {
>+		    (pdev, DMA_64BIT_MASK)) {
> 			DBG_PRINT(ERR_DBG,
> 				  "Unable to obtain 64bit DMA for \
> 					consistent allocations\n");
> 			pci_disable_device(pdev);
> 			return -ENOMEM;
> 		}
>-	} else if (!pci_set_dma_mask(pdev, 0xffffffffUL)) {
>+	} else if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
> 		DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 32bit DMA\n");
> 	} else {
> 		pci_disable_device(pdev);
>@@ -4818,122 +5327,104 @@ s2io_init_nic(struct pci_dev *pdev, cons
> 	memset(sp, 0, sizeof(nic_t));
> 	sp->dev = dev;
> 	sp->pdev = pdev;
>-	sp->vendor_id = pdev->vendor;
>-	sp->device_id = pdev->device;
> 	sp->high_dma_flag = dma_flag;
>-	sp->irq = pdev->irq;
> 	sp->device_enabled_once = FALSE;
>-	strcpy(sp->name, dev_name);
>+
>+	if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
>+		(pdev->device == PCI_DEVICE_ID_HERC_UNI))
>+		sp->device_type = XFRAME_II_DEVICE;
>+	else
>+		sp->device_type = XFRAME_I_DEVICE;
> 
> 	/* Initialize some PCI/PCI-X fields of the NIC. */
> 	s2io_init_pci(sp);
> 
>-	/* 
>+	/*
> 	 * Setting the device configuration parameters.
>-	 * Most of these parameters can be specified by the user during 
>-	 * module insertion as they are module loadable parameters. If 
>-	 * these parameters are not not specified during load time, they 
>+	 * Most of these parameters can be specified by the user during
>+	 * module insertion as they are module loadable parameters. If
>+	 * these parameters are not not specified during load time, they
> 	 * are initialized with default values.
> 	 */
> 	mac_control = &sp->mac_control;
> 	config = &sp->config;
> 
> 	/* Tx side parameters. */
>-	config->TxFIFONum = TxFifoNum;
>-	config->tx_cfg[0].FifoLen = TxFIFOLen_0;
>-	config->tx_cfg[0].FifoPriority = 0;
>-	config->tx_cfg[1].FifoLen = TxFIFOLen_1;
>-	config->tx_cfg[1].FifoPriority = 1;
>-	config->tx_cfg[2].FifoLen = TxFIFOLen_2;
>-	config->tx_cfg[2].FifoPriority = 2;
>-	config->tx_cfg[3].FifoLen = TxFIFOLen_3;
>-	config->tx_cfg[3].FifoPriority = 3;
>-	config->tx_cfg[4].FifoLen = TxFIFOLen_4;
>-	config->tx_cfg[4].FifoPriority = 4;
>-	config->tx_cfg[5].FifoLen = TxFIFOLen_5;
>-	config->tx_cfg[5].FifoPriority = 5;
>-	config->tx_cfg[6].FifoLen = TxFIFOLen_6;
>-	config->tx_cfg[6].FifoPriority = 6;
>-	config->tx_cfg[7].FifoLen = TxFIFOLen_7;
>-	config->tx_cfg[7].FifoPriority = 7;
>-
>-	config->TxIntrType = TXD_INT_TYPE_UTILZ;
>-	for (i = 0; i < config->TxFIFONum; i++) {
>-		config->tx_cfg[i].fNoSnoop =
>+	if (tx_fifo_len[0] == 0)
>+		tx_fifo_len[0] = DEFAULT_FIFO_LEN; /* Default value. */
>+	config->tx_fifo_num = tx_fifo_num;
>+	for (i = 0; i < MAX_TX_FIFOS; i++) {
>+		config->tx_cfg[i].fifo_len = tx_fifo_len[i];
>+		config->tx_cfg[i].fifo_priority = i;
>+	}
>+
>+	/* mapping the QoS priority to the configured fifos */
>+	for (i = 0; i < MAX_TX_FIFOS; i++)
>+		config->fifo_mapping[i] = fifo_map[config->tx_fifo_num][i];
>+
>+	config->tx_intr_type = TXD_INT_TYPE_UTILZ;
>+	for (i = 0; i < config->tx_fifo_num; i++) {
>+		config->tx_cfg[i].f_no_snoop =
> 		    (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
>-		if (config->tx_cfg[i].FifoLen < 65) {
>-			config->TxIntrType = TXD_INT_TYPE_PER_LIST;
>+		if (config->tx_cfg[i].fifo_len < 65) {
>+			config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
> 			break;
> 		}
> 	}
>-	config->MaxTxDs = MAX_SKB_FRAGS;
>-	config->TxFlow = TRUE;
>+	config->max_txds = MAX_SKB_FRAGS + 1;
> 
> 	/* Rx side parameters. */
>-	config->RxRingNum = RxRingNum;
>-	config->rx_cfg[0].NumRxd = RxRingSz_0 * (MAX_RXDS_PER_BLOCK + 1);
>-	config->rx_cfg[0].RingPriority = 0;
>-	config->rx_cfg[1].NumRxd = RxRingSz_1 * (MAX_RXDS_PER_BLOCK + 1);
>-	config->rx_cfg[1].RingPriority = 1;
>-	config->rx_cfg[2].NumRxd = RxRingSz_2 * (MAX_RXDS_PER_BLOCK + 1);
>-	config->rx_cfg[2].RingPriority = 2;
>-	config->rx_cfg[3].NumRxd = RxRingSz_3 * (MAX_RXDS_PER_BLOCK + 1);
>-	config->rx_cfg[3].RingPriority = 3;
>-	config->rx_cfg[4].NumRxd = RxRingSz_4 * (MAX_RXDS_PER_BLOCK + 1);
>-	config->rx_cfg[4].RingPriority = 4;
>-	config->rx_cfg[5].NumRxd = RxRingSz_5 * (MAX_RXDS_PER_BLOCK + 1);
>-	config->rx_cfg[5].RingPriority = 5;
>-	config->rx_cfg[6].NumRxd = RxRingSz_6 * (MAX_RXDS_PER_BLOCK + 1);
>-	config->rx_cfg[6].RingPriority = 6;
>-	config->rx_cfg[7].NumRxd = RxRingSz_7 * (MAX_RXDS_PER_BLOCK + 1);
>-	config->rx_cfg[7].RingPriority = 7;
>-
>-	for (i = 0; i < RxRingNum; i++) {
>-		config->rx_cfg[i].RingOrg = RING_ORG_BUFF1;
>-		config->rx_cfg[i].RxdThresh = DEFAULT_RXD_THRESHOLD;
>-		config->rx_cfg[i].fNoSnoop =
>-		    (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
>-		config->rx_cfg[i].RxD_BackOff_Interval = TBD;
>+	if (rx_ring_sz[0] == 0)
>+		rx_ring_sz[0] = SMALL_BLK_CNT; /* Default value. */
>+	config->rx_ring_num = rx_ring_num;
>+	for (i = 0; i < MAX_RX_RINGS; i++) {
>+		config->rx_cfg[i].num_rxd = rx_ring_sz[i] *
>+		    (MAX_RXDS_PER_BLOCK + 1);
>+		config->rx_cfg[i].ring_priority = i;
> 	}
> 
>-	config->RxFlow = TRUE;
>-
>-	/* Miscellaneous parameters. */
>-	config->RxVLANEnable = TRUE;
>-	config->MTU = MAX_MTU_VLAN;
>-	config->JumboEnable = FALSE;
>+	for (i = 0; i < rx_ring_num; i++) {
>+		config->rx_cfg[i].ring_org = RING_ORG_BUFF1;
>+		config->rx_cfg[i].f_no_snoop =
>+		    (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
>+	}
> 
> 	/*  Setting Mac Control parameters */
>-	mac_control->txdl_len = MAX_SKB_FRAGS;
> 	mac_control->rmac_pause_time = rmac_pause_time;
> 	mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
> 	mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
> 
> 
> 	/* Initialize Ring buffer parameters. */
>-	for (i = 0; i < config->RxRingNum; i++)
>+	for (i = 0; i < config->rx_ring_num; i++)
> 		atomic_set(&sp->rx_bufs_left[i], 0);
> 
>+	/* Initialize the number of ISRs currently running */
>+	atomic_set(&sp->isr_cnt, 0);
>+
> 	/*  initialize the shared memory used by the NIC and the host */
> 	if (init_shared_mem(sp)) {
> 		DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n",
>-			  dev->name);
>+			  __FUNCTION__);
>+		ret = -ENOMEM;
> 		goto mem_alloc_failed;
> 	}
> 
>-	sp->bar0 = (caddr_t) ioremap(pci_resource_start(pdev, 0),
>+	sp->bar0 = ioremap(pci_resource_start(pdev, 0),
> 				     pci_resource_len(pdev, 0));
> 	if (!sp->bar0) {
> 		DBG_PRINT(ERR_DBG, "%s: S2IO: cannot remap io mem1\n",
> 			  dev->name);
>+		ret = -ENOMEM;
> 		goto bar0_remap_failed;
> 	}
> 
>-	sp->bar1 = (caddr_t) ioremap(pci_resource_start(pdev, 2),
>+	sp->bar1 = ioremap(pci_resource_start(pdev, 2),
> 				     pci_resource_len(pdev, 2));
> 	if (!sp->bar1) {
> 		DBG_PRINT(ERR_DBG, "%s: S2IO: cannot remap io mem2\n",
> 			  dev->name);
>+		ret = -ENOMEM;
> 		goto bar1_remap_failed;
> 	}
> 
>@@ -4942,7 +5433,7 @@ s2io_init_nic(struct pci_dev *pdev, cons
> 
> 	/* Initializing the BAR1 address as the start of the FIFO pointer. */
> 	for (j = 0; j < MAX_TX_FIFOS; j++) {
>-		mac_control->tx_FIFO_start[j] = (TxFIFO_element_t *)
>+		mac_control->tx_FIFO_start[j] = (TxFIFO_element_t __iomem *)
> 		    (sp->bar1 + (j * 0x00020000));
> 	}
> 
>@@ -4954,26 +5445,25 @@ s2io_init_nic(struct pci_dev *pdev, cons
> 	dev->set_multicast_list = &s2io_set_multicast;
> 	dev->do_ioctl = &s2io_ioctl;
> 	dev->change_mtu = &s2io_change_mtu;
>-#ifdef SET_ETHTOOL_OPS
> 	SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
>-#endif
>+	dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
>+	dev->vlan_rx_register = s2io_vlan_rx_register;
>+	dev->vlan_rx_kill_vid = (void *)s2io_vlan_rx_kill_vid;
>+
> 	/*
> 	 * will use eth_mac_addr() for  dev->set_mac_address
> 	 * mac address will be set every time dev->open() is called
> 	 */
>-#ifdef CONFIG_S2IO_NAPI
>+#if defined(CONFIG_S2IO_NAPI)
> 	dev->poll = s2io_poll;
>-	dev->weight = 90;	/* For now. */
>+	dev->weight = 32;
> #endif
> 
>-	dev->features |= NETIF_F_SG;
>-	if (cksum_offload_enable)
>-		dev->features |= NETIF_F_IP_CSUM;
>+	dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
> 	if (sp->high_dma_flag == TRUE)
> 		dev->features |= NETIF_F_HIGHDMA;
> #ifdef NETIF_F_TSO
>-	if (lso_enable)
>-		dev->features |= NETIF_F_TSO;
>+	dev->features |= NETIF_F_TSO;
> #endif
> 
> 	dev->tx_timeout = &s2io_tx_watchdog;
>@@ -4989,28 +5479,36 @@ s2io_init_nic(struct pci_dev *pdev, cons
> 	if (s2io_set_swapper(sp)) {
> 		DBG_PRINT(ERR_DBG, "%s:swapper settings are wrong\n",
> 			  dev->name);
>+		ret = -EAGAIN;
> 		goto set_swap_failed;
> 	}
> 
>-	/* Fix for all "FFs" MAC address problems observed on Alpha platforms */
>-	fix_mac_address(sp);
>-	s2io_reset(sp);
>+	/* Verify if the Herc works on the slot its placed into */
>+	if (sp->device_type & XFRAME_II_DEVICE) {
>+		mode = s2io_verify_pci_mode(sp);
>+		if (mode < 0) {
>+			DBG_PRINT(ERR_DBG, "%s: ", __FUNCTION__);
>+			DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
>+			ret = -EBADSLT;
>+			goto set_swap_failed;
>+		}
>+	}
> 
>-	/*
>-	 * Setting swapper control on the NIC, so the MAC address can be read.
>-	 */
>-	if (s2io_set_swapper(sp)) {
>-		DBG_PRINT(ERR_DBG,
>-			  "%s: S2IO: swapper settings are wrong\n",
>-			  dev->name);
>-		goto set_swap_failed;
>+	/* Not needed for Herc */
>+	if (sp->device_type & XFRAME_I_DEVICE) {
>+		/*
>+		 * Fix for all "FFs" MAC address problems observed on
>+		 * Alpha platforms
>+		 */
>+		fix_mac_address(sp);
>+		s2io_reset(sp);
> 	}
> 
>-	/*  
>+	/*
> 	 * MAC address initialization.
> 	 * For now only one mac address will be read and used.
> 	 */
>-	bar0 = (XENA_dev_config_t *) sp->bar0;
>+	bar0 = sp->bar0;
> 	val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
> 	    RMAC_ADDR_CMD_MEM_OFFSET(0 + MAC_MAC_ADDR_START_OFFSET);
> 	writeq(val64, &bar0->rmac_addr_cmd_mem);
>@@ -5029,32 +5527,28 @@ s2io_init_nic(struct pci_dev *pdev, cons
> 	sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
> 	sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
> 
>-	DBG_PRINT(INIT_DBG,
>-		  "DEFAULT MAC ADDR:0x%02x-%02x-%02x-%02x-%02x-%02x\n",
>-		  sp->def_mac_addr[0].mac_addr[0],
>-		  sp->def_mac_addr[0].mac_addr[1],
>-		  sp->def_mac_addr[0].mac_addr[2],
>-		  sp->def_mac_addr[0].mac_addr[3],
>-		  sp->def_mac_addr[0].mac_addr[4],
>-		  sp->def_mac_addr[0].mac_addr[5]);
>-
> 	/*  Set the factory defined MAC address initially   */
> 	dev->addr_len = ETH_ALEN;
> 	memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
> 
>-	/*  Initialize the tasklet status flag */
>-	atomic_set(&(sp->tasklet_status), 0);
>-
>+	/*
>+	 * Initialize the tasklet status and link state flags
>+	 * and the card state parameter
>+	 */
>+	atomic_set(&(sp->card_state), 0);
>+	sp->tasklet_status = 0;
>+	sp->link_state = 0;
> 
> 	/* Initialize spinlocks */
> 	spin_lock_init(&sp->tx_lock);
> #ifndef CONFIG_S2IO_NAPI
> 	spin_lock_init(&sp->put_lock);
> #endif
>+	spin_lock_init(&sp->rx_lock);
> 
>-	/* 
>-	 * SXE-002: Configure link and activity LED to init state 
>-	 * on driver load. 
>+	/*
>+	 * SXE-002: Configure link and activity LED to init state
>+	 * on driver load.
> 	 */
> 	subid = sp->pdev->subsystem_device;
> 	if ((subid & 0xFF) >= 0x07) {
>@@ -5062,40 +5556,82 @@ s2io_init_nic(struct pci_dev *pdev, cons
> 		val64 |= 0x0000800000000000ULL;
> 		writeq(val64, &bar0->gpio_control);
> 		val64 = 0x0411040400000000ULL;
>-		writeq(val64, (u64 *) ((u8 *) bar0 + 0x2700));
>+		writeq(val64, (void __iomem *) bar0 + 0x2700);
> 		val64 = readq(&bar0->gpio_control);
> 	}
> 
> 	sp->rx_csum = 1;	/* Rx chksum verify enabled by default */
> 
>-#ifdef SNMP_SUPPORT
>-	if (!s2io_bdsnmp_init(dev))
>-		DBG_PRINT(INIT_DBG,
>-			  "Error Creating Proc directory for SNMP\n");
>+	if (register_netdev(dev)) {
>+		DBG_PRINT(ERR_DBG, "Device registration failed\n");
>+		ret = -ENODEV;
>+		goto register_failed;
>+	}
> 
>-	sp->nLinkStatus = 1;
>-#ifdef NETIF_F_TSO
>-	sp->nFeature = 1;
>+	if (sp->device_type & XFRAME_II_DEVICE) {
>+		DBG_PRINT(ERR_DBG, "%s: Neterion Xframe II 10GbE adapter ",
>+			  dev->name);
>+		DBG_PRINT(ERR_DBG, "(rev %d), %s",
>+				get_xena_rev_id(sp->pdev),
>+				s2io_driver_version);
>+#ifdef CONFIG_2BUFF_MODE
>+		DBG_PRINT(ERR_DBG, ", Buffer mode %d",2);
> #endif
>-	memcpy(sp->cVersion, s2io_driver_version + 8, 20);
>-	memcpy(sp->cName, s2io_driver_name, 20);
>-	struct timeval tm;
>-	do_gettimeofday(&tm);
>-	sp->lDate = tm.tv_sec;
>+
>+		DBG_PRINT(ERR_DBG, "\nCopyright(c) 2002-2005 Neterion Inc.\n");
>+		DBG_PRINT(ERR_DBG, "MAC ADDR: %02x:%02x:%02x:%02x:%02x:%02x\n",
>+			  sp->def_mac_addr[0].mac_addr[0],
>+			  sp->def_mac_addr[0].mac_addr[1],
>+			  sp->def_mac_addr[0].mac_addr[2],
>+			  sp->def_mac_addr[0].mac_addr[3],
>+			  sp->def_mac_addr[0].mac_addr[4],
>+			  sp->def_mac_addr[0].mac_addr[5]);
>+		mode = s2io_print_pci_mode(sp);
>+		if (mode < 0) {
>+			DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode ");
>+			ret = -EBADSLT;
>+			goto set_swap_failed;
>+		}
>+	} else {
>+		DBG_PRINT(ERR_DBG, "%s: Neterion Xframe I 10GbE adapter ",
>+			  dev->name);
>+		DBG_PRINT(ERR_DBG, "(rev %d), %s",
>+					get_xena_rev_id(sp->pdev),
>+					s2io_driver_version);
>+#ifdef CONFIG_2BUFF_MODE
>+		DBG_PRINT(ERR_DBG, ", Buffer mode %d",2);
> #endif
>+		DBG_PRINT(ERR_DBG, "\nCopyright(c) 2002-2005 Neterion Inc.\n");
>+		DBG_PRINT(ERR_DBG, "MAC ADDR: %02x:%02x:%02x:%02x:%02x:%02x\n",
>+			  sp->def_mac_addr[0].mac_addr[0],
>+			  sp->def_mac_addr[0].mac_addr[1],
>+			  sp->def_mac_addr[0].mac_addr[2],
>+			  sp->def_mac_addr[0].mac_addr[3],
>+			  sp->def_mac_addr[0].mac_addr[4],
>+			  sp->def_mac_addr[0].mac_addr[5]);
>+	}
>+
>+	/* Initialize device name */
>+	strcpy(sp->name, dev->name);
>+	if (sp->device_type & XFRAME_II_DEVICE)
>+		strcat(sp->name, ": Neterion Xframe II 10GbE adapter");
>+	else
>+		strcat(sp->name, ": Neterion Xframe I 10GbE adapter");
> 
>-	if (register_netdev(dev)) {
>-		DBG_PRINT(ERR_DBG, "Device registration failed\n");
>-		goto register_failed;
>+	/* Initialize bimodal Interrupts */
>+	sp->config.bimodal = bimodal;
>+	if (!(sp->device_type & XFRAME_II_DEVICE) && bimodal) {
>+		sp->config.bimodal = 0;
>+		DBG_PRINT(ERR_DBG,"%s:Bimodal intr not supported by Xframe I\n",
>+			dev->name);
> 	}
> 
>-	/* 
>-	 * Make Link state as off at this point, when the Link change 
>-	 * interrupt comes the state will be automatically changed to 
>+	/*
>+	 * Make Link state as off at this point, when the Link change
>+	 * interrupt comes the state will be automatically changed to
> 	 * the right state.
> 	 */
> 	netif_carrier_off(dev);
>-	sp->last_link_state = LINK_DOWN;
> 
> 	return 0;
> 
>@@ -5112,15 +5648,15 @@ s2io_init_nic(struct pci_dev *pdev, cons
> 	pci_set_drvdata(pdev, NULL);
> 	free_netdev(dev);
> 
>-	return -ENODEV;
>+	return ret;
> }
> 
> /**
>- * s2io_rem_nic - Free the PCI device 
>+ * s2io_rem_nic - Free the PCI device
>  * @pdev: structure containing the PCI related information of the device.
>- * Description: This function is called by the Pci subsystem to release a 
>+ * Description: This function is called by the Pci subsystem to release a
>  * PCI device and free up all resource held up by the device. This could
>- * be in response to a Hot plug event or when the driver is to be removed 
>+ * be in response to a Hot plug event or when the driver is to be removed
>  * from memory.
>  */
> 
>@@ -5144,10 +5680,6 @@ static void __devexit s2io_rem_nic(struc
> 	pci_disable_device(pdev);
> 	pci_release_regions(pdev);
> 	pci_set_drvdata(pdev, NULL);
>-#ifdef SNMP_SUPPORT
>-	s2io_bdsnmp_rem(dev);
>-#endif
>-
> 	free_netdev(dev);
> }
> 
>@@ -5159,13 +5691,11 @@ static void __devexit s2io_rem_nic(struc
> 
> int __init s2io_starter(void)
> {
>-	if (verify_load_parm())
>-		return -ENODEV;
> 	return pci_module_init(&s2io_driver);
> }
> 
> /**
>- * s2io_closer - Cleanup routine for the driver 
>+ * s2io_closer - Cleanup routine for the driver
>  * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
>  */
> 
>@@ -5177,571 +5707,3 @@ void s2io_closer(void)
> 
> module_init(s2io_starter);
> module_exit(s2io_closer);
>-/**
>- * verify_load_parm -  verifies the module loadable parameters
>- * Descriptions: Verifies the module loadable paramters and initializes the
>- * Tx Fifo, Rx Ring and other paramters.
>- */
>-
>-int verify_load_parm()
>-{
>-	int fail = 0;
>-	if (!((lso_enable == 0) || (lso_enable == 1))) {
>-		printk("lso_enable can be either '1' or '0'\n");
>-		fail = 1;
>-	}
>-#ifndef CONFIG_S2IO_NAPI
>-	if ((indicate_max_pkts > (0xFFFFFFFF))) {
>-		printk
>-		    ("indicate_max_pkts can take value greater than zero but less than 2power(32)\n");
>-		fail = 1;
>-	}
>-#endif
>-	if (!((cksum_offload_enable == 0) || (cksum_offload_enable == 1))) {
>-		printk("cksum_offload_enable can be only '0' or '1' \n");
>-		fail = 1;
>-	}
>-	if ((TxFifoNum == 0) || (TxFifoNum > 8)) {
>-		printk("TxFifoNum can take value from 1 to 8\n");
>-		fail = 1;
>-	}
>-	switch (TxFifoNum) {
>-	case 8:
>-		if ((TxFIFOLen_7 == 0) || TxFIFOLen_7 > 8192) {
>-			printk
>-			    ("TxFIFOLen_7 can take value from 1 to 8192\n");
>-			fail = 1;
>-		}
>-	case 7:
>-		if ((TxFIFOLen_6 == 0) || TxFIFOLen_6 > 8192) {
>-			printk
>-			    ("TxFIFOLen_6 can take value from 1 to 8192\n");
>-			fail = 1;
>-		}
>-	case 6:
>-		if ((TxFIFOLen_5 == 0) || TxFIFOLen_5 > 8192) {
>-			printk
>-			    ("TxFIFOLen_5 can take value from 1 to 8192\n");
>-			fail = 1;
>-		}
>-	case 5:
>-		if ((TxFIFOLen_4 == 0) || TxFIFOLen_4 > 8192) {
>-			printk
>-			    ("TxFIFOLen_4 can take value from 1 to 8192\n");
>-			fail = 1;
>-		}
>-	case 4:
>-		if ((TxFIFOLen_3 == 0) || TxFIFOLen_3 > 8192) {
>-			printk
>-			    ("TxFIFOLen_3 can take value from 1 to 8192\n");
>-			fail = 1;
>-		}
>-	case 3:
>-		if ((TxFIFOLen_2 == 0) || TxFIFOLen_2 > 8192) {
>-			printk
>-			    ("TxFIFOLen_2 can take value from 1 to 8192\n");
>-			fail = 1;
>-		}
>-	case 2:
>-		if ((TxFIFOLen_1 == 0) || TxFIFOLen_1 > 8192) {
>-			printk
>-			    ("TxFIFOLen_1 can take value from 1 to 8192\n");
>-			fail = 1;
>-		}
>-	case 1:
>-		if ((TxFIFOLen_0 == 0) || TxFIFOLen_0 > 8192) {
>-			printk
>-			    ("TxFIFOLen_0 can take value from 1 to 8192\n");
>-			fail = 1;
>-		}
>-	}
>-	if ((MaxTxDs > 32) || (MaxTxDs < 1)) {
>-		printk("MaxTxDs can take falue from 1 to 32\n");
>-		fail = 1;
>-	}
>-	if ((RxRingNum > 8) || (RxRingNum < 1)) {
>-		printk("RxRingNum can take falue from 1 to 8\n");
>-		fail = 1;
>-	}
>-	switch (RxRingNum) {
>-	case 8:
>-		if (RxRingSz_7 < 1) {
>-			printk
>-			    ("RxRingSz_7 can take value greater than 0\n");
>-			fail = 1;
>-		}
>-	case 7:
>-		if (RxRingSz_6 < 1) {
>-			printk
>-			    ("RxRingSz_6 can take value greater than 0\n");
>-			fail = 1;
>-		}
>-	case 6:
>-		if (RxRingSz_5 < 1) {
>-			printk
>-			    ("RxRingSz_5 can take value greater than 0\n");
>-			fail = 1;
>-		}
>-	case 5:
>-		if (RxRingSz_4 < 1) {
>-			printk
>-			    ("RxRingSz_4 can take value greater than 0\n");
>-			fail = 1;
>-		}
>-	case 4:
>-		if (RxRingSz_3 < 1) {
>-			printk
>-			    ("RxRingSz_3 can take value greater than 0\n");
>-			fail = 1;
>-		}
>-	case 3:
>-		if (RxRingSz_2 < 1) {
>-			printk
>-			    ("RxRingSz_2 can take value greater than 0\n");
>-			fail = 1;
>-		}
>-	case 2:
>-		if (RxRingSz_1 < 1) {
>-			printk
>-			    ("RxRingSz_1 can take value greater than 0\n");
>-			fail = 1;
>-		}
>-	case 1:
>-		if (RxRingSz_0 < 1) {
>-			printk
>-			    ("RxRingSz_0 can take value greater than 0\n");
>-			fail = 1;
>-		}
>-	}
>-	if ((Stats_refresh_time < 1)) {
>-		printk
>-		    ("Stats_refresh_time cannot be less than 1 second \n");
>-		fail = 1;
>-	}
>-	if (((rmac_pause_time < 0x10) && (rmac_pause_time != 0)) ||
>-	    (rmac_pause_time > 0xFFFF)) {
>-		printk
>-		    ("rmac_pause_time can take value from 16 to 65535\n");
>-		fail = 1;
>-	}
>-	if ((max_splits_trans < 0) || (max_splits_trans > 7)) {
>-		printk("max_splits_trans can take value from 0 to 7\n");
>-		fail = 1;
>-	}
>-	if ((mc_pause_threshold_q0q3 > 0xFE)) {
>-		printk("mc_pause_threshold_q0q3 cannot exceed 254\n");
>-		fail = 1;
>-	}
>-	if ((mc_pause_threshold_q4q7 > 0xFE)) {
>-		printk("mc_pause_threshold_q4q7 cannot exceed 254\n");
>-		fail = 1;
>-	}
>-	if ((latency_timer)
>-	    && ((latency_timer < 8) /* || (latency_timer > 255) */)) {
>-		printk("latency_timer can take value from 8 to 255\n");
>-		fail = 1;
>-	}
>-	if (max_read_byte_cnt > 3) {
>-		printk("max_read_byte_cnt can take value from 0 to 3\n");
>-		fail = 1;
>-	}
>-	if ((shared_splits > 31)) {
>-		printk("shared_splits cannot exceed 31\n");
>-		fail = 1;
>-	}
>-	if (rmac_util_period > 0xF) {
>-		printk("rmac_util_period cannot exceed 15\n");
>-		fail = 1;
>-	}
>-	if (tmac_util_period > 0xF) {
>-		printk("tmac_util_period cannot exceed 15\n");
>-		fail = 1;
>-	}
>-	if ((tx_utilz_periodic > 1) || (rx_utilz_periodic > 1)) {
>-		printk
>-		    ("tx_utilz_periodic & rx_utilz_periodic can be either "
>-		     "'0' or '1'\n");
>-		fail = 1;
>-	}
>-	if ((tx_urange_a > 127) || (tx_urange_b > 127)
>-	    || (tx_urange_c > 127)) {
>-		printk
>-		    ("tx_urange_a, tx_urange_b & tx_urange_c can take value "
>-		     "from 0 to 127\n");
>-		fail = 1;
>-	}
>-	if ((rx_urange_a > 127) || (rx_urange_b > 127)
>-	    || (rx_urange_c > 127)) {
>-		printk
>-		    ("rx_urange_a, rx_urange_b & rx_urange_c can take value "
>-		     "from 0 to 127\n");
>-		fail = 1;
>-	}
>-	if ((tx_ufc_a > 0xffff) || (tx_ufc_b > 0xffff) ||
>-	    (tx_ufc_c > 0xffff) || (tx_ufc_d > 0xffff)) {
>-		printk
>-		    (" tx_ufc_a, tx_ufc_b, tx_ufc_c, tx_ufc_d can take value"
>-		     "from 0 to 65535(0xFFFF)\n");
>-		fail = 1;
>-	}
>-	if ((rx_ufc_a > 0xffff) || (rx_ufc_b > 0xffff) ||
>-	    (rx_ufc_c > 0xffff) || (rx_ufc_d > 0xffff)) {
>-		printk
>-		    (" rx_ufc_a, rx_ufc_b, rx_ufc_c, rx_ufc_d can take value"
>-		     "from 0 to 65535(0xFFFF)\n");
>-		fail = 1;
>-	}
>-	return fail;
>-}
>-
>-#ifdef SNMP_SUPPORT
>-/**
>- * fnBaseDrv - Get the driver information
>- * @pBaseDrv -Pointer to Base driver structure which contains the offset 
>- * and length of each of the field.
>- * Description
>- * This function copies the driver specific information from the dev structure
>- * to the pBaseDrv stucture. It calculates the number of physical adapters by
>- * parsing the dev_base global variable maintained by the kernel. This 
>- * variable has to read locked before accesing.This function is called by
>- * fnBaseReadProc function.
>- *
>- */
>-
>-static void fnBaseDrv(struct stBaseDrv *pBaseDrv, struct net_device *dev)
>-{
>-
>-	struct pci_dev *pdev = NULL;
>-	struct net_device *ndev;
>-	int nCount = 0;
>-	nic_t *sp = (nic_t *) dev->priv;
>-
>-	strncpy(pBaseDrv->m_cName, sp->cName, 20);
>-	strncpy(pBaseDrv->m_cVersion, sp->cVersion, 20);
>-	pBaseDrv->m_nStatus = sp->nLinkStatus;
>-	pBaseDrv->m_nFeature = sp->nFeature;
>-	pBaseDrv->m_nMemorySize = sp->nMemorySize;
>-	sprintf(pBaseDrv->m_cDate, "%ld", sp->lDate);
>-	/* 
>-	 * Find all the ethernet devices on the system using 
>-	 * pci_find_class. Get the private data which will be the 
>-	 * net_device structure assigned by the driver.
>-	 */
>-	while ((pdev =
>-		pci_find_class((PCI_CLASS_NETWORK_ETHERNET << 8), pdev))) {
>-		ndev = (struct net_device *) pci_get_drvdata(pdev);
>-		if (ndev == NULL)
>-			break;
>-		memcpy(pBaseDrv->m_stPhyAdap[nCount].m_cName, ndev->name,
>-		       20);
>-		pBaseDrv->m_stPhyAdap[nCount].m_nIndex = ndev->ifindex;
>-		nCount++;
>-	}
>-	pBaseDrv->m_nPhyCnt = nCount;
>-}
>-
>-/* 
>- *  fnBaseReadProc - Read entry point for the proc file  
>- *  @page - Buffer pointer where the data is written
>- *  @start- Pointer to buffer ptr . It is used if the data is more than a page
>- *  @off- the offset to the page where data is written
>- *  @count - number of bytes to write
>- *  @eof - to indicate end of file
>- *  @data - pointer to device structure.
>- *
>- * Description - 
>- * This function gets  Base driver specific information from the fnBaseDrv 
>- * function and writes into the BDInfo file. This function is called whenever 
>- * the user reads the file. The length of data written cannot exceed 4kb. 
>- * If it exceeds then use the start pointer to write multiple pages
>- * Return - the length of the string written to proc file
>- */
>-static int fnBaseReadProc(char *page, char **start, off_t off, int count,
>-			  int *eof, void *data)
>-{
>-	struct stBaseDrv *pBaseDrv;
>-	int nLength = 0;
>-	int nCount = 0;
>-	struct net_device *dev = (struct net_device *) data;
>-	int nIndex = 0;
>-
>-	pBaseDrv = kmalloc(sizeof(struct stBaseDrv), GFP_KERNEL);
>-	if (pBaseDrv == NULL) {
>-		printk("Error allocating memory\n");
>-		return -ENOMEM;
>-	}
>-	fnBaseDrv(pBaseDrv, dev);
>-	sprintf(page + nLength, "%-30s%-20s\n", "Base Driver Name",
>-		pBaseDrv->m_cName);
>-	nLength += 51;
>-	if (pBaseDrv->m_nStatus == 1)
>-		sprintf(page + nLength, "%-30s%-20s\n", "Load Status",
>-			"Loaded");
>-	else
>-		sprintf(page + nLength, "%-30s%-20s\n", "Load Status",
>-			"UnLoaded");
>-	nLength += 51;
>-	sprintf(page + nLength, "%-30s%-20s\n", "Base Driver Version",
>-		pBaseDrv->m_cVersion);
>-	nLength += 51;
>-
>-	sprintf(page + nLength, "%-30s%-20d\n", "Feature Supported",
>-		pBaseDrv->m_nFeature);
>-	nLength += 51;
>-
>-	sprintf(page + nLength, "%-30s%-20d\n",
>-		"Base Driver Memrory in Bytes", pBaseDrv->m_nMemorySize);
>-	nLength += 51;
>-
>-	sprintf(page + nLength, "%-30s%-20s\n", "Base Driver Date",
>-		pBaseDrv->m_cDate);
>-	nLength += 51;
>-
>-	sprintf(page + nLength, "%-30s%-20d\n", "No of Phy Adapter",
>-		pBaseDrv->m_nPhyCnt);
>-	nLength += 51;
>-	sprintf(page + nLength, "%-20s%-20s\n\n", "Phy Adapter Index",
>-		"Phy Adapter Name");
>-	nLength += 42;
>-
>-	for (nIndex = 0, nCount = pBaseDrv->m_nPhyCnt; nCount != 0;
>-	     nCount--, nIndex++) {
>-		sprintf(page + nLength, "%-20d%-20s\n",
>-			pBaseDrv->m_stPhyAdap[nIndex].m_nIndex,
>-			pBaseDrv->m_stPhyAdap[nIndex].m_cName);
>-		nLength += 41;
>-	}
>-
>-	*eof = 1;
>-	kfree(pBaseDrv);
>-	return nLength;
>-}
>-
>-/* 
>- *  fnPhyAdapReadProc - Read entry point for the proc file  
>- *  @page - Buffer pointer where the data is written
>- *  @start- Pointer to buffer ptr . It is used if the data is more than a page
>- *  @off- the offset to the page where data is written
>- *  @count - number of bytes to write
>- *  @eof - to indicate end of file
>- *  @data - pointer to device structure.
>- *
>- * Description - 
>- * This function gets  physical adapter information. This function is called
>- * whenever the use* r reads the file. The length of data written cannot
>- * exceed 4kb. If it exceeds then use the start pointer to write multiple page 
>- *
>- * Return - the length of the string written to proc file
>- */
>-static int fnPhyAdapReadProc(char *page, char **start, off_t off,
>-			     int count, int *eof, void *data)
>-{
>-
>-	struct stPhyData *pPhyData;
>-	pPhyData = kmalloc(sizeof(struct stPhyData), GFP_KERNEL);
>-	if (pPhyData == NULL) {
>-		printk("Error allocating memory\n");
>-		return -ENOMEM;
>-	}
>-
>-	struct net_device *pNetDev;
>-	struct net_device_stats *pNetStat;
>-	int nLength = 0;
>-	unsigned char cMAC[20];
>-
>-	/* Print the header in the PhyAdap proc file */
>-	sprintf(page + nLength,
>-		"%-10s%-22s%-10s%-10s%-22s%-22s%-10s%-10s%-10s%-10s%-10s%-10s%-10s%-10s%-10s%-10s%-10s%-10s%-10s%-10s\n",
>-		"Index", "Description", "Mode", "Type", "Speed", "MAC",
>-		"Status", "Slot", "Bus", "IRQ", "Colis", "Multi",
>-		"RxBytes", "RxDrop", "RxError", "RxPacket", "TRxBytes",
>-		"TRxDrop", "TxError", "TxPacket");
>-
>-	/* 237 is the lenght of the above string copied in the page  */
>-	nLength += 237;
>-
>-	struct pci_dev *pdev = NULL;
>-	/* 
>-	 * pci_find_class will return to the pointer to the pdev structure
>-	 * for all the network devices using PCI_CLASS_NETWORK_ETHERNET.
>-	 * The third argument is pointer to previous pdev structure.Initailly
>-	 * it has to be null
>-	 */
>-	while ((pdev =
>-		pci_find_class((PCI_CLASS_NETWORK_ETHERNET << 8), pdev))) {
>-		/* Private data will point to the netdevice structure */
>-		pNetDev = (struct net_device *) pci_get_drvdata(pdev);
>-		if (pNetDev == NULL)
>-			continue;
>-		if (pNetDev->addr_len != 0) {
>-			pNetStat = pNetDev->get_stats(pNetDev);
>-			pPhyData->m_nIndex = pNetDev->ifindex;
>-			memcpy(pPhyData->m_cDesc, pNetDev->name, 20);
>-			pPhyData->m_nMode = 0;
>-			pPhyData->m_nType = 0;
>-			switch (pPhyData->m_nType) {
>-				/* case IFT_ETHER:
>-				   memcpy(pPhyData->m_cSpeed,"10000000",20);
>-				   break;
>-
>-				   case 9:
>-				   memcpy(pPhyData->m_cSpeed,"4000000",20);
>-				   break; */
>-			default:
>-				memcpy(pPhyData->m_cSpeed, "10000000", 20);
>-				break;
>-			}
>-			memcpy(pPhyData->m_cPMAC, pNetDev->dev_addr,
>-			       ETH_ALEN);
>-			memcpy(pPhyData->m_cCMAC, pNetDev->dev_addr,
>-			       ETH_ALEN);
>-			pPhyData->m_nLinkStatus =
>-			    test_bit(__LINK_STATE_START, &pNetDev->state);
>-			pPhyData->m_nPCISlot = PCI_SLOT(pdev->devfn);
>-			pPhyData->m_nPCIBus = pdev->bus->number;
>-			pPhyData->m_nIRQ = pNetDev->irq;
>-			pPhyData->m_nCollision = pNetStat->collisions;
>-			pPhyData->m_nMulticast = pNetStat->multicast;
>-
>-			pPhyData->m_nRxBytes = pNetStat->rx_bytes;
>-			pPhyData->m_nRxDropped = pNetStat->rx_dropped;
>-			pPhyData->m_nRxErrors = pNetStat->rx_errors;
>-			pPhyData->m_nRxPackets = pNetStat->rx_packets;
>-
>-			pPhyData->m_nTxBytes = pNetStat->tx_bytes;
>-			pPhyData->m_nTxDropped = pNetStat->tx_dropped;
>-			pPhyData->m_nTxErrors = pNetStat->tx_errors;
>-			pPhyData->m_nTxPackets = pNetStat->tx_packets;
>-
>-			sprintf(cMAC, "%02x:%02x:%02x:%02x:%02x:%02x",
>-				pPhyData->m_cPMAC[0], pPhyData->m_cPMAC[1],
>-				pPhyData->m_cPMAC[2], pPhyData->m_cPMAC[3],
>-				pPhyData->m_cPMAC[4],
>-				pPhyData->m_cPMAC[5]);
>-
>-			sprintf(page + nLength,
>-				"%-10d%-22s%-10d%-10d%-22s%-22s%-10d%-10d%-10d%-10d%-10d%-10d%-10d%-10d%-10d%-10d%-10d%-10d%-10d%-10d\n",
>-				pPhyData->m_nIndex, pPhyData->m_cDesc,
>-				pPhyData->m_nMode, pPhyData->m_nType,
>-				pPhyData->m_cSpeed, cMAC,
>-				pPhyData->m_nLinkStatus,
>-				pPhyData->m_nPCISlot, pPhyData->m_nPCIBus,
>-				pPhyData->m_nIRQ, pPhyData->m_nCollision,
>-				pPhyData->m_nMulticast,
>-				pPhyData->m_nRxBytes,
>-				pPhyData->m_nRxDropped,
>-				pPhyData->m_nRxErrors,
>-				pPhyData->m_nRxPackets,
>-				pPhyData->m_nTxBytes,
>-				pPhyData->m_nTxDropped,
>-				pPhyData->m_nTxErrors,
>-				pPhyData->m_nTxPackets);
>-			nLength += 237;
>-		}
>-	}
>-
>-	*eof = 1;
>-
>-	kfree(pPhyData);
>-	return nLength;
>-}
>-
>-/* 
>- * s2io_bdsnmp_init - Entry point to create proc file
>- * @dev-  Pointer to net device structure passed by the driver.
>- * Return 
>- * Success If creates all the files
>- * ERROR_PROC_ENTRY /ERROR_PROC_DIR Error If could not create all the files
>- * Description
>- * This functon is called when the driver is loaded. It creates the S2IO
>- * proc file system in the /proc/net/ directory. This directory is used to 
>- * store the info about the base driver afm driver, lacp, vlan  and nplus.
>- * It checks if S2IO directory already exists else creates it and creates 
>- * the files BDInfo  files and assiciates read function to each of the files.
>- */
>-
>-int s2io_bdsnmp_init(struct net_device *dev)
>-{
>-	struct proc_dir_entry *S2ioDir;
>-	struct proc_dir_entry *BaseDrv;
>-	struct proc_dir_entry *PhyAdap;
>-	int nLength = 0;
>-
>-	nLength = strlen(S2IODIRNAME);
>-	/* IF the directory already exists then just return */
>-	for (S2ioDir = proc_net->subdir; S2ioDir != NULL;
>-	     S2ioDir = S2ioDir->next) {
>-		if ((S2ioDir->namelen == nLength)
>-		    && (!memcmp(S2ioDir->name, S2IODIRNAME, nLength)))
>-			break;
>-	}
>-	if (S2ioDir == NULL)
>-		/* Create the s2io directory */
>-		if (!
>-		    (S2ioDir =
>-		     create_proc_entry(S2IODIRNAME, S_IFDIR, proc_net))) {
>-			DBG_PRINT(INIT_DBG,
>-				  "Error Creating Proc directory for SNMP\n");
>-			return ERROR_PROC_DIR;
>-		}
>-	/* 
>-	 * Create the BDInfo file to store driver info and associate 
>-	 * read funtion.
>-	 */
>-	if (!
>-	    (BaseDrv =
>-	     create_proc_read_entry(BDFILENAME, S_IFREG | S_IRUSR, S2ioDir,
>-				    fnBaseReadProc, (void *) dev))) {
>-		DBG_PRINT(INIT_DBG,
>-			  "Error Creating Proc File for Base Drvr\n");
>-		return ERROR_PROC_ENTRY;
>-	}
>-	if (!
>-	    (PhyAdap =
>-	     create_proc_read_entry(PADAPFILENAME, S_IFREG | S_IRUSR,
>-				    S2ioDir, fnPhyAdapReadProc,
>-				    (void *) dev))) {
>-		DBG_PRINT(INIT_DBG,
>-			  "Error Creating Proc File for Phys Adap\n");
>-		return ERROR_PROC_ENTRY;
>-	}
>-
>-
>-	return SUCCESS;
>-}
>-
>-/**
>- * s2io_bdsnmp_rem : Removes the proc file entry
>- * @dev - pointer to netdevice structre
>- * Return - void
>- * Description
>- * This functon is called when the driver is Unloaded. It checks if the 
>- * S2IO directoy exists and deletes the files in the reverse order of 
>- * creation.
>- */
>-
>-void s2io_bdsnmp_rem(struct net_device *dev)
>-{
>-	int nLength = 0;
>-	struct proc_dir_entry *S2ioDir;
>-	nLength = strlen(S2IODIRNAME);
>-	/* 
>-	 * Check if the S2IO directory exists or not and then delete 
>-	 * all the files in the S2IO Directory 
>-	 */
>-	for (S2ioDir = proc_net->subdir; S2ioDir != NULL;
>-	     S2ioDir = S2ioDir->next) {
>-		if ((S2ioDir->namelen == nLength)
>-		    && (!memcmp(S2ioDir->name, S2IODIRNAME, nLength)))
>-
>-			break;
>-	}
>-	if (S2ioDir == NULL)
>-		return;
>-	remove_proc_entry(BDFILENAME, S2ioDir);
>-	remove_proc_entry(PADAPFILENAME, S2ioDir);
>-	if (S2ioDir->subdir == NULL) {
>-		remove_proc_entry(S2IODIRNAME, proc_net);
>-	}
>-}
>-#endif
>diff -urpN old/drivers/net/s2io.h new/drivers/net/s2io.h
>--- old/drivers/net/s2io.h	2005-09-08 15:45:42.273721072 -0700
>+++ new/drivers/net/s2io.h	2005-09-09 07:19:11.575013040 -0700
>@@ -1,6 +1,6 @@
> /************************************************************************
>- * s2io.h: A Linux PCI-X Ethernet driver for S2IO 10GbE Server NIC
>- * Copyright 2002 Raghavendra Koushik (raghavendra.koushik@s2io.com)
>+ * s2io.h: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
>+ * Copyright(c) 2002-2005 Neterion Inc.
> 
>  * This software may be used and distributed according to the terms of
>  * the GNU General Public License (GPL), incorporated herein by reference.
>@@ -31,6 +31,13 @@
> #define SUCCESS 0
> #define FAILURE -1
> 
>+#ifndef NET_IP_ALIGN
>+#define NET_IP_ALIGN 2
>+#endif
>+
>+/* Maximum time to flicker LED when asked to identify NIC using ethtool */
>+#define MAX_FLICKER_TIME	60000 /* 60 Secs */
>+
> /* Maximum outstanding splits to be configured into xena. */
> typedef enum xena_max_outstanding_splits {
> 	XENA_ONE_SPLIT_TRANSACTION = 0,
>@@ -45,14 +52,10 @@ typedef enum xena_max_outstanding_splits
> #define XENA_MAX_OUTSTANDING_SPLITS(n) (n << 4)
> 
> /*  OS concerned variables and constants */
>-#define WATCH_DOG_TIMEOUT   	5*HZ
>-#define EFILL       			0x1234
>-#define ALIGN_SIZE  			127
>-#define	PCIX_COMMAND_REGISTER	0x62
>-
>-#ifndef SET_ETHTOOL_OPS
>-#define SUPPORTED_10000baseT_Full (1 << 12)
>-#endif
>+#define WATCH_DOG_TIMEOUT		15*HZ
>+#define EFILL				0x1234
>+#define ALIGN_SIZE			127
>+#define	PCIX_COMMAND_REGISTER		0x62
> 
> /*
>  * Debug related variables.
>@@ -75,123 +78,14 @@ int debug_level = ERR_DBG;	/* Default le
> #define L4_CKSUM_OK 0xFFFF
> #define S2IO_JUMBO_SIZE 9600
> 
>+/* Driver statistics maintained by driver */
>+typedef struct {
>+	unsigned long long single_ecc_errs;
>+	unsigned long long double_ecc_errs;
>+} swStat_t;
>+
> /* The statistics block of Xena */
> typedef struct stat_block {
>-#ifdef  __BIG_ENDIAN
>-/* Tx MAC statistics counters. */
>-	u32 tmac_frms;
>-	u32 tmac_data_octets;
>-	u64 tmac_drop_frms;
>-	u32 tmac_mcst_frms;
>-	u32 tmac_bcst_frms;
>-	u64 tmac_pause_ctrl_frms;
>-	u32 tmac_ttl_octets;
>-	u32 tmac_ucst_frms;
>-	u32 tmac_nucst_frms;
>-	u32 tmac_any_err_frms;
>-	u64 tmac_ttl_less_fb_octets;
>-	u64 tmac_vld_ip_octets;
>-	u32 tmac_vld_ip;
>-	u32 tmac_drop_ip;
>-	u32 tmac_icmp;
>-	u32 tmac_rst_tcp;
>-	u64 tmac_tcp;
>-	u32 tmac_udp;
>-	u32 reserved_0;
>-
>-/* Rx MAC Statistics counters. */
>-	u32 rmac_vld_frms;
>-	u32 rmac_data_octets;
>-	u64 rmac_fcs_err_frms;
>-	u64 rmac_drop_frms;
>-	u32 rmac_vld_mcst_frms;
>-	u32 rmac_vld_bcst_frms;
>-	u32 rmac_in_rng_len_err_frms;
>-	u32 rmac_out_rng_len_err_frms;
>-	u64 rmac_long_frms;
>-	u64 rmac_pause_ctrl_frms;
>-	u64 rmac_unsup_ctrl_frms;
>-	u32 rmac_ttl_octets;
>-	u32 rmac_accepted_ucst_frms;
>-	u32 rmac_accepted_nucst_frms;
>-	u32 rmac_discarded_frms;
>-	u32 rmac_drop_events;
>-	u32 reserved_1;
>-	u64 rmac_ttl_less_fb_octets;
>-	u64 rmac_ttl_frms;
>-	u64 reserved_2;
>-	u32 reserved_3;
>-	u32 rmac_usized_frms;
>-	u32 rmac_osized_frms;
>-	u32 rmac_frag_frms;
>-	u32 rmac_jabber_frms;
>-	u32 reserved_4;
>-	u64 rmac_ttl_64_frms;
>-	u64 rmac_ttl_65_127_frms;
>-	u64 reserved_5;
>-	u64 rmac_ttl_128_255_frms;
>-	u64 rmac_ttl_256_511_frms;
>-	u64 reserved_6;
>-	u64 rmac_ttl_512_1023_frms;
>-	u64 rmac_ttl_1024_1518_frms;
>-	u32 reserved_7;
>-	u32 rmac_ip;
>-	u64 rmac_ip_octets;
>-	u32 rmac_hdr_err_ip;
>-	u32 rmac_drop_ip;
>-	u32 rmac_icmp;
>-	u32 reserved_8;
>-	u64 rmac_tcp;
>-	u32 rmac_udp;
>-	u32 rmac_err_drp_udp;
>-	u64 rmac_xgmii_err_sym;
>-	u64 rmac_frms_q0;
>-	u64 rmac_frms_q1;
>-	u64 rmac_frms_q2;
>-	u64 rmac_frms_q3;
>-	u64 rmac_frms_q4;
>-	u64 rmac_frms_q5;
>-	u64 rmac_frms_q6;
>-	u64 rmac_frms_q7;
>-	u16 rmac_full_q0;
>-	u16 rmac_full_q1;
>-	u16 rmac_full_q2;
>-	u16 rmac_full_q3;
>-	u16 rmac_full_q4;
>-	u16 rmac_full_q5;
>-	u16 rmac_full_q6;
>-	u16 rmac_full_q7;
>-	u32 rmac_pause_cnt;
>-	u32 reserved_9;
>-	u64 rmac_xgmii_data_err_cnt;
>-	u64 rmac_xgmii_ctrl_err_cnt;
>-	u32 rmac_accepted_ip;
>-	u32 rmac_err_tcp;
>-
>-/* PCI/PCI-X Read transaction statistics. */
>-	u32 rd_req_cnt;
>-	u32 new_rd_req_cnt;
>-	u32 new_rd_req_rtry_cnt;
>-	u32 rd_rtry_cnt;
>-	u32 wr_rtry_rd_ack_cnt;
>-
>-/* PCI/PCI-X write transaction statistics. */
>-	u32 wr_req_cnt;
>-	u32 new_wr_req_cnt;
>-	u32 new_wr_req_rtry_cnt;
>-	u32 wr_rtry_cnt;
>-	u32 wr_disc_cnt;
>-	u32 rd_rtry_wr_ack_cnt;
>-
>-/*	DMA Transaction statistics. */
>-	u32 txp_wr_cnt;
>-	u32 txd_rd_cnt;
>-	u32 txd_wr_cnt;
>-	u32 rxd_rd_cnt;
>-	u32 rxd_wr_cnt;
>-	u32 txf_rd_cnt;
>-	u32 rxf_wr_cnt;
>-#else
> /* Tx MAC statistics counters. */
> 	u32 tmac_data_octets;
> 	u32 tmac_frms;
>@@ -305,17 +199,94 @@ typedef struct stat_block {
> 	u32 rxd_rd_cnt;
> 	u32 rxf_wr_cnt;
> 	u32 txf_rd_cnt;
>-#endif
>+
>+/* Tx MAC statistics overflow counters. */
>+	u32 tmac_data_octets_oflow;
>+	u32 tmac_frms_oflow;
>+	u32 tmac_bcst_frms_oflow;
>+	u32 tmac_mcst_frms_oflow;
>+	u32 tmac_ucst_frms_oflow;
>+	u32 tmac_ttl_octets_oflow;
>+	u32 tmac_any_err_frms_oflow;
>+	u32 tmac_nucst_frms_oflow;
>+	u64 tmac_vlan_frms;
>+	u32 tmac_drop_ip_oflow;
>+	u32 tmac_vld_ip_oflow;
>+	u32 tmac_rst_tcp_oflow;
>+	u32 tmac_icmp_oflow;
>+	u32 tpa_unknown_protocol;
>+	u32 tmac_udp_oflow;
>+	u32 reserved_10;
>+	u32 tpa_parse_failure;
>+
>+/* Rx MAC Statistics overflow counters. */
>+	u32 rmac_data_octets_oflow;
>+	u32 rmac_vld_frms_oflow;
>+	u32 rmac_vld_bcst_frms_oflow;
>+	u32 rmac_vld_mcst_frms_oflow;
>+	u32 rmac_accepted_ucst_frms_oflow;
>+	u32 rmac_ttl_octets_oflow;
>+	u32 rmac_discarded_frms_oflow;
>+	u32 rmac_accepted_nucst_frms_oflow;
>+	u32 rmac_usized_frms_oflow;
>+	u32 rmac_drop_events_oflow;
>+	u32 rmac_frag_frms_oflow;
>+	u32 rmac_osized_frms_oflow;
>+	u32 rmac_ip_oflow;
>+	u32 rmac_jabber_frms_oflow;
>+	u32 rmac_icmp_oflow;
>+	u32 rmac_drop_ip_oflow;
>+	u32 rmac_err_drp_udp_oflow;
>+	u32 rmac_udp_oflow;
>+	u32 reserved_11;
>+	u32 rmac_pause_cnt_oflow;
>+	u64 rmac_ttl_1519_4095_frms;
>+	u64 rmac_ttl_4096_8191_frms;
>+	u64 rmac_ttl_8192_max_frms;
>+	u64 rmac_ttl_gt_max_frms;
>+	u64 rmac_osized_alt_frms;
>+	u64 rmac_jabber_alt_frms;
>+	u64 rmac_gt_max_alt_frms;
>+	u64 rmac_vlan_frms;
>+	u32 rmac_len_discard;
>+	u32 rmac_fcs_discard;
>+	u32 rmac_pf_discard;
>+	u32 rmac_da_discard;
>+	u32 rmac_red_discard;
>+	u32 rmac_rts_discard;
>+	u32 reserved_12;
>+	u32 rmac_ingm_full_discard;
>+	u32 reserved_13;
>+	u32 rmac_accepted_ip_oflow;
>+	u32 reserved_14;
>+	u32 link_fault_cnt;
>+	swStat_t sw_stat;
> } StatInfo_t;
> 
>-/* Structures representing different init time configuration
>+/*
>+ * Structures representing different init time configuration
>  * parameters of the NIC.
>  */
> 
>+#define MAX_TX_FIFOS 8
>+#define MAX_RX_RINGS 8
>+
>+/* FIFO mappings for all possible number of fifos configured */
>+int fifo_map[][MAX_TX_FIFOS] = {
>+	{0, 0, 0, 0, 0, 0, 0, 0},
>+	{0, 0, 0, 0, 1, 1, 1, 1},
>+	{0, 0, 0, 1, 1, 1, 2, 2},
>+	{0, 0, 1, 1, 2, 2, 3, 3},
>+	{0, 0, 1, 1, 2, 2, 3, 4},
>+	{0, 0, 1, 1, 2, 3, 4, 5},
>+	{0, 0, 1, 2, 3, 4, 5, 6},
>+	{0, 1, 2, 3, 4, 5, 6, 7},
>+};
>+
> /* Maintains Per FIFO related information. */
> typedef struct tx_fifo_config {
> #define	MAX_AVAILABLE_TXDS	8192
>-	u32 FifoLen;		/* specifies len of FIFO upto 8192, ie no of TxDLs */
>+	u32 fifo_len;		/* specifies len of FIFO upto 8192, ie no of TxDLs */
> /* Priority definition */
> #define TX_FIFO_PRI_0               0	/*Highest */
> #define TX_FIFO_PRI_1               1
>@@ -325,9 +296,9 @@ typedef struct tx_fifo_config {
> #define TX_FIFO_PRI_5               5
> #define TX_FIFO_PRI_6               6
> #define TX_FIFO_PRI_7               7	/*lowest */
>-	u8 FifoPriority;	/* specifies pointer level for FIFO */
>+	u8 fifo_priority;	/* specifies pointer level for FIFO */
> 	/* user should not set twos fifos with same pri */
>-	u8 fNoSnoop;
>+	u8 f_no_snoop;
> #define NO_SNOOP_TXD                0x01
> #define NO_SNOOP_TXD_BUFFER          0x02
> } tx_fifo_config_t;
>@@ -335,7 +306,7 @@ typedef struct tx_fifo_config {
> 
> /* Maintains per Ring related information */
> typedef struct rx_ring_config {
>-	u32 NumRxd;		/*No of RxDs per Rx Ring */
>+	u32 num_rxd;		/*No of RxDs per Rx Ring */
> #define RX_RING_PRI_0               0	/* highest */
> #define RX_RING_PRI_1               1
> #define RX_RING_PRI_2               2
>@@ -345,76 +316,42 @@ typedef struct rx_ring_config {
> #define RX_RING_PRI_6               6
> #define RX_RING_PRI_7               7	/* lowest */
> 
>-	u8 RingPriority;	/*Specifies service priority of ring */
>+	u8 ring_priority;	/*Specifies service priority of ring */
> 	/* OSM should not set any two rings with same priority */
>-	u8 RingOrg;		/*Organization of ring */
>-#define RING_ORG_BUFF1           0x01
>-#define RX_RING_ORG_BUFF3           0x03
>-#define RX_RING_ORG_BUFF5           0x05
>-
>-/* In case of 3 buffer recv. mode, size of three buffers is expected as.. */
>-#define BUFF_SZ_1                   22	/* ethernet header */
>-#define BUFF_SZ_2                   (64+64)	/* max. IP+TCP header size */
>-#define BUFF_SZ_3                   (1500-20-20)	/* TCP payload */
>-#define BUFF_SZ_3_JUMBO             (9600-20-20)	/* Jumbo TCP payload */
>-
>-	u32 RxdThresh;		/*No of used Rxds NIC can store before transfer to host */
>-#define DEFAULT_RXD_THRESHOLD       0x1	/* TODO */
>-	u8 fNoSnoop;
>+	u8 ring_org;		/*Organization of ring */
>+#define RING_ORG_BUFF1		0x01
>+#define RX_RING_ORG_BUFF3	0x03
>+#define RX_RING_ORG_BUFF5	0x05
>+
>+	u8 f_no_snoop;
> #define NO_SNOOP_RXD                0x01
> #define NO_SNOOP_RXD_BUFFER         0x02
>-	u32 RxD_BackOff_Interval;
>-#define RXD_BACKOFF_INTERVAL_DEF        0x0
>-#define RXD_BACKOFF_INTERVAL_MIN        0x0
>-#define RXD_BACKOFF_INTERVAL_MAX        0x0
> } rx_ring_config_t;
> 
>-/* This structure provides contains values of the tunable parameters 
>- * of the H/W 
>+/* This structure provides contains values of the tunable parameters
>+ * of the H/W
>  */
> struct config_param {
>-
> /* Tx Side */
>-	u32 TxFIFONum;		/*Number of Tx FIFOs */
>-#define MAX_TX_FIFOS 8
>+	u32 tx_fifo_num;	/*Number of Tx FIFOs */
> 
>+	u8 fifo_mapping[MAX_TX_FIFOS];
> 	tx_fifo_config_t tx_cfg[MAX_TX_FIFOS];	/*Per-Tx FIFO config */
>-	u32 MaxTxDs;		/*Max no. of Tx buffer descriptor per TxDL */
>-	BOOL TxVLANEnable;	/*TRUE: Insert VLAN ID, FALSE: Don't insert */
>-#define TX_REQ_TIMEOUT_DEFAULT          0x0
>-#define TX_REQ_TIMEOUT_MIN              0x0
>-#define TX_REQ_TIMEOUT_MAX              0x0
>-	u32 TxReqTimeOut;
>-	BOOL TxFlow;		/*Tx flow control enable */
>-	BOOL RxFlow;
>-	BOOL OverrideTxServiceState;	/* TRUE: Overide, FALSE: Do not override 
>-					   Use the new priority information
>-					   of service state. It is not recommended
>-					   to change but OSM can opt to do so */
>-#define MAX_SERVICE_STATES  36
>-	u8 TxServiceState[MAX_SERVICE_STATES];
>-	/* Array element represent 'priority' 
>-	 * and array index represents
>-	 *  'Service state' e.g. 
>-	 *  TxServiceState[3]=7; it means 
>-	 *  Service state 3 is associated 
>-	 *  with priority 7 of a Tx FIFO */
>-	u64 TxIntrType;		/* Specifies if Tx Intr is UTILZ or PER_LIST type. */
>+	u32 max_txds;		/*Max no. of Tx buffer descriptor per TxDL */
>+	u64 tx_intr_type;
>+	/* Specifies if Tx Intr is UTILZ or PER_LIST type. */
> 
> /* Rx Side */
>-	u32 RxRingNum;		/*Number of receive rings */
>-#define MAX_RX_RINGS 8
>+	u32 rx_ring_num;	/*Number of receive rings */
> #define MAX_RX_BLOCKS_PER_RING  150
> 
> 	rx_ring_config_t rx_cfg[MAX_RX_RINGS];	/*Per-Rx Ring config */
>-	BOOL RxVLANEnable;	/*TRUE: Strip off VLAN tag from the frame,
>-				   FALSE: Don't strip off VLAN tag */
>+	u8 bimodal;		/*Flag for setting bimodal interrupts*/
> 
> #define HEADER_ETHERNET_II_802_3_SIZE 14
> #define HEADER_802_2_SIZE              3
> #define HEADER_SNAP_SIZE               5
> #define HEADER_VLAN_SIZE               4
>-#define HEADER_ALIGN_LAYER_3           2
> 
> #define MIN_MTU                       46
> #define MAX_PYLD                    1500
>@@ -423,23 +360,7 @@ struct config_param {
> #define MAX_PYLD_JUMBO              9600
> #define MAX_MTU_JUMBO               (MAX_PYLD_JUMBO+18)
> #define MAX_MTU_JUMBO_VLAN          (MAX_PYLD_JUMBO+22)
>-	u32 MTU;		/*Maximum Payload */
>-	BOOL JumboEnable;	/*Enable Jumbo frames recv/send */
>-	BOOL OverrideRxServiceState;	/* TRUE: Overide, FALSE: Do not override 
>-					   Use the new priority information
>-					   of service state. It is not recommended
>-					   to change but OSM can opt to do so */
>-#define MAX_SERVICE_STATES  36
>-	u8 RxServiceState[MAX_SERVICE_STATES];
>-	/* Array element represent 'priority' 
>-	 * and array index represents 
>-	 * 'Service state'e.g. 
>-	 * RxServiceState[3]=7; it means 
>-	 * Service state 3 is associated 
>-	 * with priority 7 of a Rx FIFO */
>-	BOOL StatAutoRefresh;	/* When true, StatRefreshTime have valid value */
>-	u32 StatRefreshTime;	/*Time for refreshing statistics */
>-#define     STAT_TRSF_PER_1_SECOND      0x208D5
>+	u16 bus_speed;
> };
> 
> /* Structure representing MAC Addrs */
>@@ -448,7 +369,7 @@ typedef struct mac_addr {
> } macaddr_t;
> 
> /* Structure that represent every FIFO element in the BAR1
>- * Address location. 
>+ * Address location.
>  */
> typedef struct _TxFIFO_element {
> 	u64 TxDL_Pointer;
>@@ -510,6 +431,7 @@ typedef struct _RxD_t {
> #define RXD_FRAME_PROTO         vBIT(0xFFFF,24,8)
> #define RXD_FRAME_PROTO_IPV4    BIT(27)
> #define RXD_FRAME_PROTO_IPV6    BIT(28)
>+#define RXD_FRAME_IP_FRAG	BIT(29)
> #define RXD_FRAME_PROTO_TCP     BIT(30)
> #define RXD_FRAME_PROTO_UDP     BIT(31)
> #define TCP_OR_UDP_FRAME        (RXD_FRAME_PROTO_TCP | RXD_FRAME_PROTO_UDP)
>@@ -517,11 +439,15 @@ typedef struct _RxD_t {
> #define RXD_GET_L4_CKSUM(val)   ((u16)(val) & 0xFFFF)
> 
> 	u64 Control_2;
>+#define	THE_RXD_MARK		0x3
>+#define	SET_RXD_MARKER		vBIT(THE_RXD_MARK, 0, 2)
>+#define	GET_RXD_MARKER(ctrl)	((ctrl & SET_RXD_MARKER) >> 62)
>+
> #ifndef CONFIG_2BUFF_MODE
>-#define MASK_BUFFER0_SIZE       vBIT(0xFFFF,0,16)
>-#define SET_BUFFER0_SIZE(val)   vBIT(val,0,16)
>+#define MASK_BUFFER0_SIZE       vBIT(0x3FFF,2,14)
>+#define SET_BUFFER0_SIZE(val)   vBIT(val,2,14)
> #else
>-#define MASK_BUFFER0_SIZE       vBIT(0xFF,0,16)
>+#define MASK_BUFFER0_SIZE       vBIT(0xFF,2,14)
> #define MASK_BUFFER1_SIZE       vBIT(0xFFFF,16,16)
> #define MASK_BUFFER2_SIZE       vBIT(0xFFFF,32,16)
> #define SET_BUFFER0_SIZE(val)   vBIT(val,8,8)
>@@ -534,7 +460,7 @@ typedef struct _RxD_t {
> #define SET_NUM_TAG(val)       vBIT(val,16,32)
> 
> #ifndef CONFIG_2BUFF_MODE
>-#define RXD_GET_BUFFER0_SIZE(Control_2) (u64)((Control_2 & vBIT(0xFFFF,0,16)))
>+#define RXD_GET_BUFFER0_SIZE(Control_2) (u64)((Control_2 & vBIT(0x3FFF,2,14)))
> #else
> #define RXD_GET_BUFFER0_SIZE(Control_2) (u8)((Control_2 & MASK_BUFFER0_SIZE) \
> 							>> 48)
>@@ -553,7 +479,7 @@ typedef struct _RxD_t {
> #endif
> } RxD_t;
> 
>-/* Structure that represents the Rx descriptor block which contains 
>+/* Structure that represents the Rx descriptor block which contains
>  * 128 Rx descriptors.
>  */
> #ifndef CONFIG_2BUFF_MODE
>@@ -563,11 +489,11 @@ typedef struct _RxD_block {
> 
> 	u64 reserved_0;
> #define END_OF_BLOCK    0xFEFFFFFFFFFFFFFFULL
>-	u64 reserved_1;		/* 0xFEFFFFFFFFFFFFFF to mark last 
>+	u64 reserved_1;		/* 0xFEFFFFFFFFFFFFFF to mark last
> 				 * Rxd in this blk */
> 	u64 reserved_2_pNext_RxD_block;	/* Logical ptr to next */
> 	u64 pNext_RxD_Blk_physical;	/* Buff0_ptr.In a 32 bit arch
>-					 * the upper 32 bits should 
>+					 * the upper 32 bits should
> 					 * be 0 */
> } RxD_block_t;
> #else
>@@ -576,13 +502,13 @@ typedef struct _RxD_block {
> 	RxD_t rxd[MAX_RXDS_PER_BLOCK];
> 
> #define END_OF_BLOCK    0xFEFFFFFFFFFFFFFFULL
>-	u64 reserved_1;		/* 0xFEFFFFFFFFFFFFFF to mark last Rxd 
>+	u64 reserved_1;		/* 0xFEFFFFFFFFFFFFFF to mark last Rxd
> 				 * in this blk */
> 	u64 pNext_RxD_Blk_physical;	/* Phy ponter to next blk. */
> } RxD_block_t;
> #define SIZE_OF_BLOCK	4096
> 
>-/* Structure to hold virtual addresses of Buf0 and Buf1 in 
>+/* Structure to hold virtual addresses of Buf0 and Buf1 in
>  * 2buf mode. */
> typedef struct bufAdd {
> 	void *ba_0_org;
>@@ -594,8 +520,8 @@ typedef struct bufAdd {
> 
> /* Structure which stores all the MAC control parameters */
> 
>-/* This structure stores the offset of the RxD in the ring 
>- * from which the Rx Interrupt processor can start picking 
>+/* This structure stores the offset of the RxD in the ring
>+ * from which the Rx Interrupt processor can start picking
>  * up the RxDs for processing.
>  */
> typedef struct _rx_curr_get_info_t {
>@@ -607,7 +533,7 @@ typedef struct _rx_curr_get_info_t {
> typedef rx_curr_get_info_t rx_curr_put_info_t;
> 
> /* This structure stores the offset of the TxDl in the FIFO
>- * from which the Tx Interrupt processor can start picking 
>+ * from which the Tx Interrupt processor can start picking
>  * up the TxDLs for send complete interrupt processing.
>  */
> typedef struct {
>@@ -617,57 +543,99 @@ typedef struct {
> 
> typedef tx_curr_get_info_t tx_curr_put_info_t;
> 
>-/* Infomation related to the Tx and Rx FIFOs and Rings of Xena
>- * is maintained in this structure.
>- */
>-typedef struct mac_info {
>-/* rx side stuff */
>-	u32 rxd_ring_mem_sz;
>+/* Structure that holds the Phy and virt addresses of the Blocks */
>+typedef struct rx_block_info {
>+	RxD_t *block_virt_addr;
>+	dma_addr_t block_dma_addr;
>+} rx_block_info_t;
>+
>+/* pre declaration of the nic structure */
>+typedef struct s2io_nic nic_t;
>+
>+/* Ring specific structure */
>+typedef struct ring_info {
>+	/* The ring number */
>+	int ring_no;
>+
>+	/*
>+	 *  Place holders for the virtual and physical addresses of
>+	 *  all the Rx Blocks
>+	 */
>+	rx_block_info_t rx_blocks[MAX_RX_BLOCKS_PER_RING];
>+	int block_count;
>+	int pkt_cnt;
> 
>-	/* Put pointer info which indictes which RxD has to be replenished 
>+	/*
>+	 * Put pointer info which indictes which RxD has to be replenished
> 	 * with a new buffer.
> 	 */
>-	rx_curr_put_info_t rx_curr_put_info[MAX_RX_RINGS];
>+	rx_curr_put_info_t rx_curr_put_info;
> 
>-	/* Get pointer info which indictes which is the last RxD that was 
>+	/*
>+	 * Get pointer info which indictes which is the last RxD that was
> 	 * processed by the driver.
> 	 */
>-	rx_curr_get_info_t rx_curr_get_info[MAX_RX_RINGS];
>+	rx_curr_get_info_t rx_curr_get_info;
> 
>-	u16 rmac_pause_time;
>-	u16 mc_pause_threshold_q0q3;
>-	u16 mc_pause_threshold_q4q7;
>+#ifndef CONFIG_S2IO_NAPI
>+	/* Index to the absolute position of the put pointer of Rx ring */
>+	int put_pos;
>+#endif
> 
>+#ifdef CONFIG_2BUFF_MODE
>+	/* Buffer Address store. */
>+	buffAdd_t **ba;
>+#endif
>+	nic_t *nic;
>+} ring_info_t;
>+
>+/* Fifo specific structure */
>+typedef struct fifo_info {
>+	/* FIFO number */
>+	int fifo_no;
>+
>+	/* Maximum TxDs per TxDL */
>+	int max_txds;
>+
>+	/* Place holder of all the TX List's Phy and Virt addresses. */
>+	list_info_hold_t *list_info;
> 
>-	/* this will be used in receive function, this decides which ring would
>-	   be processed first. eg: ring with priority value 0 (highest) should
>-	   be processed first. 
>-	   first 3 LSB bits represent ring number which should be processed 
>-	   first, similarly next 3 bits represent next ring to be processed.
>-	   eg: value of _rx_ring_pri_map = 0x0000 003A means 
>-	   ring #2 would be processed first and #7 would be processed next
>+	/*
>+	 * Current offset within the tx FIFO where driver would write
>+	 * new Tx frame
> 	 */
>-	u32 _rx_ring_pri_map;
>+	tx_curr_put_info_t tx_curr_put_info;
> 
>-/* tx side stuff */
>-	void *txd_list_mem;	/* orignal pointer to allocated mem */
>-	dma_addr_t txd_list_mem_phy;
>-	u32 txd_list_mem_sz;
>+	/*
>+	 * Current offset within tx FIFO from where the driver would start freeing
>+	 * the buffers
>+	 */
>+	tx_curr_get_info_t tx_curr_get_info;
> 
>+	nic_t *nic;
>+}fifo_info_t;
>+
>+/* Infomation related to the Tx and Rx FIFOs and Rings of Xena
>+ * is maintained in this structure.
>+ */
>+typedef struct mac_info {
>+/* tx side stuff */
> 	/* logical pointer of start of each Tx FIFO */
>-	TxFIFO_element_t *tx_FIFO_start[MAX_TX_FIFOS];
>+	TxFIFO_element_t __iomem *tx_FIFO_start[MAX_TX_FIFOS];
> 
>-	/* logical pointer of start of TxDL which corresponds to each Tx FIFO */
>-	TxD_t *txdl_start[MAX_TX_FIFOS];
>+	/* Fifo specific structure */
>+	fifo_info_t fifos[MAX_TX_FIFOS];
> 
>-	/* Same as txdl_start but phy addr */
>-	dma_addr_t txdl_start_phy[MAX_TX_FIFOS];
>+	/* Save virtual address of TxD page with zero DMA addr(if any) */
>+	void *zerodma_virt_addr;
> 
>-/* Current offset within tx_FIFO_start, where driver would write new Tx frame*/
>-	tx_curr_put_info_t tx_curr_put_info[MAX_TX_FIFOS];
>-	tx_curr_get_info_t tx_curr_get_info[MAX_TX_FIFOS];
>+/* rx side stuff */
>+	/* Ring specific structure */
>+	ring_info_t rings[MAX_RX_RINGS];
> 
>-	u16 txdl_len;		/* length of a TxDL, same for all */
>+	u16 rmac_pause_time;
>+	u16 mc_pause_threshold_q0q3;
>+	u16 mc_pause_threshold_q4q7;
> 
> 	void *stats_mem;	/* orignal pointer to allocated mem */
> 	dma_addr_t stats_mem_phy;	/* Physical address of the stat block */
>@@ -681,12 +649,6 @@ typedef struct {
> 	int usage_cnt;
> } usr_addr_t;
> 
>-/* Structure that holds the Phy and virt addresses of the Blocks */
>-typedef struct rx_block_info {
>-	RxD_t *block_virt_addr;
>-	dma_addr_t block_dma_addr;
>-} rx_block_info_t;
>-
> /* Default Tunable parameters of the NIC. */
> #define DEFAULT_FIFO_LEN 4096
> #define SMALL_RXD_CNT	30 * (MAX_RXDS_PER_BLOCK+1)
>@@ -695,7 +657,20 @@ typedef struct rx_block_info {
> #define LARGE_BLK_CNT	100
> 
> /* Structure representing one instance of the NIC */
>-typedef struct s2io_nic {
>+struct s2io_nic {
>+#ifdef CONFIG_S2IO_NAPI
>+	/*
>+	 * Count of packets to be processed in a given iteration, it will be indicated
>+	 * by the quota field of the device structure when NAPI is enabled.
>+	 */
>+	int pkts_to_process;
>+#endif
>+	struct net_device *dev;
>+	mac_info_t mac_control;
>+	struct config_param config;
>+	struct pci_dev *pdev;
>+	void __iomem *bar0;
>+	void __iomem *bar1;
> #define MAX_MAC_SUPPORTED   16
> #define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED
> 
>@@ -703,34 +678,20 @@ typedef struct s2io_nic {
> 	macaddr_t pre_mac_addr[MAX_MAC_SUPPORTED];
> 
> 	struct net_device_stats stats;
>-	caddr_t bar0;
>-	caddr_t bar1;
>-	struct config_param config;
>-	mac_info_t mac_control;
> 	int high_dma_flag;
> 	int device_close_flag;
> 	int device_enabled_once;
> 
>-	char name[32];
>+	char name[50];
> 	struct tasklet_struct task;
>-	atomic_t tasklet_status;
>-	struct timer_list timer;
>-	struct net_device *dev;
>-	struct pci_dev *pdev;
>+	volatile unsigned long tasklet_status;
>+
>+	/* Timer that handles I/O errors/exceptions */
>+	struct timer_list alarm_timer;
> 
>-	u16 vendor_id;
>-	u16 device_id;
>-	u16 ccmd;
>-	u32 cbar0_1;
>-	u32 cbar0_2;
>-	u32 cbar1_1;
>-	u32 cbar1_2;
>-	u32 cirq;
>-	u8 cache_line;
>-	u32 rom_expansion;
>-	u16 pcix_cmd;
>+	/* Space to back up the PCI config space */
> 	u32 config_space[256 / sizeof(u32)];
>-	u32 irq;
>+
> 	atomic_t rx_bufs_left[MAX_RX_RINGS];
> 
> 	spinlock_t tx_lock;
>@@ -755,27 +716,11 @@ typedef struct s2io_nic {
> 	u16 tx_err_count;
> 	u16 rx_err_count;
> 
>-#ifndef CONFIG_S2IO_NAPI
>-	/* Index to the absolute position of the put pointer of Rx ring. */
>-	int put_pos;
>-#endif
>-
>-	/*
>-	 *  Place holders for the virtual and physical addresses of 
>-	 *  all the Rx Blocks
>-	 */
>-	rx_block_info_t rx_blocks[MAX_RX_RINGS][MAX_RX_BLOCKS_PER_RING];
>-	int block_count[MAX_RX_RINGS];
>-	int pkt_cnt[MAX_RX_RINGS];
>-
>-	/* Place holder of all the TX List's Phy and Virt addresses. */
>-	list_info_hold_t *list_info[MAX_TX_FIFOS];
>-
> 	/*  Id timer, used to blink NIC to physically identify NIC. */
> 	struct timer_list id_timer;
> 
> 	/*  Restart timer, used to restart NIC if the device is stuck and
>-	 *  a schedule task that will set the correct Link state once the 
>+	 *  a schedule task that will set the correct Link state once the
> 	 *  NIC's PHY has stabilized after a state change.
> 	 */
> #ifdef INIT_TQUEUE
>@@ -786,12 +731,12 @@ typedef struct s2io_nic {
> 	struct work_struct set_link_task;
> #endif
> 
>-	/* Flag that can be used to turn on or turn off the Rx checksum 
>+	/* Flag that can be used to turn on or turn off the Rx checksum
> 	 * offload feature.
> 	 */
> 	int rx_csum;
> 
>-	/*  after blink, the adapter must be restored with original 
>+	/*  after blink, the adapter must be restored with original
> 	 *  values.
> 	 */
> 	u64 adapt_ctrl_org;
>@@ -801,28 +746,26 @@ typedef struct s2io_nic {
> #define	LINK_DOWN	1
> #define	LINK_UP		2
> 
>-#ifdef CONFIG_2BUFF_MODE
>-	/* Buffer Address store. */
>-	buffAdd_t **ba[MAX_RX_RINGS];
>-#endif
> 	int task_flag;
>-#ifdef SNMP_SUPPORT
>-	char cName[20];
>-	int nMemorySize;
>-	int nLinkStatus;
>-	int nFeature;
>-	char cVersion[20];
>-	long lDate;
>-#endif
>+#define CARD_DOWN 1
>+#define CARD_UP 2
>+	atomic_t card_state;
>+	volatile unsigned long link_state;
>+	struct vlan_group *vlgrp;
>+#define XFRAME_I_DEVICE		1
>+#define XFRAME_II_DEVICE	2
>+	u8 device_type;
> 
>-} nic_t;
>+	spinlock_t	rx_lock;
>+	atomic_t	isr_cnt;
>+};
> 
> #define RESET_ERROR 1;
> #define CMD_ERROR   2;
> 
> /*  OS related system calls */
> #ifndef readq
>-static inline u64 readq(void *addr)
>+static inline u64 readq(void __iomem *addr)
> {
> 	u64 ret = 0;
> 	ret = readl(addr + 4);
>@@ -834,28 +777,30 @@ static inline u64 readq(void *addr)
> #endif
> 
> #ifndef writeq
>-static inline void writeq(u64 val, void *addr)
>+static inline void writeq(u64 val, void __iomem *addr)
> {
> 	writel((u32) (val), addr);
> 	writel((u32) (val >> 32), (addr + 4));
> }
> 
>-/* In 32 bit modes, some registers have to be written in a 
>+/* In 32 bit modes, some registers have to be written in a
>  * particular order to expect correct hardware operation. The
>- * macro SPECIAL_REG_WRITE is used to perform such ordered 
>- * writes. Defines UF (Upper First) and LF (Lower First) will 
>+ * macro SPECIAL_REG_WRITE is used to perform such ordered
>+ * writes. Defines UF (Upper First) and LF (Lower First) will
>  * be used to specify the required write order.
>  */
> #define UF	1
> #define LF	2
>-#define SPECIAL_REG_WRITE(val, addr, order) 			\
>-		if (order == LF) {				\
>-			writel((u32) (val), addr);		\
>-			writel((u32) (val >> 32), (addr + 4));	\
>-		} else {					\
>-			writel((u32) (val >> 32), (addr + 4));	\
>-			writel((u32) (val), addr);		\
>-		}
>+static inline void SPECIAL_REG_WRITE(u64 val, void __iomem *addr, int order)
>+{
>+	if (order == LF) {
>+		writel((u32) (val), addr);
>+		writel((u32) (val >> 32), (addr + 4));
>+	} else {
>+		writel((u32) (val >> 32), (addr + 4));
>+		writel((u32) (val), addr);
>+	}
>+}
> #else
> #define SPECIAL_REG_WRITE(val, addr, dummy) writeq(val, addr)
> #endif
>@@ -917,6 +862,7 @@ static inline void writeq(u64 val, void 
> #define	PCC_FB_ECC_ERR	   vBIT(0xff, 16, 8)	/* Interrupt to indicate
> 						   PCC_FB_ECC Error. */
> 
>+#define RXD_GET_VLAN_TAG(Control_2) (u16)(Control_2 & MASK_VLAN_TAG)
> /*
>  * Prototype declaration.
>  */
>@@ -926,10 +872,8 @@ static void __devexit s2io_rem_nic(struc
> static int init_shared_mem(struct s2io_nic *sp);
> static void free_shared_mem(struct s2io_nic *sp);
> static int init_nic(struct s2io_nic *nic);
>-#ifndef CONFIG_S2IO_NAPI
>-static void rx_intr_handler(struct s2io_nic *sp);
>-#endif
>-static void tx_intr_handler(struct s2io_nic *sp);
>+static void rx_intr_handler(ring_info_t *ring_data);
>+static void tx_intr_handler(fifo_info_t *fifo_data);
> static void alarm_intr_handler(struct s2io_nic *sp);
> 
> static int s2io_starter(void);
>@@ -937,85 +881,21 @@ void s2io_closer(void);
> static void s2io_tx_watchdog(struct net_device *dev);
> static void s2io_tasklet(unsigned long dev_addr);
> static void s2io_set_multicast(struct net_device *dev);
>-#ifndef CONFIG_2BUFF_MODE
>-static int rx_osm_handler(nic_t * sp, u16 len, RxD_t * rxdp, int ring_no);
>-#else
>-static int rx_osm_handler(nic_t * sp, RxD_t * rxdp, int ring_no,
>-			  buffAdd_t * ba);
>-#endif
>+static int rx_osm_handler(ring_info_t *ring_data, RxD_t * rxdp);
> void s2io_link(nic_t * sp, int link);
> void s2io_reset(nic_t * sp);
>-#ifdef CONFIG_S2IO_NAPI
>+#if defined(CONFIG_S2IO_NAPI)
> static int s2io_poll(struct net_device *dev, int *budget);
> #endif
> static void s2io_init_pci(nic_t * sp);
> int s2io_set_mac_addr(struct net_device *dev, u8 * addr);
>+static void s2io_alarm_handle(unsigned long data);
> static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs);
>-static int verify_xena_quiescence(u64 val64, int flag);
>-int verify_load_parm(void);
>-#ifdef SET_ETHTOOL_OPS
>+static int verify_xena_quiescence(nic_t *sp, u64 val64, int flag);
> static struct ethtool_ops netdev_ethtool_ops;
>-#endif
> static void s2io_set_link(unsigned long data);
>-
>-#ifdef SNMP_SUPPORT
>-
>-#define S2IODIRNAME             "S2IO"
>-#define BDFILENAME      "BDInfo"
>-#define PADAPFILENAME   "PhyAdap"
>-#define ERROR_PROC_DIR          -20
>-#define ERROR_PROC_ENTRY        -21
>-
>-struct stDrvData {
>-	struct stBaseDrv *pBaseDrv;
>-};
>-
>-struct stPhyAdap {
>-	int m_nIndex;
>-	char m_cName[20];
>-};
>-struct stBaseDrv {
>-	char m_cName[21];
>-	int m_nStatus;
>-	char m_cVersion[21];
>-	int m_nFeature;
>-	int m_nMemorySize;
>-	char m_cDate[21];
>-	int m_nPhyCnt;
>-	char m_cPhyIndex[21];
>-	struct stPhyAdap m_stPhyAdap[5];
>-};
>-
>-struct stPhyData {
>-	int m_nIndex;
>-	unsigned char m_cDesc[20];
>-	int m_nMode;
>-	int m_nType;
>-	char m_cSpeed[20];
>-	unsigned char m_cPMAC[20];
>-	unsigned char m_cCMAC[20];
>-	int m_nLinkStatus;
>-	int m_nPCISlot;
>-	int m_nPCIBus;
>-	int m_nIRQ;
>-	int m_nCollision;
>-	int m_nMulticast;
>-
>-	int m_nRxBytes;
>-	int m_nRxDropped;
>-	int m_nRxErrors;
>-	int m_nRxPackets;
>-	int m_nTxBytes;
>-	int m_nTxDropped;
>-	int m_nTxErrors;
>-	int m_nTxPackets;
>-
>-
>-};
>-
>-static int s2io_bdsnmp_init(struct net_device *dev);
>-static void s2io_bdsnmp_rem(struct net_device *dev);
>-#endif
>-
>-
>+int s2io_set_swapper(nic_t * sp);
>+static void s2io_card_down(nic_t *nic);
>+static int s2io_card_up(nic_t *nic);
>+int get_xena_rev_id(struct pci_dev *pdev);
> #endif				/* _S2IO_H */
>diff -urpN old/include/linux/pci_ids.h new/include/linux/pci_ids.h
>--- old/include/linux/pci_ids.h	2005-09-08 15:47:19.585927368 -0700
>+++ new/include/linux/pci_ids.h	2005-09-08 15:59:06.492461240 -0700
>@@ -1912,6 +1912,8 @@
> #define PCI_VENDOR_ID_S2IO		0x17d5
> #define	PCI_DEVICE_ID_S2IO_WIN		0x5731
> #define	PCI_DEVICE_ID_S2IO_UNI		0x5831
>+#define PCI_DEVICE_ID_HERC_WIN		0x5732
>+#define PCI_DEVICE_ID_HERC_UNI		0x5832
> 
> #define PCI_VENDOR_ID_ARC               0x192E
> #define PCI_DEVICE_ID_ARC_EHCI          0x0101

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Attachments on bug 116305: 49501 | 49502