Attachment #50076 for bug #113203

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Lines 82-87 Link Here

(-)nv_driver.c (-6 / +18 lines)
82	0	82	0
83	};	83	};
84		84
		85	/* Known cards as of 2005/08/31 */
		86
85	static SymTabRec NVKnownChipsets[] =	87	static SymTabRec NVKnownChipsets[] =
86	{	88	{
87	{ 0x12D20018, "RIVA 128" },	89	{ 0x12D20018, "RIVA 128" },
Lines 200-206 Link Here
200	#else	202	#else
201	{ 0x10DE0329, "0x0329" },	203	{ 0x10DE0329, "0x0329" },
202	#endif	204	#endif
203	{ 0x10DE032A, "Quadro NVS 280 PCI" },	205	{ 0x10DE032A, "Quadro NVS 55/280 PCI" },
204	{ 0x10DE032B, "Quadro FX 500/600 PCI" },	206	{ 0x10DE032B, "Quadro FX 500/600 PCI" },
205	{ 0x10DE032C, "GeForce FX Go53xx Series" },	207	{ 0x10DE032C, "GeForce FX Go53xx Series" },
206	{ 0x10DE032D, "GeForce FX Go5100" },	208	{ 0x10DE032D, "GeForce FX Go5100" },
Lines 233-244 Link Here
233	{ 0x10DE0043, "0x0043" },	235	{ 0x10DE0043, "0x0043" },
234	{ 0x10DE0045, "GeForce 6800 GT" },	236	{ 0x10DE0045, "GeForce 6800 GT" },
235	{ 0x10DE0046, "GeForce 6800 GT" },	237	{ 0x10DE0046, "GeForce 6800 GT" },
		238	{ 0x10DE0048, "GeForce 6800 XT" },
236	{ 0x10DE0049, "0x0049" },	239	{ 0x10DE0049, "0x0049" },
237	{ 0x10DE004E, "Quadro FX 4000" },	240	{ 0x10DE004E, "Quadro FX 4000" },
238		241
239	{ 0x10DE00C0, "0x00C0" },	242	{ 0x10DE00C0, "0x00C0" },
240	{ 0x10DE00C1, "GeForce 6800" },	243	{ 0x10DE00C1, "GeForce 6800" },
241	{ 0x10DE00C2, "GeForce 6800 LE" },	244	{ 0x10DE00C2, "GeForce 6800 LE" },
		245	{ 0x10DE00C3, "GeForce 6800 XT" },
242	{ 0x10DE00C8, "GeForce Go 6800" },	246	{ 0x10DE00C8, "GeForce Go 6800" },
243	{ 0x10DE00C9, "GeForce Go 6800 Ultra" },	247	{ 0x10DE00C9, "GeForce Go 6800 Ultra" },
244	{ 0x10DE00CC, "Quadro FX Go1400" },	248	{ 0x10DE00CC, "Quadro FX Go1400" },
Lines 261-276 Link Here
261	{ 0x10DE014E, "Quadro FX 540" },	265	{ 0x10DE014E, "Quadro FX 540" },
262	{ 0x10DE014F, "GeForce 6200" },	266	{ 0x10DE014F, "GeForce 6200" },
263		267
264	{ 0x10DE0160, "0x0160" },	268	{ 0x10DE0160, "GeForce 6500" },
265	{ 0x10DE0161, "GeForce 6200 TurboCache(TM)" },	269	{ 0x10DE0161, "GeForce 6200 TurboCache(TM)" },
266	{ 0x10DE0162, "GeForce 6200SE TurboCache(TM)" },	270	{ 0x10DE0162, "GeForce 6200SE TurboCache(TM)" },
267	{ 0x10DE0163, "0x0163" },	271	{ 0x10DE0163, "GeForce 6200 LE" },
268	{ 0x10DE0164, "GeForce Go 6200" },	272	{ 0x10DE0164, "GeForce Go 6200" },
269	{ 0x10DE0165, "Quadro NVS 285" },	273	{ 0x10DE0165, "Quadro NVS 285" },
270	{ 0x10DE0166, "GeForce Go 6400" },	274	{ 0x10DE0166, "GeForce Go 6400" },
271	{ 0x10DE0167, "GeForce Go 6200" },	275	{ 0x10DE0167, "GeForce Go 6200" },
272	{ 0x10DE0168, "GeForce Go 6400" },	276	{ 0x10DE0168, "GeForce Go 6400" },
273	{ 0x10DE0169, "0x0169" },	277	{ 0x10DE0169, "GeForce 6250" },
274	{ 0x10DE016B, "0x016B" },	278	{ 0x10DE016B, "0x016B" },
275	{ 0x10DE016C, "0x016C" },	279	{ 0x10DE016C, "0x016C" },
276	{ 0x10DE016D, "0x016D" },	280	{ 0x10DE016D, "0x016D" },
Lines 288-294 Link Here
288		292
289	{ 0x10DE0090, "0x0090" },	293	{ 0x10DE0090, "0x0090" },
290	{ 0x10DE0091, "GeForce 7800 GTX" },	294	{ 0x10DE0091, "GeForce 7800 GTX" },
291	{ 0x10DE0092, "0x0092" },	295	{ 0x10DE0092, "GeForce 7800 GT" },
292	{ 0x10DE0093, "0x0093" },	296	{ 0x10DE0093, "0x0093" },
293	{ 0x10DE0094, "0x0094" },	297	{ 0x10DE0094, "0x0094" },
294	{ 0x10DE0098, "0x0098" },	298	{ 0x10DE0098, "0x0098" },
Lines 694-699 Link Here
694	case 0x0210:	698	case 0x0210:
695	case 0x0220:	699	case 0x0220:
696	case 0x0230:	700	case 0x0230:
		701	case 0x0290:
		702	case 0x0390:
697	NVChipsets[numUsed].token = pciid;	703	NVChipsets[numUsed].token = pciid;
698	NVChipsets[numUsed].name = "Unknown NVIDIA chip";	704	NVChipsets[numUsed].name = "Unknown NVIDIA chip";
699	NVPciChipsets[numUsed].numChipset = pciid;	705	NVPciChipsets[numUsed].numChipset = pciid;
Lines 1384-1389 Link Here
1384	case 0x0210:	1390	case 0x0210:
1385	case 0x0220:	1391	case 0x0220:
1386	case 0x0230:	1392	case 0x0230:
		1393	case 0x0290:
		1394	case 0x0390:
1387	pNv->Architecture = NV_ARCH_40;	1395	pNv->Architecture = NV_ARCH_40;
1388	break;	1396	break;
1389	default:	1397	default:
Lines 1420-1428 Link Here
1420	}	1428	}
1421	}	1429	}
1422		1430
1423	pNv->FbUsableSize = pNv->FbMapSize - (128 * 1024);	1431	if(pNv->Architecture >= NV_ARCH_40)
		1432	pNv->FbUsableSize = pNv->FbMapSize - (560 * 1024);
		1433	else
		1434	pNv->FbUsableSize = pNv->FbMapSize - (128 * 1024);
1424	pNv->ScratchBufferSize = (pNv->Architecture < NV_ARCH_10) ? 8192 : 16384;	1435	pNv->ScratchBufferSize = (pNv->Architecture < NV_ARCH_10) ? 8192 : 16384;
1425	pNv->ScratchBufferStart = pNv->FbUsableSize - pNv->ScratchBufferSize;	1436	pNv->ScratchBufferStart = pNv->FbUsableSize - pNv->ScratchBufferSize;
		1437	pNv->CursorStart = pNv->FbUsableSize + (32 * 1024);
1426		1438
1427	/*	1439	/*
1428	* Setup the ClockRanges, which describe what clock ranges are available,	1440	* Setup the ClockRanges, which describe what clock ranges are available,





    if(pNv->Architecture == NV_ARCH_04) {
        pNv->PFB[0x0200/4] = state->config;
    } else 
    if((pNv->Architecture < NV_ARCH_40) ||
       ((pNv->Chipset & 0xfff0) == 0x0040))
    {
        }
    } else {
        for(i = 0; i < 8; i++) {
           pNv->PFB[(0x0240 + (i * 0x10))/4] = 0;
           pNv->PFB[(0x0244 + (i * 0x10))/4] = pNv->FbMapSize - 1;
        }
    } else {
        int regions = 12;

        if(((pNv->Chipset & 0xfff0) == 0x0090) ||
           ((pNv->Chipset & 0xfff0) == 0x01D0) ||
           ((pNv->Chipset & 0xfff0) == 0x0290))
        {
           regions = 15;
        }
 
       for(i = 0; i < regions; i++) {
          pNv->PFB[(0x0600 + (i * 0x10))/4] = 0;
          pNv->PFB[(0x0604 + (i * 0x10))/4] = pNv->FbMapSize - 1;
       }
    }

    if(pNv->Architecture >= NV_ARCH_40) {

                 pNv->PFB[0x033C/4] &= 0xffff7fff;
                 break;
              case 0x00C0:
              case 0x0120:
                 pNv->PGRAPH[0x0828/4] = 0x007596ff;
                 pNv->PGRAPH[0x082C/4] = 0x00000108;
                 break;

                 pNv->PRAMDAC[0x0608/4] |= 0x00100000;
                 break;
              case 0x0090:
              case 0x0290:
                 pNv->PRAMDAC[0x0608/4] |= 0x00100000;
                 pNv->PGRAPH[0x0828/4] = 0x07830610;
                 pNv->PGRAPH[0x082C/4] = 0x0000016A;

              }
           }

           if((pNv->Architecture < NV_ARCH_40) ||
              ((pNv->Chipset & 0xfff0) == 0x0040)) 
           {
           } else {
              for(i = 0; i < 32; i++)
                pNv->PGRAPH[(0x0900/4) + i] = pNv->PFB[(0x0240/4) + i];
           } else {
              if(((pNv->Chipset & 0xfff0) == 0x0090) ||
                 ((pNv->Chipset & 0xfff0) == 0x01D0) ||
                 ((pNv->Chipset & 0xfff0) == 0x0290))
              {
                 for(i = 0; i < 60; i++)
                   pNv->PGRAPH[(0x0D00/4) + i] = pNv->PFB[(0x0600/4) + i];
              } else {
                 for(i = 0; i < 48; i++)
                   pNv->PGRAPH[(0x0900/4) + i] = pNv->PFB[(0x0600/4) + i];
              }
           }

           if(pNv->Architecture >= NV_ARCH_40) {

                 pNv->PGRAPH[0x0864/4] = pNv->FbMapSize - 1;
                 pNv->PGRAPH[0x0868/4] = pNv->FbMapSize - 1;
              } else {
                 if(((pNv->Chipset & 0xfff0) == 0x0090) ||
                    ((pNv->Chipset & 0xfff0) == 0x01D0) ||
                    ((pNv->Chipset & 0xfff0) == 0x0290)) 
                 {
                    pNv->PGRAPH[0x0DF0/4] = pNv->PFB[0x0200/4];
                    pNv->PGRAPH[0x0DF4/4] = pNv->PFB[0x0204/4];
                 } else {

Lines 313-319 Link Here

(-)nv_setup.c (-1 lines)
313	pNv->CrystalFreqKHz = 27000;	313	pNv->CrystalFreqKHz = 27000;
314	}	314	}
315		315
316	pNv->CursorStart = (pNv->RamAmountKBytes - 96) * 1024;
317	pNv->CURSOR = NULL; /* can't set this here */	316	pNv->CURSOR = NULL; /* can't set this here */
318	pNv->MinVClockFreqKHz = 12000;	317	pNv->MinVClockFreqKHz = 12000;
319	pNv->MaxVClockFreqKHz = pNv->twoStagePLL ? 400000 : 350000;	318	pNv->MaxVClockFreqKHz = pNv->twoStagePLL ? 400000 : 350000;

Return to bug 113203

Lines 928-943 Link Here

(-)nv_hw.c (-11 / +38 lines)
928		928
929	if(pNv->Architecture == NV_ARCH_04) {	929	if(pNv->Architecture == NV_ARCH_04) {
930	pNv->PFB[0x0200/4] = state->config;	930	pNv->PFB[0x0200/4] = state->config;
931	} else if ((pNv->Chipset & 0xfff0) == 0x0090) {	931	} else
932	for(i = 0; i < 15; i++) {	932	if((pNv->Architecture < NV_ARCH_40) \|\|
933	pNv->PFB[(0x0600 + (i * 0x10))/4] = 0;	933	((pNv->Chipset & 0xfff0) == 0x0040))
934	pNv->PFB[(0x0604 + (i * 0x10))/4] = pNv->FbMapSize - 1;	934	{
935	}
936	} else {
937	for(i = 0; i < 8; i++) {	935	for(i = 0; i < 8; i++) {
938	pNv->PFB[(0x0240 + (i * 0x10))/4] = 0;	936	pNv->PFB[(0x0240 + (i * 0x10))/4] = 0;
939	pNv->PFB[(0x0244 + (i * 0x10))/4] = pNv->FbMapSize - 1;	937	pNv->PFB[(0x0244 + (i * 0x10))/4] = pNv->FbMapSize - 1;
940	}	938	}
		939	} else {
		940	int regions = 12;
		941
		942	if(((pNv->Chipset & 0xfff0) == 0x0090) \|\|
		943	((pNv->Chipset & 0xfff0) == 0x01D0) \|\|
		944	((pNv->Chipset & 0xfff0) == 0x0290))
		945	{
		946	regions = 15;
		947	}
		948
		949	for(i = 0; i < regions; i++) {
		950	pNv->PFB[(0x0600 + (i * 0x10))/4] = 0;
		951	pNv->PFB[(0x0604 + (i * 0x10))/4] = pNv->FbMapSize - 1;
		952	}
941	}	953	}
942		954
943	if(pNv->Architecture >= NV_ARCH_40) {	955	if(pNv->Architecture >= NV_ARCH_40) {
Lines 1172-1177 Link Here
1172	pNv->PFB[0x033C/4] &= 0xffff7fff;	1184	pNv->PFB[0x033C/4] &= 0xffff7fff;
1173	break;	1185	break;
1174	case 0x00C0:	1186	case 0x00C0:
		1187	case 0x0120:
1175	pNv->PGRAPH[0x0828/4] = 0x007596ff;	1188	pNv->PGRAPH[0x0828/4] = 0x007596ff;
1176	pNv->PGRAPH[0x082C/4] = 0x00000108;	1189	pNv->PGRAPH[0x082C/4] = 0x00000108;
1177	break;	1190	break;
Lines 1196-1201 Link Here
1196	pNv->PRAMDAC[0x0608/4] \|= 0x00100000;	1209	pNv->PRAMDAC[0x0608/4] \|= 0x00100000;
1197	break;	1210	break;
1198	case 0x0090:	1211	case 0x0090:
		1212	case 0x0290:
1199	pNv->PRAMDAC[0x0608/4] \|= 0x00100000;	1213	pNv->PRAMDAC[0x0608/4] \|= 0x00100000;
1200	pNv->PGRAPH[0x0828/4] = 0x07830610;	1214	pNv->PGRAPH[0x0828/4] = 0x07830610;
1201	pNv->PGRAPH[0x082C/4] = 0x0000016A;	1215	pNv->PGRAPH[0x082C/4] = 0x0000016A;
Lines 1243-1254 Link Here
1243	}	1257	}
1244	}	1258	}
1245		1259
1246	if((pNv->Chipset & 0xfff0) == 0x0090) {	1260	if((pNv->Architecture < NV_ARCH_40) \|\|
1247	for(i = 0; i < 60; i++)	1261	((pNv->Chipset & 0xfff0) == 0x0040))
1248	pNv->PGRAPH[(0x0D00/4) + i] = pNv->PFB[(0x0600/4) + i];	1262	{
1249	} else {
1250	for(i = 0; i < 32; i++)	1263	for(i = 0; i < 32; i++)
1251	pNv->PGRAPH[(0x0900/4) + i] = pNv->PFB[(0x0240/4) + i];	1264	pNv->PGRAPH[(0x0900/4) + i] = pNv->PFB[(0x0240/4) + i];
		1265	} else {
		1266	if(((pNv->Chipset & 0xfff0) == 0x0090) \|\|
		1267	((pNv->Chipset & 0xfff0) == 0x01D0) \|\|
		1268	((pNv->Chipset & 0xfff0) == 0x0290))
		1269	{
		1270	for(i = 0; i < 60; i++)
		1271	pNv->PGRAPH[(0x0D00/4) + i] = pNv->PFB[(0x0600/4) + i];
		1272	} else {
		1273	for(i = 0; i < 48; i++)
		1274	pNv->PGRAPH[(0x0900/4) + i] = pNv->PFB[(0x0600/4) + i];
		1275	}
1252	}	1276	}
1253		1277
1254	if(pNv->Architecture >= NV_ARCH_40) {	1278	if(pNv->Architecture >= NV_ARCH_40) {
Lines 1263-1269 Link Here
1263	pNv->PGRAPH[0x0864/4] = pNv->FbMapSize - 1;	1287	pNv->PGRAPH[0x0864/4] = pNv->FbMapSize - 1;
1264	pNv->PGRAPH[0x0868/4] = pNv->FbMapSize - 1;	1288	pNv->PGRAPH[0x0868/4] = pNv->FbMapSize - 1;
1265	} else {	1289	} else {
1266	if((pNv->Chipset & 0xfff0) == 0x0090) {	1290	if(((pNv->Chipset & 0xfff0) == 0x0090) \|\|
		1291	((pNv->Chipset & 0xfff0) == 0x01D0) \|\|
		1292	((pNv->Chipset & 0xfff0) == 0x0290))
		1293	{
1267	pNv->PGRAPH[0x0DF0/4] = pNv->PFB[0x0200/4];	1294	pNv->PGRAPH[0x0DF0/4] = pNv->PFB[0x0200/4];
1268	pNv->PGRAPH[0x0DF4/4] = pNv->PFB[0x0204/4];	1295	pNv->PGRAPH[0x0DF4/4] = pNv->PFB[0x0204/4];
1269	} else {	1296	} else {