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Lines 10-15
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*/ |
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*/ |
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#define DEBUG 0 |
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#define DEBUG 0 |
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#include <linux/config.h> |
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#include <linux/config.h> |
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#include <linux/version.h> |
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#include <linux/version.h> |
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#include <linux/module.h> |
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#include <linux/module.h> |
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Lines 22-28
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#include <asm/io.h> |
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#include <asm/io.h> |
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#include <linux/proc_fs.h> |
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#include <linux/proc_fs.h> |
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#define ECC_VER "0.14 (Oct 10 2001)" |
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#define ECC_VER "0.15 (Dec 1 2005)" |
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#define KERN_ECC KERN_ALERT |
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#define KERN_ECC KERN_ALERT |
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static struct timer_list ecctimer; |
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static struct timer_list ecctimer; |
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Lines 1102-1116
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} |
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} |
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} |
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} |
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// Spec source: AMD 761 System Controller/BIOS Guide, 24081D-February 2002 |
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// http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24081.pdf |
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void check_amd76x(void) |
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void check_amd76x(void) |
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{ |
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{ |
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unsigned long eccstat = pci_dword(0x48); |
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u32 eccstat; |
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pci_read_config_dword(bridge, 0x48, &eccstat); |
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if(eccstat & 0x30) |
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{ |
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if(eccstat & 0x10) |
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if(eccstat & 0x10) |
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{ |
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{ |
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/* bits 7-4 of eccstat indicate the row the MBE occurred. */ |
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/* bits 7-4 of eccstat indicate the row the MBE occurred. */ |
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int row = (eccstat >> 4) & 0xf; |
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int row = (eccstat >> 4) & 0xf; |
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printk("<1>ECC: MBE Detected in DRAM row %d\n", row); |
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printk("<1>ECC: MBE Detected in DRAM row %d\n", row); |
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scrub_needed |= 2; |
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bank[row].mbecount++; |
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bank[row].mbecount++; |
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} |
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} |
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if(eccstat & 0x20) |
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if(eccstat & 0x20) |
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Lines 1118-1139
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/* bits 3-0 of eccstat indicate the row the SBE occurred. */ |
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/* bits 3-0 of eccstat indicate the row the SBE occurred. */ |
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int row = eccstat & 0xf; |
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int row = eccstat & 0xf; |
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printk("<1>ECC: SBE Detected in DRAM row %d\n", row); |
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printk("<1>ECC: SBE Detected in DRAM row %d\n", row); |
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scrub_needed |= 1; |
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bank[row].sbecount++; |
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bank[row].sbecount++; |
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} |
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} |
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if (scrub_needed) |
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pci_write_config_dword(bridge, 0x48, eccstat); // clear by writing a 1 |
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{ |
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/* |
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* clear error flag bits that were set by writing 0 to them |
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* we hope the error was a fluke or something :) |
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*/ |
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unsigned long value = eccstat; |
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if (scrub_needed & 1) |
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value &= 0xFFFFFDFF; |
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if (scrub_needed & 2) |
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value &= 0xFFFFFEFF; |
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pci_write_config_dword(bridge, 0x48, value); |
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scrub_needed = 0; |
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} |
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} |
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} |
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} |
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