Attachment #61888 for bug #127757

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Lines 50-55 Link Here

(-)xc.orig/programs/Xserver/hw/xfree86/drivers/ati/radeon_cursor.c (+1 lines)
50		50
51	/* Driver data structures */	51	/* Driver data structures */
52	#include "radeon.h"	52	#include "radeon.h"
		53	#include "radeon_version.h"
53	#include "radeon_reg.h"	54	#include "radeon_reg.h"
54	#include "radeon_macros.h"	55	#include "radeon_macros.h"
55	#include "radeon_mergedfb.h"	56	#include "radeon_mergedfb.h"

Lines 1456-1465 Link Here

(-)xc.orig/programs/Xserver/hw/xfree86/drivers/ati/radeon_dri.c (-4 lines)
1456	version->version_patchlevel);	1456	version->version_patchlevel);
1457	info->allowColorTiling = FALSE;	1457	info->allowColorTiling = FALSE;
1458	info->tilingEnabled = FALSE;	1458	info->tilingEnabled = FALSE;
1459	/* try to fix up already set mode, crt pitch, ddx major (hope that's ok to do here) */
1460	/* is this correct scrnIndex? flags? */
1461	RADEONSwitchMode(pScrn->scrnIndex, pScrn->currentMode, 0);
1462	pScrn->AdjustFrame(pScrn->scrnIndex, pScrn->frameX0, pScrn->frameY0, 0);
1463	pDRIInfo->ddxDriverMajorVersion = RADEON_VERSION_MAJOR;	1459	pDRIInfo->ddxDriverMajorVersion = RADEON_VERSION_MAJOR;
1464	}	1460	}
1465	drmFreeVersion(version);	1461	drmFreeVersion(version);

Lines 129-134 Link Here

(-)xc.orig/programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c (-120 / +274 lines)
129	static int RADEONValidateMergeModes(ScrnInfoPtr pScrn);	129	static int RADEONValidateMergeModes(ScrnInfoPtr pScrn);
130	static void RADEONSetDynamicClock(ScrnInfoPtr pScrn, int mode);	130	static void RADEONSetDynamicClock(ScrnInfoPtr pScrn, int mode);
131	static void RADEONUpdatePanelSize(ScrnInfoPtr pScrn);	131	static void RADEONUpdatePanelSize(ScrnInfoPtr pScrn);
		132	static void RADEONSaveMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
132		133
133	/* psuedo xinerama support */	134	/* psuedo xinerama support */
134		135
Lines 547-552 Link Here
547	static Bool RADEONMapMMIO(ScrnInfoPtr pScrn);	548	static Bool RADEONMapMMIO(ScrnInfoPtr pScrn);
548	static Bool RADEONUnmapMMIO(ScrnInfoPtr pScrn);	549	static Bool RADEONUnmapMMIO(ScrnInfoPtr pScrn);
549		550
		551	static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
		552
550	RADEONEntPtr RADEONEntPriv(ScrnInfoPtr pScrn)	553	RADEONEntPtr RADEONEntPriv(ScrnInfoPtr pScrn)
551	{	554	{
552	DevUnion *pPriv;	555	DevUnion *pPriv;
Lines 2252-2334 Link Here
2252	return TRUE;	2255	return TRUE;
2253	}	2256	}
2254		2257
2255	/* Set up MC_FB_LOCATION and related registers */	2258	static void RADEONInitMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save,
2256	static void	2259	RADEONInfoPtr info)
2257	RADEONSetFBLocation(ScrnInfoPtr pScrn)
2258	{	2260	{
2259	RADEONInfoPtr info = RADEONPTR(pScrn);	2261	save->mc_fb_location = info->mc_fb_location;
2260	RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);	2262	save->mc_agp_location = info->mc_agp_location;
		2263	save->display_base_addr = info->fbLocation;
		2264	save->display2_base_addr = info->fbLocation;
		2265	save->ov0_base_addr = info->fbLocation;
		2266	}
		2267
		2268	static void RADEONInitMemoryMap(ScrnInfoPtr pScrn)
		2269	{
		2270	RADEONInfoPtr info = RADEONPTR(pScrn);
2261	unsigned char *RADEONMMIO = info->MMIO;	2271	unsigned char *RADEONMMIO = info->MMIO;
2262	CARD32 mc_fb_location;	2272	unsigned long agp_size, agp_base, mem_size;
2263	CARD32 mc_agp_location = INREG(RADEON_MC_AGP_LOCATION);
2264	CARD32 bus_cntl = INREG(RADEON_BUS_CNTL);
2265
2266	OUTREG (RADEON_BUS_CNTL, bus_cntl \| RADEON_BUS_MASTER_DIS);
2267	RADEONWaitForIdleMMIO(pScrn);
2268		2273
2269	/* This function has many problems with newer cards.	2274	/* Default to existing values */
2270	* Even with older cards, all registers changed here are not	2275	info->mc_fb_location = INREG(RADEON_MC_FB_LOCATION);
2271	* restored properly when X quits, this will also cause	2276	info->mc_agp_location = INREG(RADEON_MC_AGP_LOCATION);
2272	* various problems, especially with radeonfb.
2273	* Since we don't have DRI support for R300 and above cards,
2274	* we just hardcode these values for now.
2275	* Need to revisit this whole function!!!
2276	*/
2277		2277
2278	if (info->IsIGP) {	2278	/* We shouldn't use info->videoRam here which might have been clipped
2279	mc_fb_location = INREG(RADEON_NB_TOM);	2279	* but the real video RAM instead
		2280	*/
		2281	mem_size = INREG(RADEON_CONFIG_MEMSIZE);
		2282	if (mem_size == 0)
		2283	mem_size = 0x800000;
2280		2284
2281	OUTREG(RADEON_GRPH2_BUFFER_CNTL,
2282	INREG(RADEON_GRPH2_BUFFER_CNTL) & ~0x7f0000);
2283		2285
2284	} else	2286	/* We won't try to change MC_FB_LOCATION when using fbdev */
		2287	if (!info->FBDev) {
		2288	if (info->IsIGP)
		2289	info->mc_fb_location = INREG(RADEON_NB_TOM);
		2290	else
2285	#ifdef XF86DRI	2291	#ifdef XF86DRI
2286	if ( info->directRenderingEnabled && info->drmMinor < 10 ) {	2292	/* Old DRI has restrictions on the memory map */
2287	mc_fb_location = (INREG(RADEON_CONFIG_APER_SIZE) - 1) & 0xffff0000U;	2293	if ( info->directRenderingEnabled && info->drmMinor < 10 )
2288	} else	2294	info->mc_fb_location = (mem_size - 1) & 0xffff0000U;
		2295	else
2289	#endif	2296	#endif
2290	{	2297	{
2291	CARD32 aper0_base = INREG(RADEON_CONFIG_APER_0_BASE);	2298	CARD32 aper0_base = INREG(RADEON_CONFIG_APER_0_BASE);
2292		2299
2293	mc_fb_location = (aper0_base >> 16)	2300	info->mc_fb_location = (aper0_base >> 16) \|
2294	\| ((aper0_base + (INREG(RADEON_CONFIG_APER_SIZE) - 1)	2301	((aper0_base + mem_size - 1) & 0xffff0000U);
2295	) & 0xffff0000U);	2302	}
2296	}
2297
2298	info->fbLocation = (mc_fb_location & 0xffff) << 16;
2299
2300	if (((mc_agp_location & 0xffff) << 16) !=
2301	((mc_fb_location & 0xffff0000U) + 0x10000)) {
2302	mc_agp_location = mc_fb_location & 0xffff0000U;
2303	mc_agp_location \|= (mc_agp_location + 0x10000) >> 16;
2304	}
2305
2306	RADEONWaitForIdleMMIO(pScrn);
2307
2308	OUTREG(RADEON_MC_FB_LOCATION, mc_fb_location);
2309	OUTREG(RADEON_MC_AGP_LOCATION, mc_agp_location);
2310	OUTREG(RADEON_DISPLAY_BASE_ADDR, info->fbLocation);
2311	if (info->HasCRTC2)
2312	OUTREG(RADEON_DISPLAY2_BASE_ADDR, info->fbLocation);
2313	OUTREG(RADEON_OV0_BASE_ADDR, info->fbLocation);
2314
2315	OUTREG (RADEON_BUS_CNTL, bus_cntl);
2316	RADEONWaitForIdleMMIO(pScrn);
2317
2318	/* Set display0/1 priority up on r3/4xx in the memory controller for
2319	* high res modes if the user specifies HIGH for displaypriority
2320	* option.
2321	*/
2322	if ((info->DispPriority == 2) && IS_R300_VARIANT) {
2323	CARD32 mc_init_misc_lat_timer = INREG(R300_MC_INIT_MISC_LAT_TIMER);
2324	if (info->MergedFB \|\| pRADEONEnt->HasSecondary) {
2325	mc_init_misc_lat_timer \|= 0x1100; /* display 0 and 1 */
2326	} else {
2327	mc_init_misc_lat_timer \|= 0x0100; /* display 0 only */
2328	}
2329	OUTREG(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2330	}	2303	}
		2304	info->fbLocation = (info->mc_fb_location & 0xffff) << 16;
2331		2305
		2306	/* Calculate AGP aperture location */
		2307	agp_size = ((info->mc_agp_location >> 16) -
		2308	(info->mc_agp_location & 0xffff) + 1) << 16;
		2309	agp_base = info->fbLocation + mem_size;
		2310
		2311	/* If there is no room up there for at least 16Mb, put AGP down to
		2312	* 0x80000000. This is an arbitrary value that should be good enough.
		2313	* In the future, we might want to use the real gartSize that will be
		2314	* requested, but at least that will give us some breathing space with
		2315	* the default value
		2316	*/
		2317	if ((agp_base + 0x01000000) < info->fbLocation)
		2318	agp_base = 0x80000000u;
		2319
		2320	/* Make sure AGP size is at least 4Mb for the sake of the memory mapping
		2321	* (even if we don't actually use it, to avoid leaving a dangling map
		2322	* or invalid setting in MC_AGP_LOCATION
		2323	*/
		2324	if (agp_size < 0x400000)
		2325	agp_size = 0x400000;
		2326
		2327	/* We may need to crop the AGP size. Hopefully, it will be changed later
		2328	* on by the DRI init again, but for now, it's the firmware setting which
		2329	* might overflow.
		2330	*/
		2331	while (agp_base > ((agp_base + agp_size) & 0xfffffffful))
		2332	agp_size >>= 1;
		2333
		2334	/* Ok, now set our various bits & pieces */
		2335	info->mc_agp_location = (agp_base >> 16) \|
		2336	((agp_base + agp_size - 1) & 0xffff0000U);
		2337
		2338	RADEONTRACE(("RADEONInitMemoryMap() : \n"));
		2339	RADEONTRACE((" mem_size : 0x%08lx\n", mem_size));
		2340	RADEONTRACE((" agp_size : 0x%08lx\n", agp_size));
		2341	RADEONTRACE((" agp_base : 0x%08lx\n", agp_base));
		2342	RADEONTRACE((" MC_FB_LOCATION : 0x%08lx\n", info->mc_fb_location));
		2343	RADEONTRACE((" MC_AGP_LOCATION : 0x%08lx\n", info->mc_agp_location));
2332	}	2344	}
2333		2345
2334	static void RADEONGetVRamType(ScrnInfoPtr pScrn)	2346	static void RADEONGetVRamType(ScrnInfoPtr pScrn)
Lines 2710-2716 Link Here
2710	* 128M is configured as invisible FB to CPU that can only be accessed from chip side.	2722	* 128M is configured as invisible FB to CPU that can only be accessed from chip side.
2711	*/	2723	*/
2712	pScrn->videoRam = INREG(RADEON_CONFIG_MEMSIZE) / 1024;	2724	pScrn->videoRam = INREG(RADEON_CONFIG_MEMSIZE) / 1024;
2713	if (pScrn->videoRam > 1281024) pScrn->videoRam = 1281024;	2725	if (pScrn->videoRam > 128*1024)
		2726	pScrn->videoRam = 128*1024;
		2727	/* XXX FIX CRAP BELOW ! IT'S WRONG */
2714	if ((info->ChipFamily == CHIP_FAMILY_RV350) \|\|	2728	if ((info->ChipFamily == CHIP_FAMILY_RV350) \|\|
2715	(info->ChipFamily == CHIP_FAMILY_RV380) \|\|	2729	(info->ChipFamily == CHIP_FAMILY_RV380) \|\|
2716	(info->ChipFamily == CHIP_FAMILY_R420)) {	2730	(info->ChipFamily == CHIP_FAMILY_R420)) {
Lines 2719-2725 Link Here
2719	}	2733	}
2720		2734
2721	/* Some production boards of m6 will return 0 if it's 8 MB */	2735	/* Some production boards of m6 will return 0 if it's 8 MB */
2722	if (pScrn->videoRam == 0) pScrn->videoRam = 8192;	2736	if (pScrn->videoRam == 0) {
		2737	pScrn->videoRam = 8192;
		2738	OUTREG(RADEON_CONFIG_MEMSIZE, 0x800000);
		2739	}
2723		2740
2724	/* Check chip errata */	2741	/* Check chip errata */
2725	info->ChipErrata = 0;	2742	info->ChipErrata = 0;
Lines 5502-5532 Link Here
5502	info->tilingEnabled = (pScrn->currentMode->Flags & (V_DBLSCAN \| V_INTERLACE)) ? FALSE : TRUE;	5519	info->tilingEnabled = (pScrn->currentMode->Flags & (V_DBLSCAN \| V_INTERLACE)) ? FALSE : TRUE;
5503	}	5520	}
5504	}	5521	}
5505
5506	if (!info->IsSecondary) {
5507	/* empty the surfaces */
5508	unsigned char *RADEONMMIO = info->MMIO;
5509	unsigned int i;
5510	for (i = 0; i < 8; i++) {
5511	OUTREG(RADEON_SURFACE0_INFO + 16 * i, 0);
5512	OUTREG(RADEON_SURFACE0_LOWER_BOUND + 16 * i, 0);
5513	OUTREG(RADEON_SURFACE0_UPPER_BOUND + 16 * i, 0);
5514	}
5515	}
5516
5517	if (info->FBDev) {
5518	unsigned char *RADEONMMIO = info->MMIO;
5519
5520	if (!fbdevHWModeInit(pScrn, pScrn->currentMode)) return FALSE;
5521	info->ModeReg.surface_cntl = INREG(RADEON_SURFACE_CNTL);
5522	} else {
5523	if (!RADEONModeInit(pScrn, pScrn->currentMode)) return FALSE;
5524	}
5525
5526	RADEONSaveScreen(pScreen, SCREEN_SAVER_ON);
5527
5528	pScrn->AdjustFrame(scrnIndex, pScrn->frameX0, pScrn->frameY0, 0);
5529
5530	/* Visual setup */	5522	/* Visual setup */
5531	miClearVisualTypes();	5523	miClearVisualTypes();
5532	if (!miSetVisualTypes(pScrn->depth,	5524	if (!miSetVisualTypes(pScrn->depth,
Lines 5588-5593 Link Here
5588	}	5580	}
5589	}	5581	}
5590		5582
		5583	hasDRI = info->directRenderingEnabled;
		5584	#endif
		5585
		5586	/* Initialize the memory map, this basically calculates the values
		5587	* we'll use later on for MC_FB_LOCATION & MC_AGP_LOCATION
		5588	*/
		5589	RADEONInitMemoryMap(pScrn);
		5590
		5591	if (!info->IsSecondary) {
		5592	/* empty the surfaces */
		5593	unsigned char *RADEONMMIO = info->MMIO;
		5594	unsigned int i;
		5595	for (i = 0; i < 8; i++) {
		5596	OUTREG(RADEON_SURFACE0_INFO + 16 * i, 0);
		5597	OUTREG(RADEON_SURFACE0_LOWER_BOUND + 16 * i, 0);
		5598	OUTREG(RADEON_SURFACE0_UPPER_BOUND + 16 * i, 0);
		5599	}
		5600	}
		5601
		5602	if (info->FBDev) {
		5603	unsigned char *RADEONMMIO = info->MMIO;
		5604
		5605	if (!fbdevHWModeInit(pScrn, pScrn->currentMode)) return FALSE;
		5606	RADEONSaveMemMapRegisters(pScrn, &info->ModeReg);
		5607	info->fbLocation = (info->ModeReg.mc_fb_location & 0xffff) << 16;
		5608	info->ModeReg.surface_cntl = INREG(RADEON_SURFACE_CNTL);
		5609	} else {
		5610	if (!RADEONModeInit(pScrn, pScrn->currentMode)) return FALSE;
		5611	}
		5612
		5613	RADEONSaveScreen(pScreen, SCREEN_SAVER_ON);
		5614
		5615	pScrn->AdjustFrame(scrnIndex, pScrn->frameX0, pScrn->frameY0, 0);
		5616
5591	/* Depth moves are disabled by default since they are extremely slow */	5617	/* Depth moves are disabled by default since they are extremely slow */
5592	info->depthMoves = xf86ReturnOptValBool(info->Options,	5618	info->depthMoves = xf86ReturnOptValBool(info->Options,
5593	OPTION_DEPTH_MOVE, FALSE);	5619	OPTION_DEPTH_MOVE, FALSE);
Lines 5602-5612 Link Here
5602	"Depth moves disabled by default\n");	5628	"Depth moves disabled by default\n");
5603	}	5629	}
5604		5630
5605	hasDRI = info->directRenderingEnabled;
5606	#endif
5607
5608	RADEONSetFBLocation(pScrn);
5609
5610	if (!fbScreenInit(pScreen, info->FB,	5631	if (!fbScreenInit(pScreen, info->FB,
5611	pScrn->virtualX, pScrn->virtualY,	5632	pScrn->virtualX, pScrn->virtualY,
5612	pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth,	5633	pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth,
Lines 5798-5803 Link Here
5798	#endif /* USE_XAA */	5819	#endif /* USE_XAA */
5799	}	5820	}
5800	}	5821	}
		5822
		5823	/* DRI final init might have changed the memory map, we need to adjust
		5824	* our local image to make sure we restore them properly on mode changes
		5825	* or VT switches
		5826	*/
		5827	RADEONAdjustMemMapRegisters(pScrn, &info->ModeReg);
		5828
5801	if (info->directRenderingEnabled) {	5829	if (info->directRenderingEnabled) {
5802	if ((info->DispPriority == 1) && (info->cardType==CARD_AGP)) {	5830	if ((info->DispPriority == 1) && (info->cardType==CARD_AGP)) {
5803	/* we need to re-calculate bandwidth because of AGPMode difference. */	5831	/* we need to re-calculate bandwidth because of AGPMode difference. */
Lines 5837-5843 Link Here
5837	return TRUE;	5865	return TRUE;
5838	}	5866	}
5839		5867
5840	/* Write common registers (initialized to 0) */	5868	/* Write memory mapping registers */
		5869	static void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn,
		5870	RADEONSavePtr restore)
		5871	{
		5872	RADEONInfoPtr info = RADEONPTR(pScrn);
		5873	unsigned char *RADEONMMIO = info->MMIO;
		5874	int i;
		5875
		5876	RADEONTRACE(("RADEONRestoreMemMapRegisters() : \n"));
		5877	RADEONTRACE((" MC_FB_LOCATION : 0x%08lx\n", restore->mc_fb_location));
		5878	RADEONTRACE((" MC_AGP_LOCATION : 0x%08lx\n", restore->mc_agp_location));
		5879
		5880	/* Write memory mapping registers only if their value change
		5881	* since we must ensure no access is done while they are
		5882	* reprogrammed
		5883	*/
		5884	if (INREG(RADEON_MC_FB_LOCATION) != restore->mc_fb_location \|\|
		5885	INREG(RADEON_MC_AGP_LOCATION) != restore->mc_agp_location) {
		5886	CARD32 tmp;
		5887
		5888	RADEONTRACE((" Map Changed ! Applying ...\n"));
		5889
		5890	/* Make sure engine is idle. We assume the CCE is stopped
		5891	* at this point
		5892	*/
		5893	RADEONWaitForIdleMMIO(pScrn);
		5894
		5895	/* Stop display & memory access */
		5896	tmp = INREG(RADEON_CRTC_EXT_CNTL);
		5897	OUTREG(RADEON_CRTC_EXT_CNTL, tmp \| RADEON_CRTC_DISPLAY_DIS);
		5898	tmp = INREG(RADEON_CRTC_GEN_CNTL);
		5899	tmp &= ~RADEON_CRTC_CUR_EN;
		5900	tmp \|= RADEON_CRTC_DISP_REQ_EN_B;
		5901	OUTREG(RADEON_CRTC_GEN_CNTL, tmp);
		5902	if (info->HasCRTC2) {
		5903	tmp = INREG(RADEON_CRTC2_GEN_CNTL);
		5904	tmp &= ~RADEON_CRTC2_CUR_EN;
		5905	tmp \|= RADEON_CRTC2_DISP_DIS \| RADEON_CRTC2_DISP_REQ_EN_B;
		5906	OUTREG(RADEON_CRTC2_GEN_CNTL, tmp);
		5907	}
		5908	tmp = INREG(RADEON_OV0_SCALE_CNTL);
		5909	tmp &= ~RADEON_SCALER_ENABLE;
		5910
		5911	/* Clear all surfaces */
		5912	for (i = 0; i < 8; i++) {
		5913	OUTREG(RADEON_SURFACE0_INFO + 16 * i, 0);
		5914	OUTREG(RADEON_SURFACE0_LOWER_BOUND + 16 * i, 0);
		5915	OUTREG(RADEON_SURFACE0_UPPER_BOUND + 16 * i, 0);
		5916	}
		5917
		5918	/* Make sure the chip settles down and set new map*/
		5919	usleep(100000);
		5920	OUTREG(RADEON_MC_FB_LOCATION, restore->mc_fb_location);
		5921	OUTREG(RADEON_MC_AGP_LOCATION, restore->mc_agp_location);
		5922	/* Make sure map fully reached the chip */
		5923	(void)INREG(RADEON_MC_FB_LOCATION);
		5924	}
		5925
		5926	/* Restore base addresses */
		5927	OUTREG(RADEON_DISPLAY_BASE_ADDR, restore->display_base_addr);
		5928	OUTREG(RADEON_DISPLAY2_BASE_ADDR, restore->display2_base_addr);
		5929	OUTREG(RADEON_OV0_BASE_ADDR, restore->ov0_base_addr);
		5930	}
		5931
		5932	static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
5933	{
5934	RADEONInfoPtr info = RADEONPTR(pScrn);
5935	unsigned char *RADEONMMIO = info->MMIO;
5936	CARD32 fb, agp;
5937	int fb_loc_changed;
5938
5939	fb = INREG(RADEON_MC_FB_LOCATION);
5940	agp = INREG(RADEON_MC_AGP_LOCATION);
5941	fb_loc_changed = (fb != info->mc_fb_location);
5942
5943	if (fb_loc_changed \|\| agp != info->mc_agp_location) {
5944	xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
5945	"DRI init changed memory map, adjusting ...\n");
5946	xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
5947	"MC_FB_LOCATION was: 0x%08lx is: 0x%08lx\n",
5948	info->mc_fb_location, fb);
5949	xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
5950	"MC_AGP_LOCATION was: 0x%08lx is: 0x%08lx\n",
5951	info->mc_agp_location, agp);
5952	info->mc_fb_location = fb;
5953	info->mc_agp_location = agp;
5954	info->fbLocation = (save->mc_fb_location & 0xffff) << 16;
5955
5956	RADEONInitMemMapRegisters(pScrn, save, info);
5957
5958	/* If MC_FB_LOCATION was changed, adjust the various offsets */
5959	if (fb_loc_changed)
5960	RADEONRestoreMemMapRegisters(pScrn, save);
5961	}
5962	}
5963
5964	/* Write common registers */
5841	static void RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn,	5965	static void RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn,
5842	RADEONSavePtr restore)	5966	RADEONSavePtr restore)
5843	{	5967	{
Lines 6000-6012 Link Here
6000	OUTREG(RADEON_FP_VERT_STRETCH, restore->fp_vert_stretch);	6124	OUTREG(RADEON_FP_VERT_STRETCH, restore->fp_vert_stretch);
6001	OUTREG(RADEON_FP_GEN_CNTL, restore->fp_gen_cntl);	6125	OUTREG(RADEON_FP_GEN_CNTL, restore->fp_gen_cntl);
6002		6126
6003	/* old AIW Radeon has some BIOS initialization problem
6004	* with display buffer underflow, only occurs to DFP
6005	*/
6006	if (!info->HasCRTC2)
6007	OUTREG(RADEON_GRPH_BUFFER_CNTL,
6008	INREG(RADEON_GRPH_BUFFER_CNTL) & ~0x7f0000);
6009
6010	if (info->IsMobility) {	6127	if (info->IsMobility) {
6011	OUTREG(RADEON_BIOS_4_SCRATCH, restore->bios_4_scratch);	6128	OUTREG(RADEON_BIOS_4_SCRATCH, restore->bios_4_scratch);
6012	OUTREG(RADEON_BIOS_5_SCRATCH, restore->bios_5_scratch);	6129	OUTREG(RADEON_BIOS_5_SCRATCH, restore->bios_5_scratch);
Lines 6457-6462 Link Here
6457		6574
6458	/* For Non-dual head card, we don't have private field in the Entity */	6575	/* For Non-dual head card, we don't have private field in the Entity */
6459	if (!info->HasCRTC2) {	6576	if (!info->HasCRTC2) {
		6577	RADEONRestoreMemMapRegisters(pScrn, restore);
6460	RADEONRestoreCommonRegisters(pScrn, restore);	6578	RADEONRestoreCommonRegisters(pScrn, restore);
6461	RADEONRestoreCrtcRegisters(pScrn, restore);	6579	RADEONRestoreCrtcRegisters(pScrn, restore);
6462	RADEONRestoreFPRegisters(pScrn, restore);	6580	RADEONRestoreFPRegisters(pScrn, restore);
Lines 6474-6483 Link Here
6474	* order. Regardless the order of X server issuing the calls, we	6592	* order. Regardless the order of X server issuing the calls, we
6475	* have to ensure we set registers in the right order!!! Otherwise	6593	* have to ensure we set registers in the right order!!! Otherwise
6476	* we may get a blank screen.	6594	* we may get a blank screen.
		6595	*
		6596	* We always restore MemMap first, the saverec should be up to date
		6597	* in all cases
6477	*/	6598	*/
6478	if (info->IsSecondary) {	6599	if (info->IsSecondary) {
6479	if (!pRADEONEnt->RestorePrimary && !info->IsSwitching)	6600	RADEONRestoreMemMapRegisters(pScrn, restore);
6480	RADEONRestoreCommonRegisters(pScrn, restore);
6481	RADEONRestoreCrtc2Registers(pScrn, restore);	6601	RADEONRestoreCrtc2Registers(pScrn, restore);
6482	RADEONRestorePLL2Registers(pScrn, restore);	6602	RADEONRestorePLL2Registers(pScrn, restore);
6483		6603
Lines 6488-6502 Link Here
6488	if (pRADEONEnt->RestorePrimary) {	6608	if (pRADEONEnt->RestorePrimary) {
6489	pRADEONEnt->RestorePrimary = FALSE;	6609	pRADEONEnt->RestorePrimary = FALSE;
6490		6610
		6611	RADEONRestoreCommonRegisters(pScrn, &restore0);
6491	RADEONRestoreCrtcRegisters(pScrn, &restore0);	6612	RADEONRestoreCrtcRegisters(pScrn, &restore0);
6492	RADEONRestoreFPRegisters(pScrn, &restore0);	6613	RADEONRestoreFPRegisters(pScrn, &restore0);
6493	RADEONRestorePLLRegisters(pScrn, &restore0);	6614	RADEONRestorePLLRegisters(pScrn, &restore0);
6494	pRADEONEnt->IsSecondaryRestored = FALSE;	6615	pRADEONEnt->IsSecondaryRestored = FALSE;
6495	}	6616	}
6496	} else {	6617	} else {
6497	if (!pRADEONEnt->IsSecondaryRestored)	6618	RADEONRestoreMemMapRegisters(pScrn, restore);
6498	RADEONRestoreCommonRegisters(pScrn, restore);
6499
6500	if (info->MergedFB) {	6619	if (info->MergedFB) {
6501	RADEONRestoreCrtc2Registers(pScrn, restore);	6620	RADEONRestoreCrtc2Registers(pScrn, restore);
6502	RADEONRestorePLL2Registers(pScrn, restore);	6621	RADEONRestorePLL2Registers(pScrn, restore);
Lines 6506-6511 Link Here
6506	info->IsSwitching) {	6625	info->IsSwitching) {
6507	pRADEONEnt->IsSecondaryRestored = FALSE;	6626	pRADEONEnt->IsSecondaryRestored = FALSE;
6508		6627
		6628	RADEONRestoreCommonRegisters(pScrn, restore);
6509	RADEONRestoreCrtcRegisters(pScrn, restore);	6629	RADEONRestoreCrtcRegisters(pScrn, restore);
6510	RADEONRestoreFPRegisters(pScrn, restore);	6630	RADEONRestoreFPRegisters(pScrn, restore);
6511	RADEONRestorePLLRegisters(pScrn, restore);	6631	RADEONRestorePLLRegisters(pScrn, restore);
Lines 6520-6525 Link Here
6520	#endif	6640	#endif
6521	}	6641	}
6522		6642
		6643	/* Read memory map */
		6644	static void RADEONSaveMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
		6645	{
		6646	RADEONInfoPtr info = RADEONPTR(pScrn);
		6647	unsigned char *RADEONMMIO = info->MMIO;
		6648
		6649	save->mc_fb_location = INREG(RADEON_MC_FB_LOCATION);
		6650	save->mc_agp_location = INREG(RADEON_MC_AGP_LOCATION);
		6651	save->display_base_addr = INREG(RADEON_DISPLAY_BASE_ADDR);
		6652	save->display2_base_addr = INREG(RADEON_DISPLAY2_BASE_ADDR);
		6653	save->ov0_base_addr = INREG(RADEON_OV0_BASE_ADDR);
		6654	}
		6655
6523	/* Read common registers */	6656	/* Read common registers */
6524	static void RADEONSaveCommonRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)	6657	static void RADEONSaveCommonRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
6525	{	6658	{
Lines 6703-6708 Link Here
6703	RADEONInfoPtr info = RADEONPTR(pScrn);	6836	RADEONInfoPtr info = RADEONPTR(pScrn);
6704		6837
6705	RADEONTRACE(("RADEONSaveMode(%p)\n", save));	6838	RADEONTRACE(("RADEONSaveMode(%p)\n", save));
		6839	RADEONSaveMemMapRegisters(pScrn, save);
6706	RADEONSaveCommonRegisters(pScrn, save);	6840	RADEONSaveCommonRegisters(pScrn, save);
6707	if (info->IsSecondary) {	6841	if (info->IsSecondary) {
6708	RADEONSaveCrtc2Registers(pScrn, save);	6842	RADEONSaveCrtc2Registers(pScrn, save);
Lines 6731-6736 Link Here
6731		6865
6732	RADEONTRACE(("RADEONSave\n"));	6866	RADEONTRACE(("RADEONSave\n"));
6733	if (info->FBDev) {	6867	if (info->FBDev) {
		6868	RADEONSaveMemMapRegisters(pScrn, save);
6734	fbdevHWSave(pScrn);	6869	fbdevHWSave(pScrn);
6735	return;	6870	return;
6736	}	6871	}
Lines 6914-6919 Link Here
6914	int stop_req, max_stop_req;	7049	int stop_req, max_stop_req;
6915	float read_return_rate, time_disp1_drop_priority;	7050	float read_return_rate, time_disp1_drop_priority;
6916		7051
		7052	/*
		7053	* Set display0/1 priority up on r3/4xx in the memory controller for
		7054	* high res modes if the user specifies HIGH for displaypriority
		7055	* option.
		7056	*/
		7057	if ((info->DispPriority == 2) && IS_R300_VARIANT) {
		7058	CARD32 mc_init_misc_lat_timer = INREG(R300_MC_INIT_MISC_LAT_TIMER);
		7059	if (info->MergedFB \|\| pRADEONEnt->HasSecondary) {
		7060	mc_init_misc_lat_timer \|= 0x1100; /* display 0 and 1 */
		7061	} else {
		7062	mc_init_misc_lat_timer \|= 0x0100; /* display 0 only */
		7063	}
		7064	OUTREG(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
		7065	}
		7066
		7067
6917	/* R420 family not supported yet */	7068	/* R420 family not supported yet */
6918	if (info->ChipFamily == CHIP_FAMILY_R420) return;	7069	if (info->ChipFamily == CHIP_FAMILY_R420) return;
6919		7070
Lines 7822-7829 Link Here
7822	}	7973	}
7823		7974
7824	/* Define PLL registers for requested video mode */	7975	/* Define PLL registers for requested video mode */
7825	static void RADEONInitPLLRegisters(RADEONInfoPtr info, RADEONSavePtr save,	7976	static void RADEONInitPLLRegisters(ScrnInfoPtr pScrn, RADEONInfoPtr info,
7826	RADEONPLLPtr pll, double dot_clock)	7977	RADEONSavePtr save, RADEONPLLPtr pll,
		7978	double dot_clock)
7827	{	7979	{
7828	unsigned long freq = dot_clock * 100;	7980	unsigned long freq = dot_clock * 100;
7829		7981
Lines 7887-7894 Link Here
7887	}	8039	}
7888		8040
7889	/* Define PLL2 registers for requested video mode */	8041	/* Define PLL2 registers for requested video mode */
7890	static void RADEONInitPLL2Registers(RADEONSavePtr save, RADEONPLLPtr pll,	8042	static void RADEONInitPLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save,
7891	double dot_clock, int no_odd_postdiv)	8043	RADEONPLLPtr pll, double dot_clock,
		8044	int no_odd_postdiv)
7892	{	8045	{
7893	unsigned long freq = dot_clock * 100;	8046	unsigned long freq = dot_clock * 100;
7894		8047
Lines 8016-8026 Link Here
8016		8169
8017	info->Flags = mode->Flags;	8170	info->Flags = mode->Flags;
8018		8171
		8172	RADEONInitMemMapRegisters(pScrn, save, info);
8019	RADEONInitCommonRegisters(save, info);	8173	RADEONInitCommonRegisters(save, info);
8020	if (info->IsSecondary) {	8174	if (info->IsSecondary) {
8021	if (!RADEONInitCrtc2Registers(pScrn, save, mode, info))	8175	if (!RADEONInitCrtc2Registers(pScrn, save, mode, info))
8022	return FALSE;	8176	return FALSE;
8023	RADEONInitPLL2Registers(save, &info->pll, dot_clock, info->DisplayType != MT_CRT);	8177	RADEONInitPLL2Registers(pScrn, save, &info->pll, dot_clock, info->DisplayType != MT_CRT);
8024	} else if (info->MergedFB) {	8178	} else if (info->MergedFB) {
8025	RADEONInitCommonRegisters(save, info);	8179	RADEONInitCommonRegisters(save, info);
8026	if (!RADEONInitCrtcRegisters(pScrn, save,	8180	if (!RADEONInitCrtcRegisters(pScrn, save,
Lines 8028-8034 Link Here
8028	return FALSE;	8182	return FALSE;
8029	dot_clock = (((RADEONMergedDisplayModePtr)mode->Private)->CRT1)->Clock / 1000.0;	8183	dot_clock = (((RADEONMergedDisplayModePtr)mode->Private)->CRT1)->Clock / 1000.0;
8030	if (dot_clock) {	8184	if (dot_clock) {
8031	RADEONInitPLLRegisters(info, save, &info->pll, dot_clock);	8185	RADEONInitPLLRegisters(pScrn, info, save, &info->pll, dot_clock);
8032	} else {	8186	} else {
8033	save->ppll_ref_div = info->SavedReg.ppll_ref_div;	8187	save->ppll_ref_div = info->SavedReg.ppll_ref_div;
8034	save->ppll_div_3 = info->SavedReg.ppll_div_3;	8188	save->ppll_div_3 = info->SavedReg.ppll_div_3;
Lines 8037-8049 Link Here
8037	RADEONInitCrtc2Registers(pScrn, save,	8191	RADEONInitCrtc2Registers(pScrn, save,
8038	((RADEONMergedDisplayModePtr)mode->Private)->CRT2, info);	8192	((RADEONMergedDisplayModePtr)mode->Private)->CRT2, info);
8039	dot_clock = (((RADEONMergedDisplayModePtr)mode->Private)->CRT2)->Clock / 1000.0;	8193	dot_clock = (((RADEONMergedDisplayModePtr)mode->Private)->CRT2)->Clock / 1000.0;
8040	RADEONInitPLL2Registers(save, &info->pll, dot_clock, info->MergeType != MT_CRT);	8194	RADEONInitPLL2Registers(pScrn, save, &info->pll, dot_clock, info->MergeType != MT_CRT);
8041	} else {	8195	} else {
8042	if (!RADEONInitCrtcRegisters(pScrn, save, mode, info))	8196	if (!RADEONInitCrtcRegisters(pScrn, save, mode, info))
8043	return FALSE;	8197	return FALSE;
8044	dot_clock = mode->Clock/1000.0;	8198	dot_clock = mode->Clock/1000.0;
8045	if (dot_clock) {	8199	if (dot_clock) {
8046	RADEONInitPLLRegisters(info, save, &info->pll, dot_clock);	8200	RADEONInitPLLRegisters(pScrn, info, save, &info->pll, dot_clock);
8047	} else {	8201	} else {
8048	save->ppll_ref_div = info->SavedReg.ppll_ref_div;	8202	save->ppll_ref_div = info->SavedReg.ppll_ref_div;
8049	save->ppll_div_3 = info->SavedReg.ppll_div_3;	8203	save->ppll_div_3 = info->SavedReg.ppll_div_3;
Lines 8396-8408 Link Here
8396	} else	8550	} else
8397	if (!RADEONModeInit(pScrn, pScrn->currentMode)) return FALSE;	8551	if (!RADEONModeInit(pScrn, pScrn->currentMode)) return FALSE;
8398		8552
8399	RADEONSetFBLocation(pScrn);
8400	if (!info->IsSecondary)	8553	if (!info->IsSecondary)
8401	RADEONRestoreSurfaces(pScrn, &info->ModeReg);	8554	RADEONRestoreSurfaces(pScrn, &info->ModeReg);
8402	#ifdef XF86DRI	8555	#ifdef XF86DRI
8403	if (info->directRenderingEnabled) {	8556	if (info->directRenderingEnabled) {
8404	/* get the Radeon back into shape after resume */	8557	/* get the Radeon back into shape after resume */
8405	RADEONDRIResume(pScrn->pScreen);	8558	RADEONDRIResume(pScrn->pScreen);
		8559	RADEONAdjustMemMapRegisters(pScrn, &info->ModeReg);
8406	}	8560	}
8407	#endif	8561	#endif
8408	/* this will get XVideo going again, but only if XVideo was initialised	8562	/* this will get XVideo going again, but only if XVideo was initialised





/* ------------------------------------- */

#define RADEON_DEBUG            1 /* Turn off debugging output               */
#define RADEON_IDLE_RETRY      16 /* Fall out of idle loops after this count */
#define RADEON_TIMEOUT    2000000 /* Fall out of wait loops after this count */
#define RADEON_MMIOSIZE   0x80000

				   */

#if RADEON_DEBUG
#define RADEONTRACE(x)                                         \
do {									\
    ErrorF("(**) %s(%d): ", RADEON_NAME, pScrn->scrnIndex);		\
    ErrorF x;								\
} while(0)
#else
#define RADEONTRACE(x) do { } while(0)
#endif



    CARD32            cap0_trig_cntl;
    CARD32            cap1_trig_cntl;
    CARD32            bus_cntl;
    CARD32            surface_cntl;
    CARD32            bios_4_scratch;
    CARD32            bios_5_scratch;
    CARD32            bios_6_scratch;
    CARD32            surface_cntl;
    CARD32            surfaces[8][3];
    CARD32            mc_agp_location;
    CARD32            mc_fb_location;
    CARD32            display_base_addr;
    CARD32            display2_base_addr;
    CARD32            ov0_base_addr;

				/* Other registers to save for VT switches */
    CARD32            dp_datatype;

    CARD32            clock_cntl_index;
    CARD32            amcgpio_en_reg;
    CARD32            amcgpio_mask;
    
    CARD32            surfaces[8][3];

				/* CRTC registers */
    CARD32            crtc_gen_cntl;

    unsigned long     MMIOAddr;         /* MMIO region physical address      */
    unsigned long     BIOSAddr;         /* BIOS physical address             */
    unsigned int      fbLocation;
    CARD32            mc_fb_location;
    CARD32            mc_agp_location;

    unsigned char     *MMIO;            /* Map of MMIO region                */
    unsigned char     *FB;              /* Map of frame buffer               */

Return to bug 127757

Lines 102-108 Link Here

(-)xc.orig/programs/Xserver/hw/xfree86/drivers/ati/radeon.h (-7 / +13 lines)
102		102
103	/* ------------------------------------- */	103	/* ------------------------------------- */
104		104
105	#define RADEON_DEBUG 0 /* Turn off debugging output */	105	#define RADEON_DEBUG 1 /* Turn off debugging output */
106	#define RADEON_IDLE_RETRY 16 /* Fall out of idle loops after this count */	106	#define RADEON_IDLE_RETRY 16 /* Fall out of idle loops after this count */
107	#define RADEON_TIMEOUT 2000000 /* Fall out of wait loops after this count */	107	#define RADEON_TIMEOUT 2000000 /* Fall out of wait loops after this count */
108	#define RADEON_MMIOSIZE 0x80000	108	#define RADEON_MMIOSIZE 0x80000
Lines 116-128 Link Here
116	*/	116	*/
117		117
118	#if RADEON_DEBUG	118	#if RADEON_DEBUG
119	#define RADEONTRACE(x) \	119	#define RADEONTRACE(x) \
120	do { \	120	do { \
121	ErrorF("(**) %s(%d): ", RADEON_NAME, pScrn->scrnIndex); \	121	ErrorF("(**) %s(%d): ", RADEON_NAME, pScrn->scrnIndex); \
122	ErrorF x; \	122	ErrorF x; \
123	} while (0);	123	} while(0)
124	#else	124	#else
125	#define RADEONTRACE(x)	125	#define RADEONTRACE(x) do { } while(0)
126	#endif	126	#endif
127		127
128		128
Lines 147-156 Link Here
147	CARD32 cap0_trig_cntl;	147	CARD32 cap0_trig_cntl;
148	CARD32 cap1_trig_cntl;	148	CARD32 cap1_trig_cntl;
149	CARD32 bus_cntl;	149	CARD32 bus_cntl;
150	CARD32 surface_cntl;
151	CARD32 bios_4_scratch;	150	CARD32 bios_4_scratch;
152	CARD32 bios_5_scratch;	151	CARD32 bios_5_scratch;
153	CARD32 bios_6_scratch;	152	CARD32 bios_6_scratch;
		153	CARD32 surface_cntl;
		154	CARD32 surfaces[8][3];
		155	CARD32 mc_agp_location;
		156	CARD32 mc_fb_location;
		157	CARD32 display_base_addr;
		158	CARD32 display2_base_addr;
		159	CARD32 ov0_base_addr;
154		160
155	/* Other registers to save for VT switches */	161	/* Other registers to save for VT switches */
156	CARD32 dp_datatype;	162	CARD32 dp_datatype;
Lines 158-165 Link Here
158	CARD32 clock_cntl_index;	164	CARD32 clock_cntl_index;
159	CARD32 amcgpio_en_reg;	165	CARD32 amcgpio_en_reg;
160	CARD32 amcgpio_mask;	166	CARD32 amcgpio_mask;
161
162	CARD32 surfaces[8][3];
163		167
164	/* CRTC registers */	168	/* CRTC registers */
165	CARD32 crtc_gen_cntl;	169	CARD32 crtc_gen_cntl;
Lines 326-331 Link Here
326	unsigned long MMIOAddr; /* MMIO region physical address */	330	unsigned long MMIOAddr; /* MMIO region physical address */
327	unsigned long BIOSAddr; /* BIOS physical address */	331	unsigned long BIOSAddr; /* BIOS physical address */
328	unsigned int fbLocation;	332	unsigned int fbLocation;
		333	CARD32 mc_fb_location;
		334	CARD32 mc_agp_location;
329		335
330	unsigned char MMIO; / Map of MMIO region */	336	unsigned char MMIO; / Map of MMIO region */
331	unsigned char FB; / Map of frame buffer */	337	unsigned char FB; / Map of frame buffer */