Attachment #65719 for bug #146687

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Lines 243-252 Link Here

(-)drm-HEAD.orig/shared-core/r300_cmdbuf.c (-4 / +6 lines)
243	but this value is not being kept.	243	but this value is not being kept.
244	This code is correct for now (does the same thing as the	244	This code is correct for now (does the same thing as the
245	code that sets MC_FB_LOCATION) in radeon_cp.c */	245	code that sets MC_FB_LOCATION) in radeon_cp.c */
246	if((offset>=dev_priv->fb_location) &&	246	if (offset >= dev_priv->fb_location &&
247	(offset<dev_priv->gart_vm_start))return 0;	247	offset < (dev_priv->fb_location + dev_priv->fb_size))
248	if((offset>=dev_priv->gart_vm_start) &&	248	return 0;
249	(offset<dev_priv->gart_vm_start+dev_priv->gart_size))return 0;	249	if (offset >= dev_priv->gart_vm_start &&
		250	offset < (dev_priv->gart_vm_start + dev_priv->gart_size))
		251	return 0;
250	return 1;	252	return 1;
251	}	253	}
252		254

Lines 1118-1128 Link Here

(-)drm-HEAD.orig/shared-core/radeon_cp.c (-6 / +46 lines)
1118	{	1118	{
1119	u32 ring_start, cur_read_ptr;	1119	u32 ring_start, cur_read_ptr;
1120	u32 tmp;	1120	u32 tmp;
1121		1121
1122	/* Initialize the memory controller */	1122	/* Initialize the memory controller. With new memory map, the fb location
1123	RADEON_WRITE(RADEON_MC_FB_LOCATION,	1123	* is not changed, it should have been properly initialized already. Part
1124	((dev_priv->gart_vm_start - 1) & 0xffff0000)	1124	* of the problem is that the code below is bogus, assuming the GART is
1125	\| (dev_priv->fb_location >> 16));	1125	* always appended to the fb which is not necessarily the case
		1126	*/
		1127	if (!dev_priv->new_memmap)
		1128	RADEON_WRITE(RADEON_MC_FB_LOCATION,
		1129	((dev_priv->gart_vm_start - 1) & 0xffff0000)
		1130	\| (dev_priv->fb_location >> 16));
1126		1131
1127	#if __OS_HAS_AGP	1132	#if __OS_HAS_AGP
1128	if (dev_priv->flags & CHIP_IS_AGP) {	1133	if (dev_priv->flags & CHIP_IS_AGP) {
Lines 1489-1494 Link Here
1489		1494
1490	dev_priv->fb_location = (RADEON_READ(RADEON_MC_FB_LOCATION)	1495	dev_priv->fb_location = (RADEON_READ(RADEON_MC_FB_LOCATION)
1491	& 0xffff) << 16;	1496	& 0xffff) << 16;
		1497	dev_priv->fb_size =
		1498	((RADEON_READ(RADEON_MC_FB_LOCATION) & 0xffff0000u) + 0x10000)
		1499	- dev_priv->fb_location;
1492		1500
1493	dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) \|	1501	dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) \|
1494	((dev_priv->front_offset	1502	((dev_priv->front_offset
Lines 1504-1510 Link Here
1504		1512
1505	dev_priv->gart_size = init->gart_size;	1513	dev_priv->gart_size = init->gart_size;
1506		1514
1507	dev_priv->gart_vm_start = dev_priv->fb_location + RADEON_READ(RADEON_CONFIG_APER_SIZE);	1515	/* New let's set the memory map ... */
		1516	if (dev_priv->new_memmap) {
		1517	u32 base = 0;
		1518
		1519	DRM_DEBUG("Setting AGP location based on new memory map\n");
		1520
		1521	/* If using AGP, try to locate the AGP aperture at the same
		1522	* location in the card and on the bus, though we have to
		1523	* align it down.
		1524	*/
		1525	#if __OS_HAS_AGP
		1526	if (dev_priv->flags & CHIP_IS_AGP) {
		1527	base = dev->agp->base;
		1528	/* Check if valid */
		1529	if ((base + dev_priv->gart_size) > dev_priv->fb_location &&
		1530	base < (dev_priv->fb_location + dev_priv->fb_size))
		1531	base = 0;
		1532	}
		1533	#endif
		1534	/* If not or if AGP is at 0 (Macs), try to put it elsewhere */
		1535	if (base == 0) {
		1536	base = dev_priv->fb_location + dev_priv->fb_size;
		1537	if (((base + dev_priv->gart_size) & 0xfffffffful)
		1538	< base)
		1539	base = dev_priv->fb_location
		1540	- dev_priv->gart_size;
		1541	}
		1542	dev_priv->gart_vm_start = base & 0xffc00000u;
		1543	} else {
		1544	DRM_DEBUG("Setting AGP location based on old memory map\n");
		1545	dev_priv->gart_vm_start = dev_priv->fb_location +
		1546	RADEON_READ(RADEON_CONFIG_APER_SIZE);
		1547	}
1508		1548
1509	#if __OS_HAS_AGP	1549	#if __OS_HAS_AGP
1510	if (dev_priv->flags & CHIP_IS_AGP)	1550	if (dev_priv->flags & CHIP_IS_AGP)

Lines 698-703 Link Here

(-)drm-HEAD.orig/shared-core/radeon_drm.h (+2 lines)
698	#define RADEON_SETPARAM_SWITCH_TILING 2 /* enable/disable color tiling */	698	#define RADEON_SETPARAM_SWITCH_TILING 2 /* enable/disable color tiling */
699	#define RADEON_SETPARAM_PCIGART_LOCATION 3 /* PCI Gart Location */	699	#define RADEON_SETPARAM_PCIGART_LOCATION 3 /* PCI Gart Location */
700		700
		701	#define RADEON_SETPARAM_NEW_MEMMAP 4 /* Use new memory map */
		702
701	/* 1.14: Clients can allocate/free a surface	703	/* 1.14: Clients can allocate/free a surface
702	*/	704	*/
703	typedef struct drm_radeon_surface_alloc {	705	typedef struct drm_radeon_surface_alloc {

Lines 93-99 Link Here

(-)drm-HEAD.orig/shared-core/radeon_drv.h (-1 / +3 lines)
93	*/	93	*/
94		94
95	#define DRIVER_MAJOR 1	95	#define DRIVER_MAJOR 1
96	#define DRIVER_MINOR 22	96	#define DRIVER_MINOR 23
97	#define DRIVER_PATCHLEVEL 0	97	#define DRIVER_PATCHLEVEL 0
98		98
99	enum radeon_family {	99	enum radeon_family {
Lines 197-202 Link Here
197	drm_radeon_sarea_t *sarea_priv;	197	drm_radeon_sarea_t *sarea_priv;
198		198
199	u32 fb_location;	199	u32 fb_location;
		200	u32 fb_size;
		201	int new_memmap;
200		202
201	int gart_size;	203	int gart_size;
202	u32 gart_vm_start;	204	u32 gart_vm_start;




	u32 off = *offset;
	struct drm_radeon_driver_file_fields *radeon_priv;

	/* Hrm ... the story of the offset ... So this function converts
	 * the various ideas of what userland clients might have for an
	 * offset in the card address space into an offset into the card
	 * address space :) So with a sane client, it should just keep
	 * the value intact and just do some boundary checking. However,
	 * not all clients are sane. Some older clients pass us 0 based
	 * offsets relative to the start of the framebuffer and some may
	 * assume the AGP aperture it appended to the framebuffer, so we
	 * try to detect those cases and fix them up.
	 *
	 * Note: It might be a good idea here to make sure the offset lands
	 * in some "allowed" area to protect things like the PCIE GART...
	 */

	/* First, the best case, the offset already lands in either the
	 * framebuffer or the GART mapped space
	 */
	if ((off >= dev_priv->fb_location &&
	     off < (dev_priv->fb_location + dev_priv->fb_size)) ||
	    (off >= dev_priv->gart_vm_start &&
	     off < (dev_priv->gart_vm_start + dev_priv->gart_size)))
		return 0;

	/* Ok, that didn't happen... now check if we have a zero based
	 * offset that fits in the framebuffer + gart space, apply the
	 * magic offset we get from SETPARAM or calculated from fb_location
	 */
	if (off < (dev_priv->fb_size + dev_priv->gart_size)) {
		radeon_priv = filp_priv->driver_priv;
		off += radeon_priv->radeon_fb_delta;
	}
		return DRM_ERR(EINVAL);

	*offset = off;

	/* Finally, assume we aimed at a GART offset if beyond the fb */
	if (off > (dev_priv->fb_location + dev_priv->fb_size))
		off = off - (dev_priv->fb_location + dev_priv->fb_size) +
			dev_priv->gart_vm_start;

	/* Now recheck and fail if out of bounds */
	if ((off >= dev_priv->fb_location &&
	     off < (dev_priv->fb_location + dev_priv->fb_size)) ||
	    (off >= dev_priv->gart_vm_start &&
	     off < (dev_priv->gart_vm_start + dev_priv->gart_size))) {
		DRM_DEBUG("offset fixed up to 0x%x\n", off);
		*offset = off;
		return 0;
	}
	return DRM_ERR(EINVAL);
}

static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t *

	case RADEON_SETPARAM_PCIGART_LOCATION:
		dev_priv->pcigart_offset = sp.value;
		break;
	case RADEON_SETPARAM_NEW_MEMMAP:
		dev_priv->new_memmap = sp.value;
		break;
	default:
		DRM_DEBUG("Invalid parameter %d\n", sp.param);
		return DRM_ERR(EINVAL);

Return to bug 146687

Lines 45-67 Link Here

(-)drm-HEAD.orig/shared-core/radeon_state.c (-14 / +47 lines)
45	u32 off = *offset;	45	u32 off = *offset;
46	struct drm_radeon_driver_file_fields *radeon_priv;	46	struct drm_radeon_driver_file_fields *radeon_priv;
47		47
48	if (off >= dev_priv->fb_location &&	48	/* Hrm ... the story of the offset ... So this function converts
49	off < (dev_priv->gart_vm_start + dev_priv->gart_size))	49	* the various ideas of what userland clients might have for an
		50	* offset in the card address space into an offset into the card
		51	* address space :) So with a sane client, it should just keep
		52	* the value intact and just do some boundary checking. However,
		53	* not all clients are sane. Some older clients pass us 0 based
		54	* offsets relative to the start of the framebuffer and some may
		55	* assume the AGP aperture it appended to the framebuffer, so we
		56	* try to detect those cases and fix them up.
		57	*
		58	* Note: It might be a good idea here to make sure the offset lands
		59	* in some "allowed" area to protect things like the PCIE GART...
		60	*/
		61
		62	/* First, the best case, the offset already lands in either the
		63	* framebuffer or the GART mapped space
		64	*/
		65	if ((off >= dev_priv->fb_location &&
		66	off < (dev_priv->fb_location + dev_priv->fb_size)) \|\|
		67	(off >= dev_priv->gart_vm_start &&
		68	off < (dev_priv->gart_vm_start + dev_priv->gart_size)))
50	return 0;	69	return 0;
51		70
52	radeon_priv = filp_priv->driver_priv;	71	/* Ok, that didn't happen... now check if we have a zero based
53		72	* offset that fits in the framebuffer + gart space, apply the
54	off += radeon_priv->radeon_fb_delta;	73	* magic offset we get from SETPARAM or calculated from fb_location
55		74	*/
56	DRM_DEBUG("offset fixed up to 0x%x\n", off);	75	if (off < (dev_priv->fb_size + dev_priv->gart_size)) {
57		76	radeon_priv = filp_priv->driver_priv;
58	if (off < dev_priv->fb_location \|\|	77	off += radeon_priv->radeon_fb_delta;
59	off >= (dev_priv->gart_vm_start + dev_priv->gart_size))	78	}
60	return DRM_ERR(EINVAL);
61
62	*offset = off;
63		79
64	return 0;	80	/* Finally, assume we aimed at a GART offset if beyond the fb */
		81	if (off > (dev_priv->fb_location + dev_priv->fb_size))
		82	off = off - (dev_priv->fb_location + dev_priv->fb_size) +
		83	dev_priv->gart_vm_start;
		84
		85	/* Now recheck and fail if out of bounds */
		86	if ((off >= dev_priv->fb_location &&
		87	off < (dev_priv->fb_location + dev_priv->fb_size)) \|\|
		88	(off >= dev_priv->gart_vm_start &&
		89	off < (dev_priv->gart_vm_start + dev_priv->gart_size))) {
		90	DRM_DEBUG("offset fixed up to 0x%x\n", off);
		91	*offset = off;
		92	return 0;
		93	}
		94	return DRM_ERR(EINVAL);
65	}	95	}
66		96
67	static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t *	97	static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t *
Lines 3014-3019 Link Here
3014	case RADEON_SETPARAM_PCIGART_LOCATION:	3044	case RADEON_SETPARAM_PCIGART_LOCATION:
3015	dev_priv->pcigart_offset = sp.value;	3045	dev_priv->pcigart_offset = sp.value;
3016	break;	3046	break;
		3047	case RADEON_SETPARAM_NEW_MEMMAP:
		3048	dev_priv->new_memmap = sp.value;
		3049	break;
3017	default:	3050	default:
3018	DRM_DEBUG("Invalid parameter %d\n", sp.param);	3051	DRM_DEBUG("Invalid parameter %d\n", sp.param);
3019	return DRM_ERR(EINVAL);	3052	return DRM_ERR(EINVAL);