Attachment #66151 for bug #146687

View | Details | Raw Unified | Return to bug 146687
Collapse All | Expand All

Lines 250-260 Link Here

(-)drivers/char/drm.orig/r300_cmdbuf.c (-4 / +4 lines)
250	but this value is not being kept.	250	but this value is not being kept.
251	This code is correct for now (does the same thing as the	251	This code is correct for now (does the same thing as the
252	code that sets MC_FB_LOCATION) in radeon_cp.c */	252	code that sets MC_FB_LOCATION) in radeon_cp.c */
253	if ((offset >= dev_priv->fb_location) &&	253	if (offset >= dev_priv->fb_location &&
254	(offset < dev_priv->gart_vm_start))	254	offset < (dev_priv->gart_vm_start + dev_priv->fb_size))
255	return 0;	255	return 0;
256	if ((offset >= dev_priv->gart_vm_start) &&	256	if (offset >= dev_priv->gart_vm_start &&
257	(offset < dev_priv->gart_vm_start + dev_priv->gart_size))	257	offset < (dev_priv->gart_vm_start + dev_priv->gart_size))
258	return 0;	258	return 0;
259	return 1;	259	return 1;
260	}	260	}

Lines 1118-1128 Link Here

(-)drivers/char/drm.orig/radeon_cp.c (-7 / +47 lines)
1118	{	1118	{
1119	u32 ring_start, cur_read_ptr;	1119	u32 ring_start, cur_read_ptr;
1120	u32 tmp;	1120	u32 tmp;
1121		1121
1122	/* Initialize the memory controller */	1122	/* Initialize the memory controller. With new memory map, the fb location
1123	RADEON_WRITE(RADEON_MC_FB_LOCATION,	1123	* is not changed, it should have been properly initialized already. Part
1124	((dev_priv->gart_vm_start - 1) & 0xffff0000)	1124	* of the problem is that the code below is bogus, assuming the GART is
1125	\| (dev_priv->fb_location >> 16));	1125	* always appended to the fb which is not necessarily the case
		1126	*/
		1127	if (!dev_priv->new_memmap)
		1128	RADEON_WRITE(RADEON_MC_FB_LOCATION,
		1129	((dev_priv->gart_vm_start - 1) & 0xffff0000)
		1130	\| (dev_priv->fb_location >> 16));
1126		1131
1127	#if __OS_HAS_AGP	1132	#if __OS_HAS_AGP
1128	if (dev_priv->flags & CHIP_IS_AGP) {	1133	if (dev_priv->flags & CHIP_IS_AGP) {
Lines 1496-1501 Link Here
1496		1501
1497	dev_priv->fb_location = (RADEON_READ(RADEON_MC_FB_LOCATION)	1502	dev_priv->fb_location = (RADEON_READ(RADEON_MC_FB_LOCATION)
1498	& 0xffff) << 16;	1503	& 0xffff) << 16;
		1504	dev_priv->fb_size =
		1505	((RADEON_READ(RADEON_MC_FB_LOCATION) & 0xffff0000u) + 0x10000)
		1506	- dev_priv->fb_location;
1499		1507
1500	dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) \|	1508	dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) \|
1501	((dev_priv->front_offset	1509	((dev_priv->front_offset
Lines 1510-1517 Link Here
1510	+ dev_priv->fb_location) >> 10));	1518	+ dev_priv->fb_location) >> 10));
1511		1519
1512	dev_priv->gart_size = init->gart_size;	1520	dev_priv->gart_size = init->gart_size;
1513	dev_priv->gart_vm_start = dev_priv->fb_location	1521
1514	+ RADEON_READ(RADEON_CONFIG_APER_SIZE);	1522	/* New let's set the memory map ... */
		1523	if (dev_priv->new_memmap) {
		1524	u32 base = 0;
		1525
		1526	DRM_DEBUG("Setting AGP location based on new memory map\n");
		1527
		1528	/* If using AGP, try to locate the AGP aperture at the same
		1529	* location in the card and on the bus, though we have to
		1530	* align it down.
		1531	*/
		1532	#if __OS_HAS_AGP
		1533	if (dev_priv->flags & CHIP_IS_AGP) {
		1534	base = dev->agp->base;
		1535	/* Check if valid */
		1536	if ((base + dev_priv->gart_size) > dev_priv->fb_location &&
		1537	base < (dev_priv->fb_location + dev_priv->fb_size))
		1538	base = 0;
		1539	}
		1540	#endif
		1541	/* If not or if AGP is at 0 (Macs), try to put it elsewhere */
		1542	if (base == 0) {
		1543	base = dev_priv->fb_location + dev_priv->fb_size;
		1544	if (((base + dev_priv->gart_size) & 0xfffffffful)
		1545	< base)
		1546	base = dev_priv->fb_location
		1547	- dev_priv->gart_size;
		1548	}
		1549	dev_priv->gart_vm_start = base & 0xffc00000u;
		1550	} else {
		1551	DRM_DEBUG("Setting AGP location based on old memory map\n");
		1552	dev_priv->gart_vm_start = dev_priv->fb_location +
		1553	RADEON_READ(RADEON_CONFIG_APER_SIZE);
		1554	}
1515		1555
1516	#if __OS_HAS_AGP	1556	#if __OS_HAS_AGP
1517	if (dev_priv->flags & CHIP_IS_AGP)	1557	if (dev_priv->flags & CHIP_IS_AGP)

Lines 698-703 Link Here

(-)drivers/char/drm.orig/radeon_drm.h (+2 lines)
698	#define RADEON_SETPARAM_SWITCH_TILING 2 /* enable/disable color tiling */	698	#define RADEON_SETPARAM_SWITCH_TILING 2 /* enable/disable color tiling */
699	#define RADEON_SETPARAM_PCIGART_LOCATION 3 /* PCI Gart Location */	699	#define RADEON_SETPARAM_PCIGART_LOCATION 3 /* PCI Gart Location */
700		700
		701	#define RADEON_SETPARAM_NEW_MEMMAP 4 /* Use new memory map */
		702
701	/* 1.14: Clients can allocate/free a surface	703	/* 1.14: Clients can allocate/free a surface
702	*/	704	*/
703	typedef struct drm_radeon_surface_alloc {	705	typedef struct drm_radeon_surface_alloc {

Lines 92-98 Link Here

(-)drivers/char/drm.orig/radeon_drv.h (-1 / +3 lines)
92	* 1.21- Add support for card type getparam	92	* 1.21- Add support for card type getparam
93	*/	93	*/
94	#define DRIVER_MAJOR 1	94	#define DRIVER_MAJOR 1
95	#define DRIVER_MINOR 21	95	#define DRIVER_MINOR 23
96	#define DRIVER_PATCHLEVEL 0	96	#define DRIVER_PATCHLEVEL 0
97		97
98	/*	98	/*
Lines 198-203 Link Here
198	drm_radeon_sarea_t *sarea_priv;	198	drm_radeon_sarea_t *sarea_priv;
199		199
200	u32 fb_location;	200	u32 fb_location;
		201	u32 fb_size;
		202	int new_memmap;
201		203
202	int gart_size;	204	int gart_size;
203	u32 gart_vm_start;	205	u32 gart_vm_start;




	u32 off = *offset;
	struct drm_radeon_driver_file_fields *radeon_priv;

        /* Hrm ... the story of the offset ... So this function converts
         * the various ideas of what userland clients might have for an
         * offset in the card address space into an offset into the card
         * address space :) So with a sane client, it should just keep
         * the value intact and just do some boundary checking. However,
         * not all clients are sane. Some older clients pass us 0 based
         * offsets relative to the start of the framebuffer and some may
         * assume the AGP aperture it appended to the framebuffer, so we
         * try to detect those cases and fix them up.
         *
         * Note: It might be a good idea here to make sure the offset lands
         * in some "allowed" area to protect things like the PCIE GART...
         */
 
        /* First, the best case, the offset already lands in either the
         * framebuffer or the GART mapped space
         */
        if ((off >= dev_priv->fb_location &&
             off < (dev_priv->fb_location + dev_priv->fb_size)) ||
            (off >= dev_priv->gart_vm_start &&
             off < (dev_priv->gart_vm_start + dev_priv->gart_size)))
                return 0;
  
        /* Ok, that didn't happen... now check if we have a zero based
         * offset that fits in the framebuffer + gart space, apply the
         * magic offset we get from SETPARAM or calculated from fb_location
         */
        if (off < (dev_priv->fb_size + dev_priv->gart_size)) {
                radeon_priv = filp_priv->driver_priv;
                off += radeon_priv->radeon_fb_delta;
        }
  
        /* Finally, assume we aimed at a GART offset if beyond the fb */
        if (off > (dev_priv->fb_location + dev_priv->fb_size))
                off = off - (dev_priv->fb_location + dev_priv->fb_size) +
                        dev_priv->gart_vm_start;
 
        /* Now recheck and fail if out of bounds */
        if ((off >= dev_priv->fb_location &&
             off < (dev_priv->fb_location + dev_priv->fb_size)) ||
            (off >= dev_priv->gart_vm_start &&
             off < (dev_priv->gart_vm_start + dev_priv->gart_size))) {
                DRM_DEBUG("offset fixed up to 0x%x\n", off);
                *offset = off;
                return 0;
        }
        return DRM_ERR(EINVAL);
}

static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t *

	case RADEON_SETPARAM_PCIGART_LOCATION:
		dev_priv->pcigart_offset = sp.value;
		break;
	case RADEON_SETPARAM_NEW_MEMMAP:
		dev_priv->new_memmap = sp.value;
		break;
	default:
		DRM_DEBUG("Invalid parameter %d\n", sp.param);
		return DRM_ERR(EINVAL);

Return to bug 146687

Lines 45-66 Link Here

(-)drivers/char/drm.orig/radeon_state.c (-16 / +50 lines)
45	u32 off = *offset;	45	u32 off = *offset;
46	struct drm_radeon_driver_file_fields *radeon_priv;	46	struct drm_radeon_driver_file_fields *radeon_priv;
47		47
48	if (off >= dev_priv->fb_location &&	48	/* Hrm ... the story of the offset ... So this function converts
49	off < (dev_priv->gart_vm_start + dev_priv->gart_size))	49	* the various ideas of what userland clients might have for an
50	return 0;	50	* offset in the card address space into an offset into the card
51		51	* address space :) So with a sane client, it should just keep
52	radeon_priv = filp_priv->driver_priv;	52	* the value intact and just do some boundary checking. However,
53	off += radeon_priv->radeon_fb_delta;	53	* not all clients are sane. Some older clients pass us 0 based
54		54	* offsets relative to the start of the framebuffer and some may
55	DRM_DEBUG("offset fixed up to 0x%x\n", off);	55	* assume the AGP aperture it appended to the framebuffer, so we
56		56	* try to detect those cases and fix them up.
57	if (off < dev_priv->fb_location \|\|	57	*
58	off >= (dev_priv->gart_vm_start + dev_priv->gart_size))	58	* Note: It might be a good idea here to make sure the offset lands
59	return DRM_ERR(EINVAL);	59	* in some "allowed" area to protect things like the PCIE GART...
60		60	*/
61	*offset = off;	61
62		62	/* First, the best case, the offset already lands in either the
63	return 0;	63	* framebuffer or the GART mapped space
		64	*/
		65	if ((off >= dev_priv->fb_location &&
		66	off < (dev_priv->fb_location + dev_priv->fb_size)) \|\|
		67	(off >= dev_priv->gart_vm_start &&
		68	off < (dev_priv->gart_vm_start + dev_priv->gart_size)))
		69	return 0;
		70
		71	/* Ok, that didn't happen... now check if we have a zero based
		72	* offset that fits in the framebuffer + gart space, apply the
		73	* magic offset we get from SETPARAM or calculated from fb_location
		74	*/
		75	if (off < (dev_priv->fb_size + dev_priv->gart_size)) {
		76	radeon_priv = filp_priv->driver_priv;
		77	off += radeon_priv->radeon_fb_delta;
		78	}
		79
		80	/* Finally, assume we aimed at a GART offset if beyond the fb */
		81	if (off > (dev_priv->fb_location + dev_priv->fb_size))
		82	off = off - (dev_priv->fb_location + dev_priv->fb_size) +
		83	dev_priv->gart_vm_start;
		84
		85	/* Now recheck and fail if out of bounds */
		86	if ((off >= dev_priv->fb_location &&
		87	off < (dev_priv->fb_location + dev_priv->fb_size)) \|\|
		88	(off >= dev_priv->gart_vm_start &&
		89	off < (dev_priv->gart_vm_start + dev_priv->gart_size))) {
		90	DRM_DEBUG("offset fixed up to 0x%x\n", off);
		91	*offset = off;
		92	return 0;
		93	}
		94	return DRM_ERR(EINVAL);
64	}	95	}
65		96
66	static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t *	97	static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t *
Lines 3012-3017 Link Here
3012	case RADEON_SETPARAM_PCIGART_LOCATION:	3043	case RADEON_SETPARAM_PCIGART_LOCATION:
3013	dev_priv->pcigart_offset = sp.value;	3044	dev_priv->pcigart_offset = sp.value;
3014	break;	3045	break;
		3046	case RADEON_SETPARAM_NEW_MEMMAP:
		3047	dev_priv->new_memmap = sp.value;
		3048	break;
3015	default:	3049	default:
3016	DRM_DEBUG("Invalid parameter %d\n", sp.param);	3050	DRM_DEBUG("Invalid parameter %d\n", sp.param);
3017	return DRM_ERR(EINVAL);	3051	return DRM_ERR(EINVAL);