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Lines 292-310
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| 292 |
{ |
292 |
{ |
| 293 |
RADEONInfoPtr info = RADEONPTR(pScrn); |
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RADEONInfoPtr info = RADEONPTR(pScrn); |
| 294 |
unsigned char *RADEONMMIO = info->MMIO; |
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unsigned char *RADEONMMIO = info->MMIO; |
| 295 |
int pitch64; |
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| 296 |
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RADEONTRACE(("EngineRestore (%d/%d)\n", |
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RADEONTRACE(("EngineRestore (%d/%d)\n", |
| 298 |
info->CurrentLayout.pixel_code, |
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info->CurrentLayout.pixel_code, |
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info->CurrentLayout.bitsPerPixel)); |
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info->CurrentLayout.bitsPerPixel)); |
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RADEONWaitForFifo(pScrn, 1); |
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/* Setup engine location. This shouldn't be necessary since we |
| 302 |
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* set them appropriately before any accel ops, but let's avoid |
| 303 |
pitch64 = ((pScrn->displayWidth * (pScrn->bitsPerPixel / 8) + 0x3f)) >> 6; |
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* random bogus DMA in case we inadvertently trigger the engine |
| 304 |
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* in the wrong place (happened). |
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/* RADEONWaitForFifo(pScrn, 2); |
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*/ |
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RADEONWaitForFifo(pScrn, 2); |
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OUTREG(RADEON_DST_PITCH_OFFSET, info->dst_pitch_offset); |
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OUTREG(RADEON_DST_PITCH_OFFSET, info->dst_pitch_offset); |
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OUTREG(RADEON_SRC_PITCH_OFFSET, info->dst_pitch_offset);*/ |
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OUTREG(RADEON_SRC_PITCH_OFFSET, info->dst_pitch_offset); |
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RADEONWaitForFifo(pScrn, 1); |
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RADEONWaitForFifo(pScrn, 1); |
| 310 |
#if X_BYTE_ORDER == X_BIG_ENDIAN |
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#if X_BYTE_ORDER == X_BIG_ENDIAN |
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Lines 326-334
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| 326 |
| RADEON_GMC_BRUSH_SOLID_COLOR |
326 |
| RADEON_GMC_BRUSH_SOLID_COLOR |
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| RADEON_GMC_SRC_DATATYPE_COLOR)); |
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| RADEON_GMC_SRC_DATATYPE_COLOR)); |
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| 329 |
RADEONWaitForFifo(pScrn, 7); |
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RADEONWaitForFifo(pScrn, 5); |
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OUTREG(RADEON_DST_LINE_START, 0); |
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| 331 |
OUTREG(RADEON_DST_LINE_END, 0); |
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OUTREG(RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); |
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OUTREG(RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); |
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OUTREG(RADEON_DP_BRUSH_BKGD_CLR, 0x00000000); |
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OUTREG(RADEON_DP_BRUSH_BKGD_CLR, 0x00000000); |
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OUTREG(RADEON_DP_SRC_FRGD_CLR, 0xffffffff); |
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OUTREG(RADEON_DP_SRC_FRGD_CLR, 0xffffffff); |