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Lines 1829-1834
Link Here
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| 1829 |
pll->xclk = RADEON_BIOS16(pll_info_block + 0x08); |
1829 |
pll->xclk = RADEON_BIOS16(pll_info_block + 0x08); |
| 1830 |
} |
1830 |
} |
| 1831 |
|
1831 |
|
|
|
1832 |
if (info->ChipFamily == CHIP_FAMILY_RV100 && !info->HasCRTC2) { |
| 1833 |
/* Avoid RN50 corruption due to memory bandwidth starvation. |
| 1834 |
* 18 is an empirical value based on the databook and Windows driver. |
| 1835 |
*/ |
| 1836 |
pll->max_pll_freq = min(pll->max_pll_freq, |
| 1837 |
18 * info->mclk * 100 / pScrn->bitsPerPixel * |
| 1838 |
info->RamWidth / 16); |
| 1839 |
} |
| 1840 |
|
| 1832 |
/* (Some?) Radeon BIOSes seem too lie about their minimum dot |
1841 |
/* (Some?) Radeon BIOSes seem too lie about their minimum dot |
| 1833 |
* clocks. Allow users to override the detected minimum dot clock |
1842 |
* clocks. Allow users to override the detected minimum dot clock |
| 1834 |
* value (e.g., and allow it to be suitable for TV sets). |
1843 |
* value (e.g., and allow it to be suitable for TV sets). |
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Lines 1969-1974
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| 1969 |
(info->ChipFamily == CHIP_FAMILY_RS200)){ |
1978 |
(info->ChipFamily == CHIP_FAMILY_RS200)){ |
| 1970 |
if (tmp & RV100_HALF_MODE) info->RamWidth = 32; |
1979 |
if (tmp & RV100_HALF_MODE) info->RamWidth = 32; |
| 1971 |
else info->RamWidth = 64; |
1980 |
else info->RamWidth = 64; |
|
|
1981 |
if (!info->HasCRTC2) { |
| 1982 |
info->RamWidth /= 4; |
| 1983 |
info->IsDDR = TRUE; |
| 1984 |
} |
| 1972 |
} else { |
1985 |
} else { |
| 1973 |
if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) info->RamWidth = 128; |
1986 |
if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) info->RamWidth = 128; |
| 1974 |
else info->RamWidth = 64; |
1987 |
else info->RamWidth = 64; |
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Lines 2035-2044
Link Here
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| 2035 |
info->ChipFamily = CHIP_FAMILY_RV100; |
2048 |
info->ChipFamily = CHIP_FAMILY_RV100; |
| 2036 |
break; |
2049 |
break; |
| 2037 |
|
2050 |
|
| 2038 |
case PCI_CHIP_RV100_QY: |
|
|
| 2039 |
case PCI_CHIP_RV100_QZ: |
| 2040 |
case PCI_CHIP_RN50_515E: /* RN50 is based on the RV100 but 3D isn't guaranteed to work. YMMV. */ |
2051 |
case PCI_CHIP_RN50_515E: /* RN50 is based on the RV100 but 3D isn't guaranteed to work. YMMV. */ |
| 2041 |
case PCI_CHIP_RN50_5969: |
2052 |
case PCI_CHIP_RN50_5969: |
|
|
2053 |
info->HasCRTC2 = FALSE; |
| 2054 |
case PCI_CHIP_RV100_QY: |
| 2055 |
case PCI_CHIP_RV100_QZ: |
| 2042 |
info->ChipFamily = CHIP_FAMILY_RV100; |
2056 |
info->ChipFamily = CHIP_FAMILY_RV100; |
| 2043 |
|
2057 |
|
| 2044 |
/* DELL triple-head configuration. */ |
2058 |
/* DELL triple-head configuration. */ |