|
Lines 176-183
static void ahci_scr_write (struct ata_p
Link Here
|
| 176 |
static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); |
176 |
static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); |
| 177 |
static int ahci_qc_issue(struct ata_queued_cmd *qc); |
177 |
static int ahci_qc_issue(struct ata_queued_cmd *qc); |
| 178 |
static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs); |
178 |
static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs); |
| 179 |
static void ahci_start_engine(struct ata_port *ap); |
179 |
static int ahci_start_engine(void __iomem *port_mmio); |
| 180 |
static int ahci_stop_engine(struct ata_port *ap); |
180 |
static int ahci_stop_engine(void __iomem *port_mmio); |
|
|
181 |
static int ahci_stop_fis_rx(void __iomem *port_mmio); |
| 182 |
static void ahci_start_fis_rx(void __iomem *port_mmio, |
| 183 |
struct ahci_port_priv *pp, |
| 184 |
struct ahci_host_priv *hpriv); |
| 181 |
static void ahci_phy_reset(struct ata_port *ap); |
185 |
static void ahci_phy_reset(struct ata_port *ap); |
| 182 |
static void ahci_irq_clear(struct ata_port *ap); |
186 |
static void ahci_irq_clear(struct ata_port *ap); |
| 183 |
static void ahci_eng_timeout(struct ata_port *ap); |
187 |
static void ahci_eng_timeout(struct ata_port *ap); |
|
Lines 331-337
static void ahci_host_stop(struct ata_ho
Link Here
|
| 331 |
static int ahci_port_start(struct ata_port *ap) |
335 |
static int ahci_port_start(struct ata_port *ap) |
| 332 |
{ |
336 |
{ |
| 333 |
struct device *dev = ap->host_set->dev; |
337 |
struct device *dev = ap->host_set->dev; |
|
|
338 |
struct ahci_host_priv *hpriv = ap->host_set->private_data; |
| 334 |
struct ahci_port_priv *pp; |
339 |
struct ahci_port_priv *pp; |
|
|
340 |
void __iomem *mmio = ap->host_set->mmio_base; |
| 341 |
void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
| 335 |
void *mem; |
342 |
void *mem; |
| 336 |
dma_addr_t mem_dma; |
343 |
dma_addr_t mem_dma; |
| 337 |
|
344 |
|
|
Lines 378-387
static int ahci_port_start(struct ata_po
Link Here
|
| 378 |
ap->private_data = pp; |
385 |
ap->private_data = pp; |
| 379 |
|
386 |
|
| 380 |
/* |
387 |
/* |
| 381 |
* Internal structures are initialized, |
388 |
* Enable FIS reception |
| 382 |
* we can now do a simple resume() |
389 |
*/ |
|
|
390 |
ahci_start_fis_rx(port_mmio, pp, hpriv); |
| 391 |
|
| 392 |
/* |
| 393 |
* We must not enable DMA here; |
| 394 |
* according to the spec this should |
| 395 |
* only be done after ports have been |
| 396 |
* probed. |
| 383 |
*/ |
397 |
*/ |
| 384 |
ahci_port_resume(ap); |
|
|
| 385 |
|
398 |
|
| 386 |
return 0; |
399 |
return 0; |
| 387 |
} |
400 |
} |
|
Lines 393-445
static void ahci_port_resume(struct ata_
Link Here
|
| 393 |
void *port_mmio = ahci_port_base(mmio, ap->port_no); |
406 |
void *port_mmio = ahci_port_base(mmio, ap->port_no); |
| 394 |
struct ahci_host_priv *hpriv = ap->host_set->private_data; |
407 |
struct ahci_host_priv *hpriv = ap->host_set->private_data; |
| 395 |
struct ahci_port_priv *pp = ap->private_data; |
408 |
struct ahci_port_priv *pp = ap->private_data; |
|
|
409 |
int rc; |
| 396 |
|
410 |
|
| 397 |
if (hpriv->cap & HOST_CAP_64) |
411 |
/* |
| 398 |
writel((pp->cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI); |
412 |
* Enable FIS reception |
| 399 |
writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); |
413 |
*/ |
| 400 |
readl(port_mmio + PORT_LST_ADDR); /* flush */ |
414 |
ahci_start_fis_rx(port_mmio, pp, hpriv); |
| 401 |
|
|
|
| 402 |
if (hpriv->cap & HOST_CAP_64) |
| 403 |
writel((pp->rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI); |
| 404 |
writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); |
| 405 |
readl(port_mmio + PORT_FIS_ADDR); /* flush */ |
| 406 |
|
| 407 |
writel(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX | |
| 408 |
PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP, |
| 409 |
port_mmio + PORT_CMD); |
| 410 |
readl(port_mmio + PORT_CMD); /* flush */ |
| 411 |
|
415 |
|
| 412 |
ahci_start_engine(ap); |
416 |
/* |
|
|
417 |
* Enable DMA |
| 418 |
*/ |
| 419 |
rc = ahci_start_engine(port_mmio); |
| 420 |
if (rc) |
| 421 |
printk(KERN_WARNING "ata%d: cannot start DMA engine (rc %d)\n", |
| 422 |
ap->id, rc); |
| 413 |
} |
423 |
} |
| 414 |
|
424 |
|
| 415 |
static void ahci_port_suspend(struct ata_port *ap) |
425 |
static void ahci_port_suspend(struct ata_port *ap) |
| 416 |
{ |
426 |
{ |
| 417 |
void *mmio = ap->host_set->mmio_base; |
427 |
void *mmio = ap->host_set->mmio_base; |
| 418 |
void *port_mmio = ahci_port_base(mmio, ap->port_no); |
428 |
void *port_mmio = ahci_port_base(mmio, ap->port_no); |
| 419 |
u32 tmp; |
429 |
int rc; |
| 420 |
int work; |
|
|
| 421 |
|
| 422 |
ahci_stop_engine(ap); |
| 423 |
|
430 |
|
| 424 |
/* |
431 |
/* |
| 425 |
* Disable FIS reception |
432 |
* Disable DMA |
| 426 |
*/ |
433 |
*/ |
| 427 |
tmp = readl(port_mmio + PORT_CMD); |
434 |
rc = ahci_stop_engine(port_mmio); |
| 428 |
tmp &= ~(PORT_CMD_FIS_RX); |
435 |
if (rc) { |
| 429 |
writel(tmp, port_mmio + PORT_CMD); |
436 |
printk(KERN_WARNING "ata%u: DMA engine busy (rc %d)\n", |
| 430 |
readl(port_mmio + PORT_CMD); /* flush */ |
437 |
ap->id, rc); |
|
|
438 |
return; |
| 439 |
} |
| 431 |
|
440 |
|
| 432 |
/* |
441 |
/* |
| 433 |
* Wait for HBA to acknowledge. |
442 |
* Disable FIS reception |
| 434 |
* This could be as long as 500 msec |
|
|
| 435 |
*/ |
443 |
*/ |
| 436 |
work = 1000; |
444 |
rc = ahci_stop_fis_rx(port_mmio); |
| 437 |
while (work-- > 0) { |
445 |
if (rc) |
| 438 |
tmp = readl(port_mmio + PORT_CMD); |
446 |
printk(KERN_WARNING "ata%d: FIS RX still running (rc %d)\n", |
| 439 |
if ((tmp & PORT_CMD_FIS_ON) == 0) |
447 |
ap->id, rc); |
| 440 |
break; |
|
|
| 441 |
udelay(10); |
| 442 |
} |
| 443 |
} |
448 |
} |
| 444 |
|
449 |
|
| 445 |
static void ahci_port_stop(struct ata_port *ap) |
450 |
static void ahci_port_stop(struct ata_port *ap) |
|
Lines 504-510
static void ahci_phy_reset(struct ata_po
Link Here
|
| 504 |
tmp = readl(port_mmio + PORT_SCR_ERR); |
509 |
tmp = readl(port_mmio + PORT_SCR_ERR); |
| 505 |
writel(tmp, port_mmio + PORT_SCR_ERR); |
510 |
writel(tmp, port_mmio + PORT_SCR_ERR); |
| 506 |
|
511 |
|
| 507 |
ahci_start_engine(ap); |
512 |
ahci_start_engine(port_mmio); |
| 508 |
|
513 |
|
| 509 |
if (ap->flags & ATA_FLAG_PORT_DISABLED) |
514 |
if (ap->flags & ATA_FLAG_PORT_DISABLED) |
| 510 |
return; |
515 |
return; |
|
Lines 604-651
static void ahci_qc_prep(struct ata_queu
Link Here
|
| 604 |
ahci_fill_sg(qc); |
609 |
ahci_fill_sg(qc); |
| 605 |
} |
610 |
} |
| 606 |
|
611 |
|
| 607 |
static void ahci_start_engine(struct ata_port *ap) |
612 |
static int ahci_start_engine(void __iomem *port_mmio) |
| 608 |
{ |
613 |
{ |
| 609 |
void __iomem *mmio = ap->host_set->mmio_base; |
|
|
| 610 |
void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
| 611 |
u32 tmp; |
614 |
u32 tmp; |
| 612 |
int work; |
615 |
int work = 1000; |
| 613 |
|
616 |
|
|
|
617 |
/* |
| 618 |
* Get current status |
| 619 |
*/ |
| 614 |
tmp = readl(port_mmio + PORT_CMD); |
620 |
tmp = readl(port_mmio + PORT_CMD); |
|
|
621 |
|
| 615 |
/* |
622 |
/* |
| 616 |
* AHCI rev 1.1 section 10.3.1: |
623 |
* AHCI rev 1.1 section 10.3.1: |
| 617 |
* Software shall not set PxCMD.ST to ‘1’ until it verifies |
624 |
* Software shall not set PxCMD.ST to ‘1’ until it verifies |
| 618 |
* that PxCMD.CR is ‘0’ and has set PxCMD.FRE to ‘1’. |
625 |
* that PxCMD.CR is ‘0’ and has set PxCMD.FRE to ‘1’. |
| 619 |
*/ |
626 |
*/ |
| 620 |
if ((tmp & PORT_CMD_FIS_RX) == 0) |
627 |
if ((tmp & PORT_CMD_FIS_RX) == 0) |
| 621 |
printk(KERN_WARNING "ata%d: dma not running\n",ap->id); |
628 |
return -EPERM; |
|
|
629 |
|
| 622 |
/* |
630 |
/* |
| 623 |
* wait for engine to become idle. |
631 |
* wait for engine to become idle. |
| 624 |
*/ |
632 |
*/ |
| 625 |
work = 1000; |
633 |
while (work-- > 0 && ((tmp & PORT_CMD_LIST_ON) == 0)) { |
| 626 |
while (work-- > 0) { |
|
|
| 627 |
tmp = readl(port_mmio + PORT_CMD); |
634 |
tmp = readl(port_mmio + PORT_CMD); |
| 628 |
if ((tmp & PORT_CMD_LIST_ON) == 0) |
|
|
| 629 |
break; |
| 630 |
udelay(10); |
635 |
udelay(10); |
| 631 |
} |
636 |
} |
| 632 |
|
637 |
|
|
|
638 |
if (!work) { |
| 639 |
/* |
| 640 |
* We need to do a port reset / HBA reset here |
| 641 |
*/ |
| 642 |
return -EBUSY; |
| 643 |
} |
| 644 |
|
| 633 |
/* |
645 |
/* |
| 634 |
* Start DMA |
646 |
* Start DMA |
| 635 |
*/ |
647 |
*/ |
| 636 |
tmp |= PORT_CMD_START; |
648 |
tmp |= PORT_CMD_START; |
| 637 |
writel(tmp, port_mmio + PORT_CMD); |
649 |
writel(tmp, port_mmio + PORT_CMD); |
| 638 |
readl(port_mmio + PORT_CMD); /* flush */ |
650 |
readl(port_mmio + PORT_CMD); /* flush */ |
|
|
651 |
|
| 652 |
return 0; |
| 639 |
} |
653 |
} |
| 640 |
|
654 |
|
| 641 |
static int ahci_stop_engine(struct ata_port *ap) |
655 |
static int ahci_stop_engine(void __iomem *port_mmio) |
| 642 |
{ |
656 |
{ |
| 643 |
void __iomem *mmio = ap->host_set->mmio_base; |
|
|
| 644 |
void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
| 645 |
int work; |
657 |
int work; |
| 646 |
u32 tmp; |
658 |
u32 tmp; |
| 647 |
|
659 |
|
| 648 |
tmp = readl(port_mmio + PORT_CMD); |
660 |
tmp = readl(port_mmio + PORT_CMD); |
|
|
661 |
/* Check if the HBA is idle */ |
| 662 |
if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0) |
| 663 |
return 0; |
| 664 |
|
| 665 |
/* Setting HBA to idle */ |
| 649 |
tmp &= ~PORT_CMD_START; |
666 |
tmp &= ~PORT_CMD_START; |
| 650 |
writel(tmp, port_mmio + PORT_CMD); |
667 |
writel(tmp, port_mmio + PORT_CMD); |
| 651 |
|
668 |
|
|
Lines 663-679
static int ahci_stop_engine(struct ata_p
Link Here
|
| 663 |
return -EIO; |
680 |
return -EIO; |
| 664 |
} |
681 |
} |
| 665 |
|
682 |
|
|
|
683 |
static int ahci_stop_fis_rx(void __iomem *port_mmio) |
| 684 |
{ |
| 685 |
u32 tmp; |
| 686 |
int work = 1000; |
| 687 |
|
| 688 |
/* |
| 689 |
* Get current status |
| 690 |
*/ |
| 691 |
tmp = readl(port_mmio + PORT_CMD); |
| 692 |
|
| 693 |
/* Check if FIS RX is already disabled */ |
| 694 |
if ((tmp & PORT_CMD_FIS_RX) == 0) |
| 695 |
return 0; |
| 696 |
|
| 697 |
/* |
| 698 |
* AHCI Rev 1.1 section 10.3.2 |
| 699 |
* Software shall not clear PxCMD.FRE while |
| 700 |
* PxCMD.ST or PxCMD.CR is set to ‘1’. |
| 701 |
*/ |
| 702 |
if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_START)) { |
| 703 |
return -EPERM; |
| 704 |
} |
| 705 |
|
| 706 |
/* |
| 707 |
* Disable FIS reception |
| 708 |
* |
| 709 |
* AHCI Rev 1.1 Section 10.1.2: |
| 710 |
* If PxCMD.FRE is set to '1', software should clear it |
| 711 |
* to '0' and wait at least 500 milliseconds for PxCMD.FR |
| 712 |
* to return '0' when read. If PxCMD.FR does not clear |
| 713 |
* '0' correctly, then software may attempt a port reset |
| 714 |
* or a full HBA reset to recover. |
| 715 |
*/ |
| 716 |
tmp &= ~(PORT_CMD_FIS_RX); |
| 717 |
writel(tmp, port_mmio + PORT_CMD); |
| 718 |
|
| 719 |
mdelay(100); |
| 720 |
work = 1000; |
| 721 |
while (work-- > 0) { |
| 722 |
tmp = readl(port_mmio + PORT_CMD); |
| 723 |
if ((tmp & PORT_CMD_FIS_ON) == 0) |
| 724 |
return 0; |
| 725 |
udelay(10); |
| 726 |
} |
| 727 |
|
| 728 |
return -EBUSY; |
| 729 |
} |
| 730 |
|
| 731 |
static void ahci_start_fis_rx(void __iomem *port_mmio, |
| 732 |
struct ahci_port_priv *pp, |
| 733 |
struct ahci_host_priv *hpriv) |
| 734 |
{ |
| 735 |
/* |
| 736 |
* Enable FIS reception |
| 737 |
*/ |
| 738 |
if (hpriv->cap & HOST_CAP_64) |
| 739 |
writel((pp->cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI); |
| 740 |
writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); |
| 741 |
readl(port_mmio + PORT_LST_ADDR); /* flush */ |
| 742 |
|
| 743 |
if (hpriv->cap & HOST_CAP_64) |
| 744 |
writel((pp->rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI); |
| 745 |
writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); |
| 746 |
readl(port_mmio + PORT_FIS_ADDR); /* flush */ |
| 747 |
|
| 748 |
/* |
| 749 |
* This is wrong. We should only activate |
| 750 |
* FIS_RX here; everything else should be handled |
| 751 |
* separately. |
| 752 |
* Some bits might not even be settable here |
| 753 |
* as they depend on the respective feature to be |
| 754 |
* implemented (Staggered Spin-up, |
| 755 |
* Cold-presence detection etc.) |
| 756 |
*/ |
| 757 |
writel(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX | |
| 758 |
PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP, |
| 759 |
port_mmio + PORT_CMD); |
| 760 |
readl(port_mmio + PORT_CMD); /* flush */ |
| 761 |
} |
| 762 |
|
| 666 |
static void ahci_restart_port(struct ata_port *ap, u32 irq_stat) |
763 |
static void ahci_restart_port(struct ata_port *ap, u32 irq_stat) |
| 667 |
{ |
764 |
{ |
| 668 |
void *mmio = ap->host_set->mmio_base; |
765 |
void *mmio = ap->host_set->mmio_base; |
| 669 |
void *port_mmio = ahci_port_base(mmio, ap->port_no); |
766 |
void *port_mmio = ahci_port_base(mmio, ap->port_no); |
| 670 |
u32 tmp; |
767 |
u32 tmp; |
|
|
768 |
int rc; |
| 671 |
|
769 |
|
| 672 |
if ((ap->device[0].class != ATA_DEV_ATAPI) || |
770 |
if ((ap->device[0].class != ATA_DEV_ATAPI) || |
| 673 |
((irq_stat & PORT_IRQ_TF_ERR) == 0)) |
771 |
((irq_stat & PORT_IRQ_TF_ERR) == 0)) |
| 674 |
ahci_dump_port_status(ap, irq_stat, "port reset"); |
772 |
ahci_dump_port_status(ap, irq_stat, "port reset"); |
| 675 |
|
773 |
|
| 676 |
ahci_stop_engine(ap); |
774 |
rc = ahci_stop_engine(port_mmio); |
| 677 |
|
775 |
|
| 678 |
/* clear SATA phy error, if any */ |
776 |
/* clear SATA phy error, if any */ |
| 679 |
tmp = readl(port_mmio + PORT_SCR_ERR); |
777 |
tmp = readl(port_mmio + PORT_SCR_ERR); |
|
Lines 683-689
static void ahci_restart_port(struct ata
Link Here
|
| 683 |
* if so, issue COMRESET |
781 |
* if so, issue COMRESET |
| 684 |
*/ |
782 |
*/ |
| 685 |
tmp = readl(port_mmio + PORT_TFDATA); |
783 |
tmp = readl(port_mmio + PORT_TFDATA); |
| 686 |
if (tmp & (ATA_BUSY | ATA_DRQ)) { |
784 |
if (rc || (tmp & (ATA_BUSY | ATA_DRQ))) { |
| 687 |
writel(0x301, port_mmio + PORT_SCR_CTL); |
785 |
writel(0x301, port_mmio + PORT_SCR_CTL); |
| 688 |
readl(port_mmio + PORT_SCR_CTL); /* flush */ |
786 |
readl(port_mmio + PORT_SCR_CTL); /* flush */ |
| 689 |
udelay(10); |
787 |
udelay(10); |
|
Lines 691-697
static void ahci_restart_port(struct ata
Link Here
|
| 691 |
readl(port_mmio + PORT_SCR_CTL); /* flush */ |
789 |
readl(port_mmio + PORT_SCR_CTL); /* flush */ |
| 692 |
} |
790 |
} |
| 693 |
|
791 |
|
| 694 |
ahci_start_engine(ap); |
792 |
/* re-start DMA */ |
|
|
793 |
rc = ahci_start_engine(port_mmio); |
| 794 |
if (rc) |
| 795 |
printk(KERN_WARNING "ata%u: cannot start DMA (rc %d)\n", |
| 796 |
ap->id, rc); |
| 695 |
} |
797 |
} |
| 696 |
|
798 |
|
| 697 |
static void ahci_eng_timeout(struct ata_port *ap) |
799 |
static void ahci_eng_timeout(struct ata_port *ap) |
|
Lines 910-916
static int ahci_host_init(struct ata_pro
Link Here
|
| 910 |
hpriv->port_map = readl(mmio + HOST_PORTS_IMPL); |
1012 |
hpriv->port_map = readl(mmio + HOST_PORTS_IMPL); |
| 911 |
probe_ent->n_ports = (hpriv->cap & 0x1f) + 1; |
1013 |
probe_ent->n_ports = (hpriv->cap & 0x1f) + 1; |
| 912 |
|
1014 |
|
| 913 |
VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n", |
1015 |
DPRINTK("cap 0x%x port_map 0x%x n_ports %d\n", |
| 914 |
hpriv->cap, hpriv->port_map, probe_ent->n_ports); |
1016 |
hpriv->cap, hpriv->port_map, probe_ent->n_ports); |
| 915 |
|
1017 |
|
| 916 |
using_dac = hpriv->cap & HOST_CAP_64; |
1018 |
using_dac = hpriv->cap & HOST_CAP_64; |
|
Lines 1110-1120
static int ahci_init_one (struct pci_dev
Link Here
|
| 1110 |
printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n"); |
1212 |
printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n"); |
| 1111 |
|
1213 |
|
| 1112 |
rc = pci_enable_device(pdev); |
1214 |
rc = pci_enable_device(pdev); |
| 1113 |
if (rc) |
1215 |
if (rc) { |
|
|
1216 |
printk(KERN_ERR DRV_NAME "(%s): cannot enable PCI device\n", |
| 1217 |
pci_name(pdev)); |
| 1114 |
return rc; |
1218 |
return rc; |
|
|
1219 |
} |
| 1115 |
|
1220 |
|
| 1116 |
rc = pci_request_regions(pdev, DRV_NAME); |
1221 |
rc = pci_request_regions(pdev, DRV_NAME); |
| 1117 |
if (rc) { |
1222 |
if (rc) { |
|
|
1223 |
printk(KERN_ERR DRV_NAME "(%s): cannot request PCI regions\n", |
| 1224 |
pci_name(pdev)); |
| 1118 |
pci_dev_busy = 1; |
1225 |
pci_dev_busy = 1; |
| 1119 |
goto err_out; |
1226 |
goto err_out; |
| 1120 |
} |
1227 |
} |
|
Lines 1139-1144
static int ahci_init_one (struct pci_dev
Link Here
|
| 1139 |
mmio_base = ioremap(pci_resource_start(pdev, AHCI_PCI_BAR), |
1246 |
mmio_base = ioremap(pci_resource_start(pdev, AHCI_PCI_BAR), |
| 1140 |
pci_resource_len(pdev, AHCI_PCI_BAR)); |
1247 |
pci_resource_len(pdev, AHCI_PCI_BAR)); |
| 1141 |
if (mmio_base == NULL) { |
1248 |
if (mmio_base == NULL) { |
|
|
1249 |
printk(KERN_ERR DRV_NAME "(%s): cannot ioremap PCI %lu mmio space at 0x%lx\n", |
| 1250 |
pci_name(pdev), pci_resource_start(pdev, AHCI_PCI_BAR), |
| 1251 |
pci_resource_len(pdev, AHCI_PCI_BAR)); |
| 1142 |
rc = -ENOMEM; |
1252 |
rc = -ENOMEM; |
| 1143 |
goto err_out_free_ent; |
1253 |
goto err_out_free_ent; |
| 1144 |
} |
1254 |
} |