Bug 132736 (CVE-2005-3105)

Summary: VUL-0: CVE-2005-3105: kernel: cache coherency issues on IA64/Montecito
Product: [Novell Products] SUSE Security Incidents Reporter: Marcus Meissner <meissner>
Component: IncidentsAssignee: Andreas Schwab <schwab>
Status: RESOLVED DUPLICATE QA Contact: Security Team bot <security-team>
Severity: Normal    
Priority: P5 - None CC: gp, security-team
Version: unspecified   
Target Milestone: ---   
Hardware: Other   
OS: Other   
Whiteboard: CVE-2005-3105: CVSS v2 Base Score: 2.1 (AV:L/AC:L/Au:N/C:N/I:N/A:P)
Found By: Other Services Priority:
Business Priority: Blocker: ---
Marketing QA Status: --- IT Deployment: ---

Description Marcus Meissner 2005-11-08 16:10:22 UTC 
just found this at Mitre ... In case you did not know yet.

CVE-2005-3105

The mprotect code (mprotect.c) in Linux 2.6 on Itanium IA64 Montecito processors does not properly maintain cache coherency as required by the architecture, which allows local users to cause a denial of service and possibly corrupt data by modifying PTE protections.

MISC:http://www.intel.com/cd/ids/developer/asmo-na/eng/215766.htm 

MISC:http://cache-www.intel.com/cd/00/00/21/57/215792_215792.pdf 

CONFIRM:http://linux.bkbits.net:8080/linux-2.6/cset@4248d4019z8HvgrPAji51TKrWiV2uw?nav=index.htmlsrc/|src/mm|related/mm/mprotect.c
Comment 2 Andreas Schwab 2005-11-21 12:18:21 UTC 

*** This bug has been marked as a duplicate of 74103 ***
Comment 3 Thomas Biege 2009-10-13 21:48:52 UTC 
CVE-2005-3105: CVSS v2 Base Score: 2.1 (AV:L/AC:L/Au:N/C:N/I:N/A:P)